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Bandi Seminar

3D ICS
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0% found this document useful (0 votes)
11 views15 pages

Bandi Seminar

3D ICS
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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3d ic technology

By: VIVEK. BANDI


21X01A0489
Ece-B
CONTENT
S

 Introduction
 Background
 Limitation of 2D IC Performance
 3D Architecture
 Technology used to build 3D ICs
 Advantages of 3D IC
 Characteristics
 Challenges in 3D Circuit
 Conclusion
 Key Points
Introduction/Definition
A three-dimensional Integrated Circuit(3D IC) is a chip in which two
or more layers of active electronic components are integrated both
vertically and horizontally into a single circuit.

Fig:Schematic diagram of 3D integrated circuit.


Background

 Integrated circuits were first invented in the 1950,


 3D IC chip commercially used first back in 2004, psp
 3D ICs was a great mutation to decrease the total area of the
Integrated Circuit
 Improvements on 3D IC technology are expected to
dramatically enhance the
• Performance
• Functionality
• Device packaging density for micro-electro-mechanical
systems(MEMS) application
Limitation of 2D IC Performance

 Complexity of the chip Design


 Moore’s Law says that the number of transistors on a
microchip will double roughly every year
 Integrated circuits are hitting hard physical limits
 Losses within large interconnection
3D Architecture

Earliest known architect design of


the 3D IC Fabrication

Three-dimensional
integration to create multilayer
Concept for developing 3D IC

 Three-dimensional integration to create multilayer Si ICs is a


concept that can significantly improve interconnect
performance,
• Increase transistor packing density
• Reduce chip area and power dissipation
 3D ICs can be very effective large scale on chip integration of
different system.
 In 3D design architecture, an entire 2D chips is divided into a
number of blocks in placed on separate layers of Si stocked on
top of eachother.
 Each Si layer in 3D structure can have multiple layer of
interconnects
Technology Used to Build 3D ICs

DIE ON
DIE
 The electronic components are built on multiple dies,
 these dies are aligned and bonded together
 An advantage is that each component die can be tested first
Advantages of 3D IC

 The 3D architecture offers extra flexibility in system design


 The 3D chip design technology can be exploited to build SoCs
by placing circuits with different voltage and performance
requirements in different layers
 3D integration can be reduce the amount of wiring you use
• Reducing capacitances
• Power dissipation
• Chip area improves performance
 Less Complex and more cost effective.
Characteristics of 3D IC Performance

 Time
 Energy
Challenges in 3D IC

 Design challenges
 Thermal issues
 TSV induced overheads
 Cross talk between layers
CONCLUSION
Over all, 3D integration is a significant development
which have a major impact on how future electronic
systems are designed and used.
References
 Topol, A. W., Tulpe, L., Shi, L., Frank, D., Bernstein, K., &
Young, A. M. IBM Research group (2016, September).
Three-Dimensional Integrated Circuit. Retrieved April 4, 2020,
from https://signallake.com/innovation/topol.pdf
 https://www.sciencedirect.com/topics/engineering/three-dime
nsional-integrated-circuits
 https://gcn.com/articles/2020/01/06/2d-3d-integrated-circuits.
aspx
 https://www.seminarsonly.com/electronics/3-%20D%20ICs.php

 https://www.slideshare.net/mufeedulislam/3d-integrated-circui
ts
Key Points

 Design: 3D IC technology allows for design flexibility for


innovators.
 Functionality: Key process technology element being
optimized for the 3D IC enables the implementation of design
flexibility.
 Device Packaging density: Active devices can be stacked
and size of chip footprint can be reduced which adds
dimension to the conventional 2D device layout.
 Chip Performance: 3D technology enables the memory
arrays to be placed above or under logic circuitry, resulting in
an increased bandwidth.
 Wafer-scale fabrication: A wafer-level stacking of 3D ICs
potentially enables a more cost-effective solution than the
THANK YOU

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