CACHE

Prabhash Barman (Verification Trainee Engineer)

CONTENTS

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 CACHE DESIGN-OVERVIEW

1. BLOCK PLACEMENT : Where to place the Main Memory Blocks in the CACHE
2. BLOCK IDENTIFICATION : How to find the Main Memory Blocks in the CACHE
3. BLOCK REPLACEMENT : How to choose which entry to replace from CACHE,during
CACHE MISS
4. WRITE STRATEGY : How are the upgradations propogated

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 BLOCK REPLACEMENT

• CACHE is limited in size.

• Necessary when cache is full i.e Capacity Miss

• Necessary when potential match can’t be found

Compulsory Miss
Conflict Miss
• It’s basically replacing a BLOCK in cache with the new block request and move the replaced
BLOCK into the next level of hierarchy
eplc

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 BLOCK REPLACEMENT

• RANDOM REPLACEMENT :
o Evicts any block from CACHE at random.
o Access information is not needed
o Not Implemented

• FIFO :
o Evicts Block based on their arrival
o CACHE behaves as a First-In-First-Out queue.

• OPTIMAL REPLACEMENT :
o Evicts the block that won’t be referred for the longest period of time in future
o Prediction of Block Request is IMPOSSIBLE. So it can’t be implemented.

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BLOCK REPLACEMENT

• RECENCY BASED POLICIES

i. MOST RECENTLY USED(MRU)
o Evicts most recently referred blocks.
o Works well with cyclic patterns

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BLOCK REPLACEMENT

i. LEAST RECENTLY USED(LRU)

o Exploits Temporal Locality
o Evicts Least Recently referred Block
o Basically use AGE bits & makes sequences of AGE bits (AGE bits are use to keep
track of the order of access)
o HUGE OVERHEAD for CACHE with Higher Associativity

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BLOCK REPLACEMENT

i. PSEUDO LEAST RECENTLY USED(PLRU)

o It generates approx. measures for replacements
o Lesser bits are required. So implementation cost is reduced.

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 BLOCK REPLACEMENT

• Least Frequency Used

o Evicts least frequently referred block.
o Frequency is recorded for all blocks present in CACHE.

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CACHE

While playing larger games, we basically have large storage(Just like GTA-5
where we need 100GB of storage) but the MM required is small memory of
4,8gb is because at that time the computer doesn't bring thew whole data in
MM memory and there the concept of Virtual memory comes into picture

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CACHE ALGORITHM FOR LOADING

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CACHE
• LEVELS OF CACHE
o LEVEL 1 CACHE(L1) : Embedded into the processor itself and it’s the fastest
and smallest.
o LEVEL 2 CACHE(L2) : Before was embedded in motherboard. But now
incorporated in processor itself. It’s larger than L1 but slower than L1.
o LEVEL 3 CACHE(L3) : It is shared among all the cores of the Processor and is
the largest among the rest.
o Every core of the Processor will have it’s own L1 & L2. But L3 is shared among all.
o L2 can’t be incorporated in L1 because of the size

• LOCALITY OF REFERENCE
o SPATIAL LOCALITY
o TEMPORAL LOCALITY

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CACHE

In CACHE, the LINE size should be equal to the

BLOCK size i.e. LINE SIZE = BLOCK SIZE

WORD: Smallest Addressable Unit of Memory

BYTE Addressable Memory=1 WORD=1 Byte
To address 64 words, we need - logbase2(64)=6
bits(Physical Address Bits)

Offset : Addressing each word in the Block

Tag : Basically differentiate among the CACHE
lines
Line Number : Basically on which particular
LINE number of the CACHE memory

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BLOCK PLACEMENT : WHERE PLACE BLOCKS IN CACHE

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DIRECT MEMORY MAPPING

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DIRECT MEMORY MAPPING

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DIRECT MEMORY MAPPING

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DIRECT MEMORY MAPPING

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ASSOCIATIVE MAPPING

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ASSOCIATIVE MAPPING

• As the number of Comparators are being increased, the cost will increase
too and overall the hardware implementation is costly
• Also heating will increase due to the increased hardware.

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SET-ASSOCIATIVE MAPPING

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SET-ASSOCIATIVE MAPPING

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SET-ASSOCIATIVE MAPPING

• As in case of Associative Mapping, we have seen that the number of comparators were
higher(as the data can be placed at any cache line) in set-associative mapping the
number of comparators decreases due to the introduction of SET concept
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EXCLUSIVE ACCESS

• The master first issues an exclusive read to the shared memory location, signaling that it intends to perform an exclusive access.
This is indicated by the ARLOCK signal in the AXI read address channel, which is set to 1 for exclusive access.
Exclusi • The read returns the current value of the memory location to the master.
ve • At this point, the master does not yet have exclusive ownership of the memory location but intends to write to it.
Read
(ARLO
CK)

• After reading the data, the master performs a modification and then issues an exclusive write to the same memory location. The
Exclusi AWLOCK signal in the AXI write address channel is set to 1, indicating that the master is requesting an exclusive write.
• The slave checks whether any other master has accessed (read or written) this memory location since the exclusive read was issued.
ve
• The AWID should be same as of ARID which was there in exclusive read.
Write
(AWLO
CK)

• If no other master has accessed the memory location since the exclusive read, the exclusive write succeeds, and the slave
Write completes the write. It sends a write response (BRESP) of EXOKAY, indicating that the exclusive access was successful.
• If another master accessed the memory location between the exclusive read and the exclusive write, the exclusive write fails, and
Respo
the slave returns a write response (BRESP) of OKAY, indicating that the write was unsuccessful due to a lost exclusive access.
nse
(BRES
P)

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 QUALITY OF SERVICE and REGION SIGNALING

Quality of service
• The AXI 4 signal set is extended to support two 4-bit QoS identifiers:
1. AWQOS A 4-bit QoS identifier, sent on the write address channel for each write transaction.
2. ARQOS A 4-bit QoS identifier, sent on the read address channel for each read transaction.

• AxQOS is used as a priority indicator for the associated write or read transaction.

• A higher value indicates a higher priority transaction.

• A default value of 4'b0000 indicates that the interface is not participating in any QoS scheme.

Region Signaling
• AWREGION A region identifier, sent on the write address channel for each write transaction.

• ARREGION A region identifier, sent on the read address channel for each read transaction.

• The use of region identifiers means a single physical interface on a slave can provide multiple logical interfaces, each
with a different location in the system address map.

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USER SIGNALING

• AXI4 interface signal set can include a set of User-defined signals, called the User signals, on each
AXI4 channel.
AWUSER Write address channel User signals.
ARUSER Read address channel User signals.
WUSER Write data channel User signals.
RUSER Read data channel User signals.
BUSER Write response channel User signals.

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MEMORY ATTRIBUTE SIGNALING

• Cache memory is a small, high-speed memory located close to the CPU (central processing unit) that stores
frequently accessed.

• Cache coherence is a critical issue in multi-processor architectures, where multiple processors share a
common cache. Cache coherence ensures that all processors have the same view of cache data to prevent
data inconsistency.

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MEMORY ATTRIBUTE SIGNALING

• The ARCACHE and AWCACHE signals in AXI4 are used to define how a transaction interacts with memory in terms
of caching and buffering behavior.

• AxCACHE [0] (B) is the bufferable bit.

This bit controls whether the transaction can be buffered. Buffering allows data to be temporarily stored in a buffer
before it is processed, which can improve performance by allowing transactions to be processed out of order or at a
more convenient time.

•Bufferable = 1: The transaction can be buffered, meaning it does not need to be immediately written to or read from
memory. For writes, this allows the system to store the data temporarily and defer the actual write to memory,
improving system throughput.

•Bufferable = 0: The transaction cannot be buffered and must be handled immediately. This is useful in situations
where latency is critical, and the data needs to be written or read as soon as the request is made.

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MEMORY ATTRIBUTE SIGNALING

• AxCACHE [1] is the cacheable bit in AXI3, or the modifiable bit in AXI4.

• This bit indicates whether the data can be modified in the cache or whether it needs to be written directly to
memory when changed.

• Modifiable = 1 (Write-back): If this bit is set, the transaction can use a write-back cache policy. In a write-back
policy, the data can be written to the cache first, and then later written back to main memory when needed (e.g.,
when the cache line is evicted). This approach is typically used to reduce memory traffic and improve performance.

• Modifiable = 0 (Write-through): If this bit is cleared, the transaction uses a write-through cache policy. In a write-
through policy, any writes to the cache are immediately forwarded to the main memory as well. This approach
ensures that the main memory always holds the most up-to-date data, but it can introduce more memory traffic.

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MEMORY ATTRIBUTE SIGNALING

• AxCACHE [2] is the RA bit.

• For reads (ARCACHE): If this bit is set (read-allocate), the system can allocate a cache line when a read miss
occurs, meaning if the requested data is not in the cache, it will be brought into the cache for future
accesses.

• If either AxCACHE [2] or AxCACHE [3] is asserted, then the transaction must be looked up in a cache as it
could have been allocated in this cache by another master.

• AxCACHE [3] is the WA bit.

• For writes (AWCACHE): If this bit is set (write-allocate), the system can allocate a cache line for a write miss.
If the data being written is not currently in the cache, the cache will load the corresponding cache line from
memory, modify it, and then store it in the cache.

• If either AxCACHE [2] or AxCACHE [3] is asserted, then the transaction must be looked up in a cache as it
could have been allocated in this cache by another master.

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 Thank You.

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