Internal Use Only

AXI Inter Connect

INTRODUCTION
 AXI abbreviated as Advanced eXtensible Interface, part of AMBA(Advance Microcontroller
Bus Architecture ) family protocols.It connects one or more AXI master device to one or
more slave device.
 Key features:

1. It has separate address and data phases

2. It has separate read and write data channels which can provide low-cost
Direct Memory Access
3. It includes optional extensions that cover signaling for low power operation

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AXI Architecture

• AXI consist of five channels:

o Read Address

o Write Address

o Read Data

o Write Data

o Write Response

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AXI Architecture

• Address channel has control information

which describes the nature of the data to be
transferred.(Read address, Write address).
• Write channel: master  slave data transfer.
• Write response: slave uses this channel to
signal the completion of the transfer to
master in write transaction.
• Read channel: Slavemaster data transfer.

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Channel and Handshake process:
• All the five channel use the same VALID / READY handshake to transfer data
and control information
• VALID- indicates when a valid data or control information are available on the
channel(transmitter generates).
• READY-indicates when receiver can accept the data(receiver generates)
• This two-way flow enables both master and slave to control the rate at which the
data and control information moves.
• The transfer occurs when both the VALID and READY signals are HIGH.

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VALID before READY handshake

• Here,source presents the information after

T1 and asserts the VALID signal.
• After T2,destination asserts the READY
signal
• When assertion is recognized ,Source must
keep information stable until the transfer
occurs at T3.
• VALID is asserted it must remain asserted
until the handshake occurs at rising edge .
• At rising edge both VALID AND READY are
asserted.

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READY before VALID handshake

• After T1,destination is asserts before the

information is valid.
• After T2, sources presents the information
and asserts VALID
• AT t3,transfer occurs when this assertion is
recognized.Here transfer of information
occurs in single cycle.

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VALID with READY handshake

• After T1,both source and destination indicate

it can transfer information.
• At t2, assertion of both VALID and READY is
recognized.This indicates transfer occurs at
t2.

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Interface and Inter connect
System consist of master and slave devices connected together by means of Interconnect.Here by using AXI
interconnect multiple master and slave are connected

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DRAWBACK

The AMBA AXI4 has limitations with respect to the burst data of information to be
transferred this limits the number of address that a slave must support.

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 Internal Use Only

APB
INTRODUCTION
• APB abbreviated as Advance Peripheral Bus , part of AMBA(Advance
Microcontroller Bus Architecture ) family protocols.
• Key features:
1.low cost interface
2.minimal power consumption
3.reduced interface complexity
4.Non-pipelined protocol so it used to connect to low-bandwidth
peripherals.
5.Relates a signal transition to the rising edge of the clock.
6.Every transfer takes at least two cycles(SETUP cycle and ACCESS
cycle).
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Block diagram

• The ARM processor and other components

are connected to AHB.
• The other low bandwidth peripherals like
UART,Timer are connected using APB.
• Both are connected by APB bridge which act
as master.AHB slvae corresponds system.

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TRANSFERS-Write transfer
• Two types:
1.with no wait states
2.without no wait states

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With no wait states

• At T1,a write transfer starts with

PADDR,PWDATA,PWRITE and PSEL are
being registered at the rising edge of PCLK.
(SETUP PHASE)
• At T2, PENABLE and PREADY signals are
registered at the rising edge of the PCLK.
• AT t3, the address PADDR write data
PWDATA and control signals all remain valid
until the transfer completes.(END OF
ACCESS PHASE)
• Next the PENABLE and PSEL signal is
deasserted unless the transfer is followed
immediately by another transfer to the same
peripheral.

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With wait states

• The transfers are same as with no wait states it differs in

a way that the slave can use PREADY signal to extend
the transfer.
• During the Access phase,When PENABLE is HIGH the
slave extends the transfer by keeping PREADY LOW.
• When keeping PREADY LOW the signals which are not
changed are:
1. PADDR

2.PWRITE
3. PSEL
4.PENABLE
5.PWDATA
6.PSTRB
7.PPROT

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WRITE STROBES
• The write strobe signals enable data transfer on write data bus.
• For write transfers the bus master drive all the bits of PSTRB HIGH.

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READ TRANSFERS
• Two types:
1. with no wait states
2. With wait states
It is similar to write transfers but the difference is PWRITE signal is LOW.

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ERROR RESPONSE
• PSLVERR indicates error condition on an APB transfer. It is valid during last
cycle of APB transfer when PSEL,PENABLE AND PREADY all are HIGH.
• When PSEL,PENABLE AND PREADY are HIGH if error occurred PSLVERR
goes HIGH.
• When PSEL,PENABLE AND PREADY are low PSLVERR is low because no
data is transferred.

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Operating states

• IDLE: default state of APB

• SETUP :when transfer required ,PSELx is HIGH then
buses moves to Setup for one clock cycle and always
moves to ACCESS at next rising edge of the clock.
• ACCESS:PENABLE is asserted in ACCESS state.The
address,write,select, and write data signals must remain
stable during transition from the SETUP to ACCESS
state.
Exit from the ACCESS state is controlled by the
PREADY signal from slave:
1. PREADY=LOW then peripherals remains in access
state.
2.PREADY =HIGH ACCESS state is exited and bus
moves to IDLE state state if no more transfers are
required.if transfers are required bus moves to
SETUPstate.

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DRAWBACKS
• Multiple outstanding transactions are not handled well.

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 Internal Use Only

JTAG
INTRODUCTION
• JTAG abbreviated as JOINT TEST ACTION GROUP. It test the hardware
interconnects between multiple ICs.
• Here data’s are pipelined.

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BOUNDARY SCAN
• It provides ability to set and read the values on pins without physical access.
• Each IO pin on the device provided with a small logic between the internal logic
and the physical pin.
• All these logics are connected so they can shift datain one direction
• The values are can be read or writtern to test functionality

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Process of boundary scan

• All the signals between the device core logic

and pins are intercepted by serial scan path
known as Boundary Scan Register(BSR).
• BSR consist of boundary scan cells.
• Normal operation boundary scan cells are
invisible.
• In test mode the cells can be used to set or
read vale of the core logic.

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Interface signals
• JTAG interface are collectively known as TAP(Test Access Port).uses the below
signals o support operation of boundary scan.
• TCK(Test Clock)-synchronizes the internal state machine operations
• TMS(Test Mode Select)- this signal is sampled at the rising edge of clock to
determine next state.
• TDI(Test Data In)- represents data shifted into device and sampled at rising
edge of clock
• TDO(Test Data Out)- represents data shifted out of the device .
• TRST(Test Reset)- can reset the TAP controller’s state.

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REGISTERS
• There are two types of registers associated with boundary scan
• Instruction register-hold the current instruction.used by TAP controller to decide
what to do with signals that are received.it defines to which of the data registers
signals should be passed.
• Data registers- there are 3 registers Boundary Scan Register(BSR),BYPASS
Register and IDCODES Register.
BSR-testing data Register.used to move data to ad from IO pins of the
device.
BYPASS-this is single bit Register that pass information from TDI to TDO.
IDCODES-contains ID code and revision number of the device.This
information allows the device to link to its BSDL file(boundary scan description
language contains details of boundary scan configuration).
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Tap controller

• The TAP controller, a state machine whose

transitions are controlled by the TMS signal,
controls the behaviour of the JTAG system.
• All states have two exits ,transition are
controlled by TMS signal sampled on TCK.
• Two main paths are there which allow for
setting or retrieving information from
registers.

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• A transition between the states only occurs on the rising edge of the clock
• Data registers operates in states named“DR” and instruction register operates in
the states name “IR”
Operation :
Test logic reset:disabled in this controller for normal operation.

Run test idle: active only if certain instruction are present.For eg, if an instruction activates the self
test then the controller it is executed when the controller enters this state.The test logic is Idle
otherwise.

Select IR SCAN:controller state controls whether to enter or not to enter the instruction parth.else
controller return to Test logic reset state other wise.

Shift-Dr, Exit1-DR, Pause-DR, Exit2-DR and Update-DR:These controller states are similar to the
Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and Update-IR states in the Instruction path.

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• Capture-IR:in this controller state,the shift register bank in the instruction register parallel loads
a pattern of fixed values on the rising edge of TCK.last two bits always must be 01.
• Shift-IR: in this controller state,the instruction register gets connected betwwwe TDI and
TDOand captured pattern gets shifted on each rising edge of tck.
• Exit1-IR:This controller state controls whether to enter the Pause-IR state or Update-IR state.

• Pause-IR:This state allows the shifting of the instruction register to be temporarily halted.

• Exit2-DR:This controller state controls whether to enter either the Shift-IR state or Update-IR
state.
• Update-IR:In this controller state, the instruction in the instruction register is latched to the latch
bank of the Instruction Register on every falling edge of TCK. This instruction becomes the
current instruction once it is latched.
• Capture-DR:In this controller state, the data is parallel-loaded into the data registers selected by
the current instruction on the rising edge of TCK.
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THANK YOU

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