Computer Evolution

ENIAC - background
• Electronic Numerical Integrator And
Computer
• Eckert and Mauchly
• University of Pennsylvania
• Trajectory tables for weapons
• Started 1943
• Finished 1946
—Too late for war effort
• Used until 1955 for other purposes.
• Hence need for easy re-programmability.
ENIAC - details
• Decimal (not binary)
• 20 accumulators of 10 digits
• Programmed manually by switches
• 18,000 vacuum tubes
• 30 tons
• 15,000 square feet
• 140 kW power consumption
• 5,000 additions per second
Decimal digit implementation
• One decimal digit implemented with 10
vacuum tubes arranged in a circle. 20
such circles for 20 accumulators each.
0 1 0 1 0 1 0 1 0 1
9 9 9 9 9
2 2 8 2 8 2 8 2
8 8
3 3 7 3 7 3 7 3
7 7 6 5 4
6 5 4 6 5 4 6 5 4 6 5 4
0 1
9
8 2
… 7 3
6 5 4
Each tube is connected to adjacent tubes for
easy implementation of inc, dec, carry,
barrow etc operations.
Von Neumann / Alan Turing
• Stored Program concept
• Main memory storing programs and data
• ALU operating on binary data
• Control unit interpreting instructions from
memory and executing
• Input and output equipment operated by
control unit
• Princeton Institute for Advanced Studies-IAS
• Completed 1952
Structure of von Neumann machine
IAS - details
• 1000 x 40 bit words
—Binary number
—2 x 20 bit instructions
• Set of registers (storage in CPU)
—Memory Buffer Register MBR
—Memory Address Register MAR
—Instruction Register IR
—Instruction Buffer Register IBR
—Program Counter PC
—Accumulator A
—Multiplier Quotient MQ
The Von-Neumann Model of a Computer

Memory

MAR

MDR

Processing Unit Output

Control Unit
l em

IR IP
ent
as
Moore’s Law
• Increased density of components on chip
• Gordon Moore – co-founder of Intel
• Number of transistors on a chip will double every
year
• Since 1970’s development has slowed a little
— Number of transistors doubles every 18 months
• Cost of a chip has remained almost unchanged
• Higher packing density means shorter electrical
paths, giving higher performance
• Smaller size gives increased flexibility
• Reduced power and cooling requirements
• Fewer interconnections increases reliability
Growth in CPU Transistor Count
DEC PDP-8
• 1964
• First minicomputer (after miniskirt!)
• Did not need air conditioned room
• Small enough to sit on a lab bench
• $16,000
—$100k+ for IBM 360
• Embedded applications & OEM
—OEM (Original Equipment Manufacturer), the
reseller companies that purchase in bulk
• BUS STRUCTURE
DEC - PDP-8 Bus Structure
IP Sequence vs Dataflow Order
v <- a + b; a b

w <- b * 2;
+ *2
x <- v-w;
y <- v+w
- +
z <- x*y
*

Instructions are
Fetched and
Instruction fetched & executed in dataflow order.
executed
No IP. Each instruction specify which node should
sequentially as
receive the result. Each node fires output when
given by IP unless
explicit control inputs are ready. Pipeline U-architecture
flow instruction is
involved
Performance Balance of a Computer
• Processor speed increased
• Memory capacity increased
• Memory speed lags behind processor
speed
Logic and Memory Performance Gap
Improvements in Chip Organization and
Architecture
• Increase hardware speed of processor
—Fundamentally due to shrinking logic gate size
– More gates, packed more tightly, increasing clock
rate
– Propagation time for signals reduced
• Increase size and speed of caches
—Dedicating part of processor chip
– Cache access times drop significantly
• Change processor organization and
architecture
—Increase effective speed of execution
—Parallelism
Problems with Clock Speed and Logic
Density
• Power
— Power density increases with density of logic and clock
speed
— Dissipating heat
• RC delay
— Speed at which electrons flow limited by resistance and
capacitance of metal wires connecting them
— Delay increases as RC product increases
— Wire interconnects thinner, increasing resistance
— Wires closer together, increasing capacitance
• Memory latency
— Memory speeds lag processor speeds
• Solution:
— More emphasis on organizational and architectural
approaches
New Approach – Multiple Cores
• Multiple processors on single chip
— Large shared cache
• Within a processor, increase in performance
proportional to square root of increase in
complexity
• If software can use multiple processors, doubling
number of processors almost doubles
performance
• So, use two simpler processors on the chip rather
than one more complex processor
• With two processors, larger caches are justified
— Power consumption of memory logic less than
processing logic
Embedded Systems
ARM
• ARM evolved from RISC design
• Used mainly in embedded systems
—Used within product
—Not general purpose computer
—Dedicated function
—E.g. Anti-lock brakes in car
Possible Organization of an Embedded System

FPGA:
Field Prgrammable Gate Array

ASIC:
App Specific Integrated Circuit
Intel’s Pentium
• This is an example of CISC design.
Differences between some members of
the Pentium family:
Evolution of the PowerPC
• The 801 minicomputer project at IBM,
together with the Berkeley RISC I
processor, launched the RISC movement.
• IBM then developed a commercial RISC
workstation, the RT PC.
• IBM then produced a third system, which
built on the 801 and RT PC, called the IBM
RISC System/6000 and referred to as the
POWER architecture.
Evolution of the PowerPC
• IBM then entered into alliance with
Motorola and Apple, which
resulted in a series of machines that
implement the PowerPC architecture
(derived from the POWER architecture).
• The PowerPC architecture is a superscalar
RISC system, and one of the most
powerful and best-designed ones on the
market.