SYSTEM DESIGN
WITH FPGA
STATIC TIMING
ANALYSIS
GROUP 13
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What is Timing Analysis?
Timing analysis as a process that ensures the circuit
operates at the desired speed without any timing
violations.
Static Timing Analysis (STA):
Examining signal propagation at design level
Dynamic Timing Analysis (DTA):
Simulation-based, checking at runtime
SYNOPSIS
1.Overview of Timing
Analysis
2.What is Static Timing
Analysis?
3.Significance
4.Types of Timing Paths in
STA
5.STA Flow and Process in
FPGA
6.Tools, Advantages and
Challenges
7.Optimization Techniques
CRITICAL ROLE OF STA IN FPGA
Emphasize that STA helps in IMPORTANCE
achieving timing closure, which is
crucial as modern FPGA designs OF STA
operate at higher clock frequencies
and have complex, multi-level logic
ENSURING RELIABLE
PERFORMANCE
Discuss how STA ensures that all
data signals reach their
destination in time to meet the
clock cycle constraints.
EFFECT ON CLOCK SPEED AND
POWER
Explain how improper timing can
lead to high power consumption and
limited performance due to
Varshini K A S
unnecessary delays and race 21BEC175
conditions.
DEFINITION
STA is a method used to verify that a
design meets its timing
requirements without running test
vectors. It checks all possible paths
in the design for violations like setup
and hold time violations.
HOW STA WORKS?
STA works by calculating the signal
delays along each timing path in
the circuit and comparing them to
the required time (clock period)..
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STA Process Flow
Netlist Extraction: Extract the logical representation of the
circuit
Clock Tree Synthesis (CTS): Ensuring the clock signal reaches all parts
of the design efficiently.
Netlist Extraction: Extract the logical representation of the
circuit
Timing Calculation: Calculate the delay for each timing path in
the design
Report Generation: The final stage involves generating timing reports that
highlight setup/hold violations and critical paths.
Critical Path Identification: Define critical path as the longest delay path
in the design, and explain how meeting timing for this path ensures the
entire design meets timing requirements.Explain the significance of the
slack
TYPES OF TIMING
PATHS
SETUP AND CLOCK-TO- DATA-TO-CLOCK ASYNCHRONOU
HOLD TIMING OUTPUT PATH PATH S PATHS
PATHS
Tools Used For STA And its
•
Features
Tools like Xilinx Vivado and Intel Quartus Prime, which
provide in-built STA capabilities are used.
• Third-party tools (e.g., PrimeTime, TimeQuest, which are
sometimes used for more advanced STA.
• Clock Definition: Define the clock period, frequency, and
other clock characteristics.
• Path Analysis: Analyze timing paths to detect violations.
• Cross-Probing: In some tools, you can visualize timing
paths in both timing reports and layout views to pinpoint
optimization areas.
Optimization
Techniques
• Pipelining: Breaking a long combinational path
into smaller stages to meet timing.
• Retiming: Moving registers across logic to
balance the delay in paths.
• Clock Gating: Reducing unnecessary switching
activity to lower power consumption without
affecting timing.
• Logic Duplication: Duplicating logic to shorten
the longest path and thus improve timing
closure.
Advantages
1.Efficiency and Speed
2.Vectorless Analysis
3.Scalability for Large Designs
4.Early Detection of Timing Issues
5.Handles Multiple Corners and
Modes
6.Supports Complex Timing
Constraints
Challenges
1.No Consideration of Logical
Functionality
2.Inability to Handle Dynamic Effects
3.Clock Domain Crossing (CDC) Issues
4.Lack of Variability Modeling
5.Limited in Handling Complex Timing
Constraints
6.Sequential Elements and Latch-Based
Designs
Conclusi
Static Timing Analysis (STA)on
is crucial in ensuring that FPGA
designs meet timing constraints, guaranteeing reliable
performance. It helps detect timing violations early,
ensuring the circuit operates as intended under various
conditions.
FUTURE TRENDS
AI-Assisted Timing Optimization: Machine learning tools will
help automate timing constraint generation and improve timing
closure efficiency.
Advanced Multi-Clock Domain Handling: New methodologies
will improve the management of complex multi-clock domain
designs, reducing timing violations.
THARUNIKA M 21BEC167
THENDAARNIKA G 21BEC168
THANK S
USHA NANDHINI
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YOU G
VAISHNAVI J K
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VARSHINI K A S
VARSHINI M
