Lecture 6:

Functions of Combinational logic

A practical combinational circuit may be vary complex. Thus, most real
combinational logic design problems are too large and difficult.
How do we design such a complex logic circuit?
In the first place, the key is structured thinking. A complex circuit or
system should be divided into some smaller subsystems or modules.
And then, we can perform these subsystems or modules by using same
specific function modules.
In this lecture, we will take several specific function modules those are
used frequently.
Functions of Combinational logic
 Encoders
 Decoders
 Multiplexers (Data selectors)
 Demultiplexers
 Comparators
 Adders
Encoders

 Decimal-to-BCD encoder
 Priority encoder
 8-line-to-3-line priority encoder (74HC148)
Decimal-to-BCD encoder
 Encoder
It is the device that can perform the process of
converting from familiar symbols or numbers to a coded
format.
This process is called encoding.
 Group Select
Decimal-to-BCD encoder It indicates if the output
code is active.

VCC
Decimal-BCD encoder
1kΩ× 10
0

1 GS

3
A0
4
10 inputs
5
A1 BCD
6 output
7 A2

9 A3
 Decimal-to-BCD encoder
 Analyzing the function
When the key is depressed, VCC Decimal-BCD encoder
corresponding input line is LOW, 1kΩ× 10
0
Or else it is HIGH
 When the key 2 is depressed 1 GS 1
Output code: A3A2A1A0= 0010 2
0
GS = 1 3
A0
0
4

5
A1 1
6

7 A2 0
8

9 A3
0
 Decimal-to-BCD encoder
 Analyzing the function
When the key is depressed, VCC Decimal-BCD encoder
corresponding input line is LOW, 1kΩ× 10
0
Or else it is HIGH
 When the key 2 is depressed 1 GS 1
Output code: A3A2A1A0= 0010 2

GS = 1 3
 When the key 7 is depressed
A0
1
4
Output code: A3A2A1A0= 0111
5
GS = 1
A1 1
6

7
0 A2 1
8

9 A3
0
 Decimal-to-BCD encoder
 Analyzing the function
When the key is depressed, VCC Decimal-BCD encoder
corresponding input line is LOW, 1kΩ× 10
0
Or else it is HIGH
 When the key 2 is depressed 1 0 GS 1
Output code: A3A2A1A0= 0010 2

GS = 1 3
 When the key 7 is depressed
A0
0
4
Output code: A3A2A1A0= 0111
5
GS = 1
A1 0
6
 When the key 0 is depressed
7
Output code: A3A2A1A0= 0000 A2 0
GS = 1 8

9 A3
0
 Decimal-to-BCD encoder
 Analyzing the function
When the key is depressed, VCC Decimal-BCD encoder
corresponding input line is LOW, 1kΩ× 10
0
Or else it is HIGH
 When the key 2 is depressed 1 GS 0
Output code: A3A2A1A0= 0010 2

GS = 1 3
 When the key 7 is depressed
A0
0
4
Output code: A3A2A1A0= 0111
5
GS = 1
A1 0
6
 When the key 0 is depressed
7
Output code: A3A2A1A0= 0000 A2 0
GS = 1 8
 When none of keys is depressed 9 A3
0
Output code: A3A2A1A0= 0000
GS = 0
 Decimal-to-BCD encoder
VCC

 Analyzing the function

Decimal-BCD encoder
1kΩ× 10
0

1 GS

Function table 2

inputs outputs 3
A0

0 1 2 3 4 5 6 7 8 9 A3 A2 A1 A0 GS 4

1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 5
A1
6
1 1 1 1 1 1 1 1 1 0 1 0 0 1 1
7 A2
1 1 1 1 1 1 1 1 0 1 1 0 0 0 1
8
1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 A3
9
1 1 1 1 1 1 0 1 1 1 0 1 1 0 1
1 1 1 1 1 0 1 1 1 1 0 1 0 1 1
1 1 1 1 0 1 1 1 1 1 0 1 0 0 1 The active input level is LOW.
1 1 1 0 1 1 1 1 1 1 0 0 1 1 1
Why is the GS required ?
1 1 0 1 1 1 1 1 1 1 0 0 1 0 1
1 0 1 1 1 1 1 1 1 1 0 0 0 1 1 What is happen when more than one
0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 key are depressed ?
 Decimal-to-BCD encoder
What is happen when more then one keys are depressed ?
 When the keys 2 and 5 are depressed VCC Decimal-BCD encoder
1kΩ× 10
Output code: A3A2A1A0= 0111 0

GS = 1 1 GS 1
2
0
Wrong code 3
A0
1
4

5
0 A1 1
6

7 A2 1
8

9 A3
0
Next item we are going to discuss

 Decimal-to-BCD encoder
 Priority encoder
 8-line-to-3-line priority encoder (74HC148)
Priority encoder
 The priority encoder is such encoder which inputs
are assigned priority, so that when multiple inputs
are active, it will only produce the code for the
highest-order input and ignore any other lower-
order active inputs.
 Priority encoder
 Decimal-to-BDC priority encoder
The code 0101 indicates input 5 truth table for priority encoder
The code 1001 indicates input 9 inputs outputs
Which is the highest-priority input 0 1 2 3 4 5 6 7 8 9 A3 A2 A1 A0 GS
? can derive the output expressions
We
1 1 1 1 1 1 1 1 1 1 0 0 0 0 0
x x x x x 0x x x x 0 1 0 0 1 1
from this table and draw logic x x x x x x x x 0 1 1 0 0 0 1
diagram. x x x x x x x 0 1 1 0 1 1 1 1
A3  9  9 8
x x x x x x 0 1 1 1 0 1 1 0 1
A2 987  9876  98765  987654
x x 0x x x 0 1 1 1 1 0 1 0 1 1
... x x x x 0 1 1 1 1 1 0 1 0 0 1
x x x 0 1 1 1 1 1 1 0 0 1 1 1
Note:
x x 0 1 1 1 1 1 1 1 0 0 1 0 1
In the expressions, 9,8,7… only x 0 1 1 1 1 1 1 1 1 0 0 0 1 1
represent the input variables. 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1
Next item we are going to discuss

 Decimal-to-BCD encoder
 Priority encoder
 8-line-to-3-line priority encoder (74HC148)
 Note: Each of A2 , A1 , A0 , EI , EO and GS
8-line-to-3-line priority encoder (74HC148)
is regarded as a whole variable. These are
active-LOW.
 Its inputs and outputs are active-LOW (Code 000 is corresponding to input 7)
 The highest-priority input is 7
 Enable input EI is active-LOW ( If EI 0 , the encoder can be allowed to encode)
 Truth table for 8-line-to-3-line priority encoder
Enable output EO is active-LOW
inputs outputs
 EO can be connected to the EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO
EI 1 x x x x x x x x 1 1 1 1 1
of another encoder for 0 x x x x x x x 0 0 0 0 0 1
 Group select GS is active-LOW 0 x x x x x x 0 1 0 0 1 0 1
expending
0 x x x x x 0 1 1 0 1 0 0 1
0 GS
1 0 x x x x 0 1 1 1 0 1 1 0 1
2 EO
3 0 x x x 0 1 1 1 1 1 0 0 0 1
4 74HC148
5 A2 0 x x 0 1 1 1 1 1 1 0 1 0 1
6
7 A1 0 x 0 1 1 1 1 1 1 1 1 0 0 1
EI A0 0 0 1 1 1 1 1 1 1 1 1 1 0 1
Logic diagram 0 1 1 1 1 1 1 1 1 1 1 1 1 0
The next topic
 Encoders
 Decoders
 Multiplexers (Data selectors)
 Demultiplexers
 Comparators
 Adders
 Decoders
 A decoder is a combinational logic circuit that essentially
performs a “reverse” encoder function.
 It is a multiple-input, multiple-output logic circuit that
converts coded inputs into coded outputs.
 The input code generally has fewer bits than the output
code, and there is a one-to-one mapping from input code
words into output code words.
Decoders
 Binary decoder
A binary decoder is an n-to-2n decoder. Such a decoder has n
inputs and 2n outputs. It is also called 1-of-2n decoder because for
any given code on the inputs, one of the 2n outputs is activated.
 Basic decoding element
To detect the state when a binary 1001 occurs on the inputs
of a digital circuit.
Using AND gate,
the output is active-
HIGH
Decoders
 Basic decoding element
To detect a binary 0101 LSB
MSB

A0
MSB
A1
X  A3 A2 A1 A0
A2
A3

Using NAND gate, the output is active-LOW

A0
A1
X
A2
A3
Decoders
 2-to-4 decoder
 The output is active-HIGH

 Enable input is active-HIGH

Decoders
 4-to-16 decoder
 The output is active-LOW
Decoders
 3-to-8 MSI decoder
Decoders
 3-to-8 MSI decoder
Decoders
 Pulse Operation
E
A0
A1
A2
1 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
E Y0_L
Y1_L
A0 Y2_L
A1
Y3_L
A2
Y4_L
Y5_L
Y6_L
Y7_L
Decoders
 Using 3-to-8 MSI decoder to design boolean function
Decoders Low order

 The extension of the decoder +5V G1 Y0 0 1

1
G2A Y1 1
How to implement a 4-to-16 decoder G2B Y2 2 1
74HC138 Y3 3 1
with two 74HC138 decoders ? (1) Y4 4 1
A Y5 10
Expand by enable inputs B
5
1
Y6 6
When D=0, chip (1) is enabled C Y7 7 1

When D=1, chip (2) is enabled Y0 8 1

G1
Y1 9 1
For example G2A
Y2 10 1
G2B
When DCBA=0101, LSB 74HC138 Y3 11 1
(2) Y4 12 1
the output 5 is 0, 1 A A Y5 01
13
others are 1s. 0 B B Y6 14 1
1 C C Y7 1
When DCBA=1101, 10 D
15

the output 13 is 0,
others are 1s. MSB High
order
Decoders
 The BCD-to-7-segment decoder
The light-emitting diode ( LED )

anode cathode
 Decoders
 The BCD-to-7-segment decoder
The light-emitting diode ( LED ) anode cathode
 If the voltage level of anode is higher than cathode,
the diode turns on, there is current through it, and it emits light.
 If the voltage level of anode is lower than cathode,
the diode turns off, there is not current through it, and it is blanking.
Limiting current
resistor to prevent +5V +5V Control circuit +5V A
that LED is burned Z
B
out R R R C
R
A
B
C Z
 Decoders
 The BCD-to-7-segment decoder
The 7-segment display
(refer to 4-12 of +5V
Textbook)
R a
a b
a c
f g b b d
c e
d f
e c e g
f
d g R

Segment identification Common anode Common cathode

 Decoders
 The 7-segment display a
a b
c
a b c d e f g d
f g b
1 1 1 1 1 1 0 e
f
e c 0 1 1 0 0 0 0 g

1 1 0 1 1 0 1 R
d
Segment identification
 Common cathode
 Decoders
 The BCD-to-7-segment decoder

BCD/7-seg a BCD/7-seg a
a
b b
A0 c Output lines A0 c f g b
A1 connect to A1
DCB input d d
A2 7-segment A2
e e
A3
f
display A3
f
e c
g g
d
A BCD-to-7-segment decoder A BCD-to-7-segment decoder
with active-LOW outputs with active-HIGH outputs
Common cathode
 The BCD-to-7-segment decoder
 The truth table for the decoder with active-HIGH outputs
Inputs Outputs
BCD/7-seg a a Decimal
A3 A2 A1 A0 abcdefg digit
b
A0 c f g b 0 0 0 0 1111110
A1
d 0 0 0 1 0110000
A2
A3
e e c 0 0 1 0 1101101
f 0 0 1 1 1111001
EN d
g
0 1 0 0 0110011
0 1 0 1 1011011
0 1 1 0 1011111
Common cathode 0 1 1 1 1110000
1 0 0 0 1111111
According to this truth table, we can design 1 0 0 1 1111011
the logic circuit of BCD-to-7-segment decoder. Other states 0000000 Dead
MSI 74HC4511 is a BCD-to-7-segment decoder
The next topic

 Encoders
 Decoders
 Multiplexers (Data selectors)
 Demultiplexers
 Comparators
 Adders
Multiplexers (Data selectors)
 Multiplexers
A multiplexer (MUX) is a digital switch which connects data
from one of n sources to its output.
D0
D1
n-data
inputs Y
Data output
The data-select inputs
control which route is
m-select inputs
chosen.
Multiplexers (Data selectors)
 The simplest multiplexer (1-of-2 data selector )
Y  S 0 D0  S 0 D1
S0
If S0=0, D0 G1
G3 Y
then Y=D0 G2
D1

If S0=1,
then Y=D1

select input: S0
data input: D0 , D1
 Multiplexers (Data selectors)
 A 4-input multiplexer (1-of-4 data selector )
10 01 function table
EN

EN
0
0
0
0
0 x x
1 0

Y  D0 S1 S 0  D1 S1 S 0  D2 S1 S 0  D3 S1 S 0
Logic symbol
 Multiplexers (Data selectors)
 A 4-input multiplexer (1-of-4 data selector )
function table
Example : the data-input and data-select
waveforms are applied to multiplexer.
Determine the output in relation to the inputs.
D0
D1
D2
D3
S0 0 1 0 1 0 1 0 1
S1 0 0 1 1 0 0 1 1

D0 D1 D2 D3 D0 D1 D2 D3
Logic symbol
 Multiplexers (Data selectors)
 The 2-input, 4-bit multiplexer (MSI 74x157)

2 sources of data
4 bits wide for each
 Multiplexers
 Application example 01

Two BCD digits: A3 A2 A1 A0 , B3 B2 B1 B0 A0

B

A1
B
A square wave is applied to data-select line
A2
B
When data-select is LOW,
The output of MUX select the A bits A3
B

The BCD/7-seg decoder decodes data A

The output Y0 of 2-to-4 decoder is LOW
and enable A-digit display
When data-select is HIGH,
The output of MUX select input B
The BCD/7-seg decoder decodes data B 0
0
The output Y1 of 2-to-4 decoder is LOW
and enable B-digit display
 Multiplexers
 Application example
Two BCD digits: A3 A2 A1 A0 , B3 B2 B1 B0
A square wave is applied to data-select line

When the cycle repeats at frequency of

the data-select square wave,
each digit display alternates between
on and off in different interval.
If this frequency is high enough (about 30
Hz),
all digit displays look like always being
on and they are not visual flicker

How to extend it to display 4-digit ?

(This question is left for you)
The next topic

 Encoders
 Decoders
 Multiplexers (Data selectors)
 Demultiplexers
 Comparators
 Adders
Demultiplexers
 Demultiplexers
The function of a demultiplexer (DMUX) is just the inverse of a
multiplexer’s. It takes data from one line and distributes them to a
given number of output lines. It is also known as a data distributor.
D0
D1
Data input

Decoders can be used

as demultiplexers
m-select inputs
 Note: in this case, the decoder
Demultiplexers must has the enable input
 A 2-to-4 decoder is used as a 1-to-4 demultiplexer
Enable input in Given different state of select
decoder lines, the input data will be
D distributed to corresponding
output.

Code inputs in decoder D0  DS1 S 0 D2  DS1 S 0

D1  DS1 S 0 D3  DS1 S 0
 Multiplexers, Demultiplexers and Buses

A selected one of multiple

data sources gets directed onto
a bus and routed to a selected
one of multiple destinations.

Block diagram
The next topic

 Encoders
 Decoders
 Multiplexers (Data selectors)
 Demultiplexers
 Comparators
 Adders
 Comparators
 Comparators
The basic function of a comparator is to compare the magnitudes
of two binary quantities to determine the relationship of those
quantities.
For simplest case, only indicating whether two numbers are equal.
We can use a XOR gate to implement 1-bit equality comparator.

A If A=B, then Z=0 A

Z Z The output is
B If AB, then Z=1 B
active-HIGH
XNOR gate
XOR gate The output is active-LOW
Comparators
 The magnitude comparator
Inputs Outputs
For 1-bit case
A B AEQB AGTB ALTB
AGTB  AB 0 0 1 0 0
0 1 0 0 1
ALTB  A B 1 0 0 1 0
AEQB  AB  A B  AB  A B 1 1 1 0 0

B
AGTB
AEQB

A ALTB
Comparators
 The magnitude comparator
For the more then one bit case
First examine the highest-order bit in each number, when they
are equal, then examine the next lower-order bit, or else ignore
other lower-order bits.
A 2-bit comparator as example
Compare A1A0 and B1B0
If A1>B1, the result is that number A is greater than number B
If A1<B1, the result is that number A is less than number B
If A1=B1, then examine the next lower-order bit position, A0 and B0
Comparators
 A 2-bit magnitude comparator
Compare A1A0 and B1B0
If A1>B1, the result is that number A is greater then number B
If A1<B1, the result is that number A is less then number B
If A1=B1, then examine the next lower-order bit position, A0 and B0
thus, If A0=B0, the result is that number A is equal to number B
If A0>B0, the result is that number A is greater then number B
If A0<B0, the result is that number A is less then number B
Comparators
 A 2-bit magnitude comparator
Implement a 2-bit magnitude comparator by using two 1-bit
comparators and an additive logic circuit

Here B0 AGTB0
AEQB0 AGTBO
AEQB1 : A1=B1
ALTB0 Additive
AGTB1 : A1>B1 A0 AEQBO
logic
ALTB1 : A1<B1 B1 AGTB1 circuit ALTBO
AEQB1
AEQB0 : A0=B0
ALTB1
AGTB0 : A1

A0>B0 ALTB0
: A0<B0
Comparators
 A 2-bit magnitude comparator
If A1>B1, the result is that number A is greater then number B
If A1<B1, the result is that number A is less then number B
When A1=B1, examine the next lower-order bit position, A0 and B0
thus, If A0=B0, the result is that number A is equal to number B
If A0>B0, the result is that number A is greater then number B
If A0<B0, the result is that number A is less then number B
For additive logic circuit
If AEQB1 and AEQB0 are true, AEQBO is true
If AGTB1 is true or AEQB1 and AGTB0 are true, AGTBO is true
If ALTB1 is true or AEQB1 and ALTB0 are true, ALTBO is true
Comparators
 A 2-bit magnitude comparator
Design additive logic circuit
If AEQB1 and AEQB0 are true, AEQBO is true
If AGTB1 is true or AEQB1 and AGTB0 are true, AGTBO is true
If ALTB1 is true or AEQB1 and ALTB0 are true, ALTBO is true

The expressions
AEQBO = AEQB1·AEQB0
AGTBO = AGTB1 + AEQB1·AGTB0
ALTBO = ALTB1 + AEQB1·ALTB0
 Comparators
 A 2-bit magnitude comparator
AGTB0 AGTBO
The expressions of additive logic circuit
AEQB0
AEQBO = AEQB1·AEQB0 ALTB0 AEQBO
AGTBO = AGTB1 + AEQB1·AGTB0 AGTB1
ALTBO
ALTBO = ALTB1 + AEQB1·ALTB0 AEQB1
ALTB1
Three AND gates and two OR gates are required.
B0 AGTB0
AEQB0 AGTBO
ALTB0 Additive
A0 AEQBO
logic
B1 AGTB1 circuit ALTBO
AEQB1
ALTB1
A1
 Comparators
 A 4-bit magnitude
comparator

3 2 1 0 3 2 1 0
A B
COMP
A>B A=B A<B
 Comparators
 An MSI 4-bit magnitude comparator
(74HC85) Inputs Outputs
3 A3 B3 A 2 B2
A 1 B1 A 0 B0 IA>B IA=B IA<B OA>B OA=B OA<B
COMP
2 1 0 x x x x x x x x x 1 0 0
A 0 1 x x x x x x x x x 0 0 1
13 A3=B3 1 0 x x x x x x x 1 0 0
OA>B
0 A3=B3 0 1 x x x x x x x 0 0 1
2
B
OA=B A3=B3 A2=B2 1 0 x x x x x 1 0 0
. .
1
OA<B . .
I0A>B .
A3=B3 A2=B2 A1=B1 A 0=B0 1 0 0 1 .
0 0
Cascading
IA=B A3=B3 A2=B2 A1=B1 A0=B0 0 0 1 0 0 1
inputs
IA<B
A3=B3 A2=B2 A1=B1 A0=B0 x 1 x 0 1 0
A3=B3 A2=B2 A1=B1 A0=B0 1 0 1 0 0 0
A3=B3 A2=B2 A1=B1 A0=B0 0 0 0 1 0 1
Comparators
 A MSI 4-bit magnitude comparator (74HC85)
Use 74HC85 comparators to compare two 8-bit numbers
A7 3
MSB COMP
A6 2
A3 3 A
COMP A5
A2 2 A4 31
A OA>B
A1 0
MSB B7
LSB A0 13 2 Compare
OA>B B6 OA=B
0 B result
B3 B5
2 1
B2 OA=B B4 OA<B
B
B1
B0 1 0IA>B
LSB OA<B IA=B
0 I0A>B IA<B
1 IA=B Cascading
0 IA<B
The next topic

 Encoders
 Decoders
 Multiplexers (Data selectors)
 Demultiplexers
 Comparators
 Adders
Adders
 The half-adder
A combinational circuit that performs the addition of two
bits is called a half adder.
Truth table for half adder
The basic rules for binary addition
0+0= 0 Inputs Outputs
0+1= 1 A B Cout 
1+0= 1 0 0 0 0
0 1 0 1
1 + 1 =10
1 0 0 1
Carry bit Sum bit 1 1 1 0
(arithmetic operation) Carry bit Sum bit
 Outputs
Adders Inputs
A B Cout 
0 0 0 0
 The half-adder 0 1 0 1
1 0 0 1
1 1 1 0
The expression
C out  AB
Σ  AB  A B  A  B

Logic diagram
Logic symbol
Here, we use logic circuit to
perform arithmetic operation.
 Adders
 The full-adder Logic symbol

The basic difference between a full-adder and a half-adder is that

the full-adder accept an input carry coming from lower-order bit.
The expression (using K-Map to simplify)
Σ ( A  B )  C in C out  AB  ( A  B )C in A B Cin Cout 
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
Logic diagram 0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
 Adders
 Parallel binary adders
Use four full-adders to implement a 4-bit
parallel binary adder
The carry output of each adder is
connected to the carry input of the next (MSI 74x283)
higher-order adder.

To the LSB position

there is no carry input,
so C0 should be
connected to ground
Adders
 Adder expansion
Adders
 Adder expansion
Adders
 Application example BCD Excess-3
Dec
A3 A2 A1 A0 Y3 Y2 Y1 Y0
Use a 4-bit parallel adder to implement 0 0000 0011
1 0001 0100
BCD-to-Excess-3 conversion. 2 0010 0101
3 0011 0110
BCD + 0011 = Excess-3 4 0100 0111
BCD 5 0101 1000
0 0 1 1 6 0110 1001
7 0111 1010
8 1000 1011
4 3 2 1 4 3 2 1 Cin 9 1001 1100
A B 10 1010 xxxx

11 1011 xxxx
12 1100 xxxx
Cout 4 3 2 1 13 1101 xxxx
14 1110 xxxx
15 1111 xxxx
Excess-3 code
Adders
 Application example
A B
A 4-bit magnitude subtraction 1
logic circuit
A and B are 4-bit magnitude numbers 4 3 2 1 4 3 2 1 Cin
S = A - B = A + (–B) = A + (B)2’com A B

= A + (B)1’com + 1 
Cout 4 3 2 1
if Indicated sign bit = 1,
difference S is positive number in true Indicated
if Indicated sign bit = 0, sign bit S
difference S is negative number in 2’
complement
How to perform that the difference is always in true ?
 A B
Adders 1

 Application example 4 3 2 1 4 3 2 1 Cin

A 4-bit magnitude subtraction A B


logic circuit
Cout 4 3 2 1
if Indicated sign bit = 1, Indicated sign bit
difference S is positive number
0 0 0 0
in true
if Indicated sign bit = 0, 4 3 2 1 4 3 2 1 Cin
A B
difference S is negative number in 2’

complement
Cout 4 3 2 1
How to perform that the difference is
always in true ? Controllable taking S
2’ complement Original Number
 A B
Adders 0 1 0 1 0 0 0 1
1

1 1 1 0
 Application example 4 3 2 1 4 3 2 1 Cin

A 4-bit magnitude subtraction A B


logic circuit
Cout 4 3 2 1
A=0101 ， B=0001 Indicated sign bit 0 1 0 0 0
1
0101
0 0 0 0
1110 0 1 0 0
+ 1 4 3 2 1 4 3 2 1 Cin
10100 A B

0100 Cout 4 3 2 1
0000 0 0 1 0 0
+ 0 sign bit S
0100 Original Number
 A B
Adders 0 0 0 1 0 1 0 1
1

1 0 1 0
 Application example 4 3 2 1 4 3 2 1 Cin

A 4-bit magnitude subtraction A B


logic circuit
Cout 4 3 2 1
A=0001 ， B=0101 Indicated sign bit 1 1 0 0 1
0
0001
0 0 0 0
1010 0 0 1 1
+ 1 4 3 2 1 4 3 2 1 Cin
01100 A B

0011 Cout 4 3 2 1
0000 1 0 1 0 0
+ 1 sign bit S
0100 Original Number
Adders
 Application example
A 5-bit signed binary numbers addition/subtraction circuit. Here all
numbers are in 2’ complement. A4 B 4 A3 A 2 A 1 A 0 B 3 B2 B1 B 0
Input numbers: add / sub
A 4 A 3 A 2 A1 A0
B 4 B 3 B 2 B1 B0
Output number: 4 3 2 1 4 3 2 1 Cin
S4 S3 S2 S1 S0 A B Cin A B

Hereinto: Cout  
A4 , B4 and S4 are sign bits Cout 4 3 2 1

The add / sub is control input

S4 S3 S2 S1 S0
 Adders
 Application example
A 5-bit signed numbers addition/subtraction circuit. Here all numbers
are in 2’ complement. A4 B 4 A3 A 2 A 1 A 0 B 3 B2 B1 B 0

When add / sub 0 add / sub

The circuit performs addition operation
S4S3S2S1S0 = A4A3A2A1A0 + B4B3B2B1B0
4 3 2 1 4 3 2 1 Cin
A4 A3 A2 A1 A0 A B Cin A B
B4 B3 B2 B1 B0 
Cout 
+ 0 Cout 4 3 2 1
S4 S3 S2 S1 S0
S4 S3 S2 S1 S0
(A4 , B4 and S4 are sign bits)
 Adders
 Application example
A 5-bit signed numbers addition/subtraction circuit. Here all numbers
are in 2’ complement. A4 B 4 A3 A 2 A 1 A 0 B 3 B2 B1 B 0

When add / sub 1 add / sub

The circuit performs subtraction operation
S4S3S2S1S0 = A4A3A2A1A0 - B4B3B2B1B0 4 3 2 1 4 3 2 1 Cin
= A4A3A2A1A0 + (B4B3B2B1B0)2’com A B Cin A B
A4 A3 A2 A1 A0 Cout  
B4 B3 B2 B1 B0 Cout 4 3 2 1
+ 1
S4 S3 S2 S1 S0 S4 S3 S2 S1 S0
This circuit is maybe a danger of overflow (A4 , B4 and S4 are sign bits)
Adders
 Application example
A 5-bit signed numbers addition/subtraction circuit. Here all numbers
are in 2’ complement. A4 B 4 A3 A 2 A 1 A 0 B 3 B2 B1 B 0
The circuit is maybe a
add / sub
danger of overflow
How to design a logic circuit to AS BS
indicate whether the overflow 4 3 2 1 4 3 2 1 Cin
A B Cin
occurs? A B
The condition of overflow : Cout  
Cout
Both input numbers of the adder 4 3 2 1
are positive or both are negative
but the result is opposite. ? S4 S3 S2 S1 S0
OF  AS BS S 4  AS BS S 4 (A4 , B4 and S4 are sign bits)
OF
 Adders
 Application example
A 5-bit signed numbers addition/subtraction circuit. Here all numbers
are in 2’ complement. A4 B 4 A 3 A 2 A1 A0 B3 B 2 B 1 B 0

add / sub
How to solve overflow?
by extending magnitude bits
4 3 2 1 4 3 2 1 Cin
If the number is positive, A B Cin A B Cin A B
the extending bits need be
Cout  
supplied with 0s Cout 
Cout 4 3 2 1
If the number is negative, the
extending bits need be
supplied with 1s S5 S4 S3 S2 S1 S0
The output has been expanded to 6-bit (A4 , B4 and S5 are sign bits)
 Adders 1
0
1
1
Application 0
0
example 1
1
0
6-input voting
system 1
1
4
Display the
number of “yes”
votes and the
number of “no” 1
votes 0
1 0
1
0
Each resistor connects
to a full-adder input
1

10k12
1
0
2
 Adders 1
1
1
1
1
Application 0
1
example 1
1
1

6
6-input voting 1
1
system 1

Display the
number of “yes”
votes and the
number of “no” 0
votes 0
0
0
0
Each resistor connects
to a full-adder input
0

10k12
0
0
 The brief statement for this lecture content
 A practical combinational circuit may have dozens of inputs and
outputs and could require hundreds, thousands, even millions of
terms to describe as a sum of products, and billions and billions
of rows to describe in a truth table. Thus, most real combinational
logic design problems are too large to solve by "brute-force"
application of theoretical techniques.
 How could any human being conceive of such a complex logic
circuit in the first place? The key is structured thinking. A complex
circuit or system is conceived as a collection of smaller
subsystems, each of which has a much simpler description.
 The brief statement for this lecture content
 In combinational logic design, there are several straightforward
structures-encoders, decoders, multiplexers, comparators, adders
and the like-that turn up quite regularly as building blocks in larger
systems.
 As we have seen these structures, that are regarded as building
blocks usually, have their specific functions and simpler
description.
 The brief statement for this lecture content
 Although the applications of MSI are declining since PLD and
FPGA are used more and more, the standard MSI functions like
encoders, decoders, multiplexers …, are widely used in PLD,
FPGA and ASIC as building blocks (or “standard cells” or
“macros”).
 We should more pay attention to the functions of these building
blocks and make light of them as MSI.