Chapter 4 : INTERCONNECT
PARASITICS
o RLC for Interconnect
o WireLoad Models
o Representation of Extracted parasitics
o Representing Coupling Capacitances
o Hierarchical Methodology
o Reducing Parasitics for Critical Nets
RLC for Interconnect
• The interconnect resistance comes from the interconnect traces in various metal
layers and vias in the design implementation.
• Thus, the interconnect resistance can be considered as resistance between the
output pin of a cell and the input pins of the fanout cells
• Below image shows example nets traversing various metal layers and vias
• The interconnect capacitance contribution is also from the metal
traces and is comprised of grounded capacitance as well as
capacitance between neighboring signal routes.
• The inductance arises due to current loops.
• Typically the effect of inductance can be ignored within the chip and is
only considered for package and board level analysis. In chip level
designs, the current loops are narrow
• T-Model :
• PI Model :
WIRELOAD MODELS
(WLM)
• Wireload models can be used to estimate capacitance, resistance
and the area overhead due to interconnect.
• The wireload model is used to estimate the length of a net based
upon the number of its fanouts.
• The average wire length within a block correlates well with the size
of the block.
• For different areas (chip or block size), different wireload models
would typically be used in determining the parasitics.
wire_load (“wlm_conservative”) {
resistance : 5.0; #per unit length of the interconnect
capacitance : 1.1;
area : 0.05;
slope : 0.5; #used for data points that are not specified
fanout_length (1, 2.6);
fanout_length (2, 2.9);
fanout_length (3, 3.2);
fanout_length (4, 3.6);
fanout_length (5, 4.1);
• The wireload model illustrates how the length of the wire can
be described as a function of fanout.
Length = 4.1 + (8 - 5) * 0.5 = 5.6 units
Capacitance = Length * cap_coeff(1.1) = 6.16 units
Resistance = Length * res_coeff(5.0) = 28.0 units
Area overhead due to interconnect = Length * area_coeff(0.05)
= 0.28 area units
• The units for the length,
capacitance, resistance and
area are as specified in the library.
INTERCONNECT TREES
• Once the resistance and capacitance estimates, say
Rwire and Cwire, of the pre-layout interconnect are
determined.
• For pre-layout estimation, the interconnect RC tree
can be represented using one of the following three
different representations
• Best-case tree: Balanced tree: Worst-case tree:
SPECIFYING WIRELOAD MODELS
• A wireload model is specified using the following command:
set_wire_load_model “wlm_cons” -library “lib_stdcell”
# Says to use the wireload model wlm_cons present in the
# cell library lib_stdcell.
• Wireload Modes
i. top ii. enclosed iii. Segmented
set_wire_load_mode enclosed
• A default wireload model may optionally be specified in the cell library as: default_wire_load : "wlm_light";
• A wireload selection group, which selects a wireload model based upon area, is defined in a cell library. Here is one such
example:
wire_load_selection (WireAreaSelGrp){
wire_load_from_area(0, 50000, "wlm_light");
wire_load_from_area(50000, 100000, "wlm_cons");
wire_load_from_area(100000, 200000, "wlm_typ");
wire_load_from_area(200000, 500000, "wlm_aggr");
}
• top wireload mode,
all nets within the hierarchy
inherit the wireload model
of the top-level.
• enclosed wireload mode,
the wireload model of the
block that fully encompasses
the net is used for the entire
net.
• segmented wireload mode,
each segment of the net gets
its wireload model from the
block that encompasses the
net segment.
Representation of Extracted
Parasitics
• Parasitics extracted from a layout can be described in three formats:
• i. Detailed Standard Parasitic Format (DSPF)
• ii. Reduced Standard Parasitic Format (RSPF)
• iii. Standard Parasitic Extraction Format (SPEF)
Detailed standard parasitic
format
• In the DSPF representation, the detailed parasitics are represented in
SPICE1 format.
• DSPF with SPICE1 format captures a wide array of information,
including exact resistances, capacitances, inductances, and their
spatial relationships within the layout.
• The advantage of this format is that the DSPF file can be used as an
input to a SPICE simulator itself
• However, the drawback is that the DSPF syntax is too detailed and
verbose with the result that the total file size for a typical block is very
large.
Reduced standard parasitic
format
• RSPF reduces detailed parasitic data, such as resistances and
capacitances, into a compact format.
• It typically includes components like voltage sources and controlled
current sources to approximate the behavior of interconnects and
devices
• This files are also spice format
• drawback of the RSPF representation since the focus of the parasitic
extraction pro cess is normally on the extraction accuracy and not on
the reduction to a compact format like RSPF.
Standard parasitic exchange
format
• The SPEF is a compact format which allows the representation of the
detailed parasitics
• SPEF allows the description of parasitic information of a design (R, L
and C) in an ASCII exchange format. A user can read and check values
in a SPEF file, though the user would never create this file manually.
• Parasitics can be represented at many different levels. SPEF supports
the distributed net model, the reduced net model and the lumped
capacitance model
• SPEF supports the specifica tion of best-case, typical, and worst-case
values
• The main advantage of the SPEF file
• By providing a name map consisting of a map of net names and
instance names to indices, the SPEF file size is made effectively
smaller, and more importantly, all long names appear in only one
place
Representing Coupling Capacitance
• The representation of coupling capacitances in DSPF is as an add-on to the original DSPF
standard and is thus not unique. In DSPF the coupling capacitances are replicated between
both sets of coupled nets. Some tools which out put DSPF resolved this discrepancy by
including half of the coupling capacitance in both of the coupled nets.
• The RSPF is a reduced representation and thus not amenable to representing coupling
capacitances.
• The SPEF standard handles the coupling capacitances in a uniform and unambiguous manner
and is thus the extraction format of choice when cross talk timing is of interest. Further, the
SPEF is a compact representation in terms of file size and is used for representing parasitics
with and without coupling.
Hierarchical Methodology
• The large and complex designs generally require hierarchical methodology during
the physical design process for the parasitic extraction and timing verification.
• In the case of the hierarchical flow, where the top level layout is complete,
wireload model based parasitic estimates can be used for the lower level blocks
along with the layout extracted parasitics for the top level.
Block Replication in Layout: If a design block is replicated multiple times in layout,
the parasitic extraction for one instantiation can be utilized for all instantiations.
This requires that the layout of the block be identical in all respects for various
instantiations of the block.
Reducing parasitics for critical
nets
• Reducing interconnect resistance: The interconnect resistance is
reduced by maintaining low slew values. This can be achieve by two
ways.
• wide traces
• Routing in upper metals
• Increasing wire spacing
• Parasitics for corelated nets
