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VLSI Unit-5

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Sariki Santosh
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141 views

VLSI Unit-5

Uploaded by

Sariki Santosh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Topics:

• VLSI design flow


• MOS layers
• Stick diagrams
• Design Rules and Layout
• 2 um CMOS design rules for wires
• Contacts and Transistors
• Layout diagrams for NMOS and
• CMOS inverters and gates, Scaling of MOS
circuits
VLSI Design Flow:
Layer Types:

• p-substrate
• n-well
• n+
• p+
• Gate oxide (thin oxide)
• Gate (polycilicon)
• Field Oxide – Insulated glass – Provide
electrical isolation
Stick Diagrams
• VLSI design aims to translate circuit concepts onto
silicon.
• Stick diagrams are a means of capturing topography
and layer information using simple diagrams.
• Stick diagrams convey layer information through
colour codes (or monochrome encoding).
• Acts as an interface between symbolic circuit and
the actual layout.
• Does show all components/vias.
• It shows relative placement of components.
• Goes one step closer to the layout
• Helps plan the layout and routing
Stick Diagrams
• Does not show
– Exact placement of components
– Transistor sizes
– Wire lengths, wire widths, tub boundaries.
– Any other low level details such as
parasitics.
Stick Diagrams – Some rules
• Rule 1
• When two or more ‘sticks’ of the same type cross or
touch each other that represents electrical contact.

• Rule 2.
• When two or more ‘sticks’ of different type cross or
touch each other there is no electrical contact. (If
electrical contact is needed we have to show the
connection explicitly).
• Rule 3.
• When a poly crosses diffusion it represents a
transistor.

Note: If a contact is shown then it is not a transistor.


• Rule 4.
• In CMOS a demarcation line is drawn to avoid
touching of p-diff with n-diff. All pMOS must lie on
one side of the line and all nMOS will have to be on
the other side.
NMOS INVERTER:
NMOS EX-OR
NMOS EX-NOR
PMOS-INVERTER
PMOS NAND
PMOS-NOR
Stick design for CMOS
Inverter:
Stick Diagram for BiCMOS Inverter:
Design Rules:
• Allow translation of circuits (usually in stick diagram or symbolic form)

into actual geometry in silicon


• Interface between circuit designer and fabrication engineer
• Compromise
– Circuit designer wants tighter, smaller layouts or improved
performance.
– Process engineer wants design rules that result in a controllable,
reproducible process.
• Lambda based design rules – work of Mead and Conway – used
widely.
Lambda Based Design Rules:
• Design rules based on single parameter, λ .
• Simple for the designer ,Widely accepted rule.
• Provide feature size independent way of setting out mask.
• If design rules are obeyed, masks will produce working
circuits .
• Minimum feature size is defined as “2 λ”.
• All paths in all layers will be mentioned in “λ” units.
• Used to preserve topological features on a chip
• Prevents shorting, opens, contacts from slipping out of area
to be contacted
Design rules for the diffusion layers and metal layers
Design rules for transistors
Contact Cuts:
⮚When making contacts between polysilicon and diffusion in nMOS circuits it should
be recognized that there are three possible approaches--poly. to metal then metal to
diff., or a buried contact poly. to diff., or a butting contact (poly. to diff. using metal).
▪ The buried contact is the most widely used, giving economy in space and a reliable
contact.
▪ Butting contacts were widely used at one time but have been mostly superseded by

buried contacts and have been included here and in the figures for the sake of
completeness.
▪ When deposition of the metal layer takes place the metal is deposited through the
contact cut areas onto the underlying area so that contact is made between the
layers.
▪ When connecting diffusion to polysilicon using the butting contact approach (see
Figure), the process is rather more complex.
▪ In effect, a 2A. x 2A. contact cut is made down to each of the layers to be joined. The
layers are butted together in such a way that these two contact cuts become
contiguous.
▪ Since the polysilicon and diffusion outlines overlap and thin oxide under polysilicon
acts as a mask in the diffusion process, the polysilicon and diffusion layers are also
butted together. The contact between the two butting layers is then made by a metal
Contacts (NMOS & CMOS)
CMOS INVERTER LAYOUT:
CMOS - INVERTER
Scaling of MOS Circuits
Microelectronic technology may be characterized in terms of several
indicators, or figures of merit. Commonly, the following are used:
• Minimum feature size
• Number of gates on one chip
• Power dissipation
• Maximum operational · frequency
• Die size
• Production cost.

Many of these figures of merit can be improved by shrinking the


dimensions of transistors, interconnections and the separation between
features, and by adjusting the doping levels and supply voltages.

Accordingly, over the past decade, much effort has been directed
toward the upgrading of process technology and the resultant scaling
down of devices and feature size.
SCALING MODELS AND SCALING FACTORS:
The most commonly used models are the constant electric field scaling model and the
constant voltage scaling model. They both present a simplified view, taking only first
degree effects into consideration, but are easily understood. Recently, a combined
voltage and dimension scaling model has been presented.

The below Figure, which indicates the device dimensions and substrate doping level
which are associated with the scaling of a transistor.
Summary of Scaling Effects:

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