Digital Circuits-Course Details

Programme: UG Programme in E&TC A.Y. 2021-22

Class: S.E (E&TC)
Engineering Sem. I
Course Code: 204182 (Theory)
Corresponding Lab Course Code : 204186 Lab Course Name: Digital Circuits Lab

Teaching Scheme Examination Scheme

Theory Practical Tutorial Theory Lab
Term
(hrs/week) (hrs/week) (hrs/week) Insem Endsem Sessional Practical Oral
Work

3 hrs 2 hrs ---- 30 70 --- --- 50 --

 UNIT V

State Machines

Dr.R.K.Navandar
Unit V : State Machines (07 Hrs)

Course Contents

 Basic design steps- State diagram, State table, State reduction, State
assignment

 Mealy and Moore machines representation , Implementation, finite state

machine implementation, Sequence detector.

 Introduction to Algorithmic state machines- construction of ASM chart and

realization for sequential circuits .
Here is a sequential circuit
with two JK flip-flops. There
is one input, X, and one
output, Z.
The values of the flip-flops
(Q1Q0) form the state, or the
memory, of the circuit.
The flip-flop outputs also go
back into the primitive gates
on the left. This fits the
general sequential circuit X Z
diagram at the bottom. Inputs Combinationa Outputs
l
circuit
Q0
Memory Q1
◦ State tables show the inputs, outputs, and flip-flop state changes
for sequential circuits.
◦ State diagrams are an alternative but equivalent way of showing
the same information.

Inputs Combinational Outputs

circuit

Memory
 State table and diagram
We can also represent the state table graphically with a state diagram.
A diagram corresponding to our example state table is shown below.

input output
Present State I nputs Next State Outputs
Q1 Q0 X Q1 Q0 Z 0/0 1/0
0 0 0 0 0 0
0 0 1 0 1 0 1/0
0 1 0 1 0 0
00 01
0 1 1 0 1 0
1/1
1 0 0 1 1 0 0/0 1/0 0/0
1 0 1 0 1 0
1 1 0 0 0 0 0/0
1 1 1 0 1 1 11 10

state
Mealy Machine
Moore Machine
Two Approaches

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10
State transition diagram

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Sequence recognizers (Mealy Machine)
A sequence recognizer is a special kind of sequential circuit that looks for a special bit pattern in
some input.
The recognizer circuit has only one input, X.
◦ One bit of input is supplied on every clock cycle. For example, it would take 20 cycles to scan a
20-bit input.
◦ This is an easy way to permit arbitrarily long input sequences.
There is one output, Z, which is 1 when the desired pattern is found.
Our example will detect the bit pattern “1001”:
Inputs: 1 1 1 0 0 1 1
0 1 0 0 1 0 0 1
1 0 …
Outputs: 0 0 0 0 0 1 0
0 0 0 0 1 0 0 1
0 0 …

Here, one input and one output bit appear every clock cycle.
This requires a sequential circuit because the circuit has to “remember” the inputs from previous
clock cycles, in order to determine whether or not a match was found.

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Sequential circuit design procedure
Step 1:
Make a state table based on the problem statement. The table should show the present
states, inputs, next states and outputs. (It may be easier to find a state diagram first, and then convert
that to a table.)
Step 2:
Assign binary codes to the states in the state table, if you haven’t already. If you have n
states, your binary codes will have at least
log2 n digits, and your circuit will have at least log2 n flip-flops.
Step 3:
For each flip-flop and each row of your state table, find the flip-flop input values that are
needed to generate the next state from the present state. You can use flip-flop excitation tables here.
Step 4:
Find simplified equations for the flip-flop inputs and the outputs.
Step 5:
Build the circuit!

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A basic state diagram
What state do we need for the sequence recognizer?
◦ We have to “remember” inputs from previous clock cycles.
◦ For example, if the previous three inputs were 100 and the current input is 1, then
the output should be 1.
◦ In general, we will have to remember occurrences of parts of the desired pattern—in
this case, 1, 10, and 100.
We’ll start with a basic state diagram:

1/0 0/0 0/0

A B C D

State Meaning
A None of the desired pattern (1001) has been input yet
B We’ve already seen the fi rst bit (1) of the desired pattern
C We’ve already seen the fi rst two bits (10) of the desired pattern
D We’ve already seen the fi rst three bits (100) of the desired pattern

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Overlapping occurrences of the pattern
What happens if we’re in state D (the last three inputs were 100), and the current input is 1?
◦ The output should be a 1, because we’ve found the desired pattern.
◦ But this last 1 could also be the start of another occurrence of the pattern! For example, 1001001
contains two occurrences of 1001.
◦ To detect overlapping occurrences of the pattern, the next state should be B.

1/0 0/0 0/0

A B C D
1/1
Pr esent S t at e I nput s N ext S t at e Out put s
Q1 Q0 X Q1 Q0 Z
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 0 1 0
1 1 0 0 0 0
1 1 1 0 1 1

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Filling in the other arrows
Remember that we need two outgoing arrows for each node, to account for the
possibilities of X=0 and X=1.
The remaining arrows we need are shown in blue. They also allow for the correct detection
of overlapping occurrences of 1001.

0/0
1/0
1/0 0/0 0/0
A B C D
1/0
0/0 1/1

State Meaning
A None of the desired pattern (1001) has been input yet
B We’ve already seen the fi rst bit (1) of the desired pattern
C We’ve already seen the fi rst two bits (10) of the desired pattern
D We’ve already seen the fi rst three bits (100) of the desired pattern

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Step 1: Making a state table
The first thing you have to figure out is precisely how the use of state will help you solve the given problem.
◦ Make a state table based on the problem statement. The table should show the present states, inputs, next states
and outputs.
◦ Sometimes it is easier to first find a state diagram and then convert that to a table.
This is usually the most difficult step. Once you have the state table, the rest of the design procedure is the same for all
sequential circuits.
Sequence recognizers are especially hard! They’re the hardest example we’ll see in this class, so if you understand this
you’re in good shape.

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Finally, making the state table
0/0
1/0
1/0 0/0 0/0
A B C D
1/0
0/0 1/1
Present Next
State I nput State Output
Remember how the A 0 A 0
state diagram arrows A 1 B 0
B 0 C 0
correspond to rows of B 1 B 0
the state table: C 0 D 0
C 1 B 0
present input/output next D 0 A 0
state state D 1 B 1

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Step 2: Assigning binary codes to states
We have four states ABCD, so we need at least two flip-flops Q 1Q0.

The easiest thing to do is represent state A with Q 1Q0 = 00, B with 01, C with 10, and D with 11.
The state assignment can have a big impact on circuit complexity, but we won’t worry about that too
much in this class.

Present Next
Present Next
State I nput State Output
State I nput State Output
Q1 Q0 X Q1 Q0 Z
A 0 A 0
0 0 0 0 0 0
A 1 B 0
0 0 1 0 1 0
B 0 C 0
0 1 0 1 0 0
B 1 B 0
0 1 1 0 1 0
C 0 D 0
1 0 0 1 1 0
C 1 B 0
1 0 1 0 1 0
D 0 A 0
1 1 0 0 0 0
D 1 B 1
1 1 1 0 1 1

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Step 3: Finding flip-flop input values
Next we have to figure out how to actually make the flip-flops change from their present state into the
desired next state.
This depends on what kind of flip-flops you use!

We’ll use two JKs. For each flip-flip Q i, look at its present and next states, and determine what the
inputs Ji and Ki should be in order to make that state change.

Present Next
State I nput State Flip fl op inputs Output
Q1 Q0 X Q1 Q0 J1 K1 J0 K0 Z
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 0 1 0
1 1 0 0 0 0
1 1 1 0 1 1

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Finding JK flip-flop input values
For JK flip-flops, this is a little tricky. Recall the characteristic table:
If the present state of a JK flip-flop is 0 and we want the next state to be 1, then we have two
choices for the JK inputs:
◦ We can use JK=10, to explicitly set the flip-flop’s next state to 1.
◦ We can also use JK=11, to complement the current state 0.
So to change from 0 to 1, we must set J=1, but K could be either 0 or 1.
Similarly, the other possible state transitions can all be done in two different ways as well.

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 JK excitation table
An excitation table shows what flip-flop inputs are required in order to make a desired state change.

Q(t) Q(t+1) J K Operation

0 0 0 x No change/ reset
0 1 1 x Set/ complement
1 0 x 1 Reset/ complement
1 1 x 0 No change/ set

This is the same information that’s given in the characteristic table, but presented “backwards.”

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Excitation tables for all flip-flops
Q(t) Q(t+1) D Operation
0 0 0 Reset
0 1 1 Set
1 0 0 Reset
1 1 1 Set

Q(t) Q(t+1) J K Operation

0 0 0 x No change/ reset
0 1 1 x Set/ complement
1 0 x 1 Reset/ complement
1 1 x 0 No change/ set

Q(t) Q(t+1) T Operation

0 0 0 No change
0 1 1 Complement
1 0 1 Complement
1 1 0 No change

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Back to the example
We can now use the JK excitation table on the right to find the
correct values for each flip-flop’s inputs, based on its present
Q(t) Q(t+1) J K
and next states. 0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0

Present Next
State I nput State Flip fl op inputs Output
Q1 Q0 X Q1 Q0 J1 K1 J0 K0 Z
0 0 0 0 0 0 x 0 x 0
0 0 1 0 1 0 x 1 x 0
0 1 0 1 0 1 x x 1 0
0 1 1 0 1 0 x x 0 0
1 0 0 1 1 x 0 1 x 0
1 0 1 0 1 x 1 1 x 0
1 1 0 0 0 x 1 x 1 0
1 1 1 0 1 x 1 x 0 1

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Step 4: Find equations for the FF inputs and output
Now you can make K-maps and find equations for each of the four flip-flop inputs, as well as for the output Z.
These equations are in terms of the present state and the inputs.
The advantage of using JK flip-flops is that there are many don’t care conditions, which can result in simpler MSP equations.

J1 = X’ Q0

K1 = X + Q 0
Present Next
State I nput State Flip fl op inputs Output
Q 1 Q 0 J0 =XX + Q1Q 1 Q 0 J1 K1 J0 K0 Z
0 0 K0 =0X’ 0 0 0 x 0 x 0
0 0 1 0 1 0 x 1 x 0
0 1 0 1 0 1 x x 1 0
Z = Q 1 Q0 X
0 1 1 0 1 0 x x 0 0
1 0 0 1 1 x 0 1 x 0
1 0 1 0 1 x 1 1 x 0
1 1 0 0 0 x 1 x 1 0
1 1 1 0 1 x 1 x 0 1

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Step 5: Build the circuit
Lastly, we use these simplified equations to build the completed circuit.

J1 = X’ Q0
K1 = X + Q 0

J0 = X + Q 1
K0 = X’

Z = Q1Q0X

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 Timing diagram
Here is one example timing diagram for our sequence detector.
◦ The flip-flops Q1Q0 start in the initial state, 00.
◦ On the first three positive clock edges, X is 1, 0, and 0. These inputs cause Q 1Q0 to change, so after the third edge Q 1Q0 = 11.
◦ Then when X=1, Z becomes 1 also, meaning that 1001 was found.

The output Z does not have to change at positive clock edges. Instead, it may change whenever X changes, since Z = Q 1Q0X.

1 2 3 4
CLK

Q1

Q0

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Building the same circuit with D flip-flops
What if you want to build the circuit using D flip-flops instead?
We already have the state table and state assignments, so we can just start from Step 3, finding the
flip-flop input values.

D flip-flops have only one input, so our table only needs two columns for D 1 and D0.

Present Next Flip-fl op

State I nput State inputs Output
Q1 Q0 X Q1 Q0 D1 D0 Z
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 0 1 0
1 1 0 0 0 0
1 1 1 0 1 1

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D flip-flop input values (Step 3)
The D excitation table is pretty boring; set the D input to
whatever the next state should be.
Q(t) Q(t+1) D Operation
0 0 0 Reset
You don’t even need to show separate columns for D 1
and D0; you can just use the Next State columns. 0 1 1 Set
1 0 0 Reset
1 1 1 Set

Present Next Flip fl op

State I nput State inputs Output
Q1 Q0 X Q1 Q0 D1 D0 Z
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 0 1 0 0
0 1 1 0 1 0 1 0
1 0 0 1 1 1 1 0
1 0 1 0 1 0 1 0
1 1 0 0 0 0 0 0
1 1 1 0 1 0 1 1

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Finding equations (Step 4)
You can do K-maps again, to find:
D1 = Q1 Q0’ X’ + Q1’ Q0 X’

D0 = X + Q1 Q0’

Z = Q 1 Q0 X

Present Next Flip fl op

State I nput State inputs Output
Q1 Q0 X Q1 Q0 D1 D0 Z
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 0 1 0 0
0 1 1 0 1 0 1 0
1 0 0 1 1 1 1 0
1 0 1 0 1 0 1 0
1 1 0 0 0 0 0 0
1 1 1 0 1 0 1 1

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Building the circuit (Step 5)

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Flip-flop comparison
JK flip-flops are good because there are many don’t care values in the flip-flop
inputs, which can lead to a simpler circuit.

D flip-flops have the advantage that you don’t have to set up flip-flop inputs at all,
since Q(t+1) = D. However, the D input equations are usually more complex than
JK input equations

In practice, D flip-flops are used more often.

◦ There is only one input for each flip-flop, not two.
◦ There are no excitation tables to worry about.
◦ D flip-flops can be implemented with slightly less hardware than JK flip-
flops.

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111 Sequence Detector –Moore Machine

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 Summary of FSM Design
:

◦ Draw a state diagram and Make a state table. This step is usually
the hardest.
◦ Assign binary codes to the states if you didn’t already.
◦ Use the present states, next states, and flip-flop excitation tables
to find the flip-flop input values.
◦ Find simplified equations using K-Map for the flip-flop inputs and
outputs and build the circuit.

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ASM

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Principle components

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Principle components

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111 Sequence Detector-Mealy machine

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 State Reduction Techniques
Removing redundant states
Row elimination
Implication Table

Advantages:
Low power
Fast
Less hardware

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Thank
You
Any Questions???

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