Unit 3
Unit 3
Status command:
It is used to text the various status
condition in the peripheral and
interface.
Output data:
The interface to respond by transferring data
from the bus into one of its registers.
Input data:
In this case interface receive an item of data from
peripheral and places in registered.
I/O VERSUS MEMORY
BUS
In addition to communicating with I/O the
processor must communicate with memory unit.
There are three ways that computer bus can be
used to communicate with memory and I/O.
Use one common bus for memory and I/O but
have separate control line, but same Address line
and data.
Use one common bus for memory and I/O with
common control lines
Use two separate bus one for memory and other
for I/O.
In the last method the computer has independent
set of data , address and control bus, one for
accessing memory and the other for I/O.
This is done by I/O processor(IOP).
In addition to CPU the memory communicate with
CPU and IOP through memory bus.
I/O is also called as data channel.
The purpose of IOP is to provide and independent
pathway for the transfer of information between
external devices and internal memory.
ISOLATED VERSUS MEMORY MAPPED I/O
Many computers use one common bus to transfer
information between memory or I/O and the CPU.
The distinction between memory transfer and I/O
transfer is made through separate read and write
lines.
The CPU specifies whether the Address on address
on address line is for a memory word or for an
interface register by enabling one of two possible
read or write lines.
I/O read and write control line are enable during
an memory transfer.
Isolated I/O method for assigning address in a
common bus.
In isolated I/O configuration CPU has distinct
input and output instruction and the instructions
associated with the dress of an interface register.
When CPU fetches and decodes the operation code
an input or I/O instruction address associated with
the instruction into common address line.
Memory I/O have different data type or each data
lines.
Memory address value are hot affected by address
since each have it own address space.
It employ only one set of read and write signals
and not distinguish between memory and I/O
address .
This configuration referred as memory mapped
I/O.
There is no specific input or output instructions.
CPU can manipulate I/O data in interface registers
with same instruction for manipulate memory
word.
The advantage is it can loaded store instruction for
reading and writing.
Also used to input and output data from I/O
registers.
Example of I/O interface
The block diagram consist of two data registers
called port , control registers , status registes , bus
buffers , and timing and control circuits.
The chip select and register select determine the
address assigned to the interface.
The I/O read and I/O write determines input and
output.
The four registers directly communicate with I/O
devices attached to the interface.
The control is send to the control register
the status information is received from
status register.
The interface register communicates with
cpu through the directional bus.
The address bus select the interface unit
through the chip select and two register
select inputs