Lecture # 4

Introduction to Boolean algebra/Types of input/ Logic gates/

By: Muhammad Zain Uddin

email: [email protected]

M. ZAIN UDDIN 1
Digital Logic Design

Muhammad Zain Uddin

Lecturer,
IBA
Review of previous lecture
SOP POS equation understanding
Boolean Rules and Laws
Simplification of Boolean equation
Gate Equivalecy
Designing Rules finalizartion

M. ZAIN UDDIN 3
Basic Designing Rules
Step 1: identify number of inputs and individual input bits
Step 2: draw truth table if total number of inputs bits
Step 3: identify number of outputs and output bits
Step 4: Identify output value on each combination of inputs
Step 5: identify whether any output can be solve using single gate or related to single or multiple inputs.
Step 6: Now determine Boolean expression of each output bit.
Step 7 : Simplify this equation using Boolean rules laws or Kmap
Step 8: Draw the circuit diagram of that simplified equation.

M. ZAIN UDDIN 4
Combinational Logic Circuits
An example of an SOP implementation is shown. The SOP expression is an AND-
OR combination of the input variables and the appropriate complements.

A
B ABC
C X = ABC + DE SOP

D
DE
E
Combinational Logic Circuits
When the output of a SOP form is inverted, the circuit is called an AND-OR-Invert
circuit. The AOI configuration lends itself to product-of-sums (POS)
implementation.

An example of an AOI implementation is shown. The output expression can be

changed to a POS expression by applying DeMorgan’s theorem twice.

A
B ABC
C X = ABC + DE X = ABC + DE AOI

D X = (ABC)(DE) DeMorgan
E DE X = (A + B + C)(D + E) POS
Implementing Combinational Logic
Implementing a SOP expression is done by first forming the AND terms; then
the terms are ORed together.

Show the circuit that will implement the Boolean

expression X = ABC + ABD + BDE. (Assume that the
variables and their complements are available.)
Start by forming the terms using three 3-input AND gates.
Then combine the three terms using a 3-input OR gate.
A
B
C
A X = ABC + ABD + BDE
B
D
B
D
E
Solution continued…

Circuit: A
C X= AC + AB
A
B

The result is shown as a sum of products.

It is a simple matter to implement this form using only NAND gates as shown
in the text and following example.
Converting Eq. into Standard
SOP

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Converting Eq. into Standard
POS

M. ZAIN UDDIN 10
Example

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NAND Logic
Convert the circuit in the previous example to one that uses
only NAND gates.

Recall from Boolean algebra that double inversion cancels. By adding inverting
bubbles to above circuit, it is easily converted to NAND gates:

A
C X= AC + AB
A
B
Universal Gates
NAND gates are sometimes called universal gates because they can be
used to produce the other basic Boolean functions.

A A A AB
B
Inverter AND gate

A A
A+B A+B
B B

OR gate NOR gate

Universal Gates
NOR gates are also universal gates and can form all of the basic gates.

A A A A+ B
B
Inverter OR gate

A A
AB AB
B B

AND gate NAND gate

NAND Logic
Recall from DeMorgan’s theorem that AB = A + B. By using equivalent
symbols, it is simpler to read the logic of SOP forms. The earlier example
shows the idea:

A
C X= AC + AB
A
B

The logic is easy to read if you (mentally) cancel the two connected bubbles on
a line.
NOR Logic
Alternatively, DeMorgan’s theorem can be written as A + B = A B. By
using equivalent symbols, it is simpler to read the logic of POS forms. For
example,

A
B X = (A + B)(A + C)
A
C

Again, the logic is easy to read if you cancel the two connected bubbles on
a line.
Simplification Examples

AB+A (B+C) +B (B+C)

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Solution Cont.

M. ZAIN UDDIN 18
Pulsed Waveforms
For combinational circuits with pulsed inputs, the output can be predicted
by developing intermediate outputs and combining the result. For example,
the circuit shown can be analyzed at the outputs of the OR gates:

A
A
B G1
B
G3
C
C
D G2
D
G1
G2
G3
Pulsed Waveforms
Inputs Output
Alternatively, you can develop the truth table for
A B C D X
the circuit and enter 0’s and 1’s on the waveforms.
Then read the output from the table. 0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
A
G1 0 0 1 1 1
B 0 1 0 0 0
G3 0 1 0 1 1
C 0 1 1 0 1
G2 1
D 0 1 1 1
1 0 0 0 0
A 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0
1 0 1 0 0
B 0 1 1 0 0 1 1 0 0 0 1 0 1 1 0
1 1 0 0 0
C 0 0 0 1 1 1 1 0 0 0
1 1 0 1 1
D 0 0 0 0 0 0 0 1 1 0 1 1 1 0 1
1 1 1 1 1
G3 0 0 0 0 1 1 1 0 1 0
Karnaugh maps
The Karnaugh map (K-map) is a tool for simplifying combinational logic with
3 or 4 variables. For 3 variables, 8 cells are required (23).

The map shown is for three variables labeled A,

B, and C. Each cell represents one possible
product term. ABC ABC

Each cell differs from an adjacent cell by only

one variable. ABC ABC

ABC ABC

ABC ABC
Karnaugh maps
Cells are usually labeled using 0’s and 1’s to represent the variable and its
complement.

C The numbers are entered in gray code, to

AB 0 1 force adjacent cells to be different by only
one variable.
00

01 Ones are read as the true variable and zeros

Gray
are read as the complemented variable.
code
11

10
Karnaugh maps
Alternatively, cells can be labeled with the variable letters. This makes it
simple to read, but it takes more time preparing the map.

CC C C
Read the terms for the yellow
ABAB ABC ABC
cells.
ABAB ABC
ABC ABC

The cells are ABC and ABC. ABAB ABC ABC

ABAB
ABC ABC
ABC
Karnaugh Map Implementation
For basic combinational logic circuits, the Karnaugh map can be read and the
circuit drawn as a minimum SOP.
A Karnaugh map is drawn from a truth table. Read the
minimum SOP expression and draw the circuit.

C C
1. Group the 1’s into two overlapping
AB 1
B changes groups as indicated.
across AB 1 1 2. Read each group by eliminating any
this variable that changes across a boundary.
boundary AB 3. The vertical group is read A C.
C changes 4. The horizontal group is read AB.
AB across
this X = A C +AB
boundary
Karnaugh maps
A 4-variable map has an adjacent cell on each of its four boundaries as
shown.

Each cell is different only by one

CD CD CD CD variable from an adjacent cell.
AB
Grouping follows the rules given in the
text.
AB The following slide shows an example
of reading a four variable map using
AB binary numbers for the variables…

AB
Karnaugh maps
Group the 1’s on the map and read the minimum logic.
C changes across
outer boundary
CD 1. Group the 1’s into two separate
00 01 11 10
AB
groups as indicated.
00 1 1
B changes 2. Read each group by eliminating
01 1 1 any variable that changes across a
boundary.
11 1 1
B changes 3. The upper (yellow) group is read as
10 1 1 AD.
C changes
4. The lower (green) group is read
X
as AD.
X = A D +AD