CHAPTER 10:

MEMORY DEVICES

Credit to:
MARLINA YAKNO
NORASYIKIN FADILAH
 CHAPTER GUIDELINE
8.1 MEMORY TERMINOLOGY

8.2 MEMORY OPERATIONS

8.3 ROM (TYPES & ARCHITECTURE)

8.4 RAM (TYPES & ARCHITECTURE)

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COMPUTER SYSTEM COMPONENTS

Figure 5.1 The von Neumann architecture

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COMPUTER SYSTEM COMPONENTS

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8.1 MEMORY TERMINOLOGY

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 TERMINOLOGY

Memory • Electrical circuit that stores 1-bit

of information
cell
1
2
3

Memory • A group of bits in a memory that

represents instructions/data.
4
5

word • Typically 8, 16, 32 or 64 bits 6

7
8

Byte • A group of 8 bits

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 TERMINOLOGY

Capacity • A way to specify how many bits can be stored in a

device
• Eg: 4096 20-bit words = 81,920 bits = 4096*20
@ Density = 4K*20

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 TERMINOLOGY
Memory • A number that identifies the
Address location of a word in a memory.

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8.2 MEMORY OPERATIONS

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 WRITE OPERATION
• New data overwrites the original data.
Address register Data register
1 0 1 1 0 0 0 1 1 0 1
1. The address is placed on
Address decoder
Byte organized memory the address bus.
array

1
0
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
2. Data is placed on the data
2 1 0 0 0 0 0 0 1 bus.
Address bus 3 1 1 1 1 1 1 0 0
4 0 0 0 0 0 1 1 0 2
5 1 0 0 0 1 1 0 1
3. A write command is issued.
6 1 1 1 1 1 1 1 1 Data bus
7 0 0 0 0 1 1 1 1
3

Write

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 READ OPERATION
• A “copy” operation, as the original data is not
changed.
Address register Data register
0 1 1 1 1 0 0 0 0 0 1
1. The address is placed on
Byte organized memory the address bus.
Address decoder array

1
0
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
2. A read command is issued.
2 1 0 0 0 0 0 0 1 3
3 1 1 0 0 0 0 0 1
Data bus
3. A copy of the data is placed
4 0 0 0 0 0 1 1 0
5 1 0 0 0 1 1 0 1 in the data bus and shifted
6 1 1 1 1 1 1 1 1 into the data register.
7 0 0 0 0 1 1 1 1

Read

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 Address & Data Line
(Example)
1024*8 means that you have:
- 1024 locations
- 8 bits per location
• Address Lines:
Assuming that number of address lines (address bits) is n, how can we find n?
If n=1, you can only address 2 locations (0 and 1).
If n=2, you can address 4 locations (0, 1, 2, and 3).
Hence, number of addressable locations = 2^n.
Given that number of addressable locations = 1024, then 1024=2^n
This means that n=log2(1024) = 10.
• Data Lines:
You have 8 bits for every location, therefore your memory needs a data bus with 8 lines. Every
time you read a location (by loading its address on the address bus), the 8 bits that are stored
at that location are loaded (by the memory chip) on the 8-line data bus.
• Memory size:
As obvious, your memory has 1024*8 bits (8192 bits). Or simply, 1024 bytes

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8.3 READ ONLY MEMORY (ROM)

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OVERVIEW ROM

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ROM BLOCK DIAGRAM

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ROM ARCHITECTURE

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ROM ARCHITECTURE

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TYPES OF ROM

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 MASK ROM
• Characteristics:
– Device permanently programmed in factory by
manufacturer
– Must be large number (≈10,000 pieces) to justify
cost
– Once manufactured, can not be erased or
reprogrammed

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 PROGRAMMABLE ROM (PROM)
• Characteristics:
– Replace the diode in each cell of a Mask ROM by
diode + fuse (fusible-link PROM).
– Initial contents are all 1s.
– Users program memory by blowing fuses to create
0s.
– Once programmed, can not be erased for
reprogramming.
– One-time programmable (OTP), need to change
program? - throw it away
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ERASABLE PROGRAMMABLE ROM (EPROM)

• Characteristics:
– Reprogrammed as often as desired.
– Erasing is by exposure to UV light for 20 minutes
or more.
– The erase operation erases the entire chip-there is
no way to select only certain addresses to be
erased

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ELECTRICALLY ERASABLE PROM (EEPROM)

• Characteristics:
– Erased with voltage pulses.
– Ability to erase and rewrite individual bytes (8-bit
words) in the memory array electrically.
– During a write operation, internal circuitry
automatically erases all of the cells at an address
location prior to writing in the new data. This byte
erasability makes it much easier to make changes
in the data stored in an EEPROM

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8.4 RANDOM ACCESS MEMORY
(RAM)

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 OVERVIEW RAM
• Any memory address location is as easily
accessible as any other.

• Is used in computers for the temporary storage of

programs and data.

• Disadvantage: it is volatile and will lose all stored

information if power is interrupted or turned off.

• Advantage: can be written into and read from

rapidly with equal ease
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TYPES OF RAM

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 STATIC RAM (SRAM)
• Characteristics:
– Can store data as long as power is applied to the
chip.
– Each cell is basically a flip-flop
– Very simple interfacing; writes & reads at same
speed
– Very fast (access times under 10 ns available)
– Consume a lot of power
– Poor density memory available

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 SRAM ARCHITECTURE

(a) Memory Symbol (b) Internal Architecture

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 SRAM OPERATION
• Read cycle sequence:
- A valid address is put on the address bus
- Chip select (CS) is LOW
- Output enable (OE) is LOW
- Data is placed on the data bus

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 SRAM OPERATION
• Write cycle sequence:
- A valid address is put on the address bus
- Chip select (CS) is LOW
- Write enable (WE) is LOW
- Data is placed on the data bus

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 DYNAMIC RAM (DRAM)
• Characteristics:
– High capacity, low power requirement, moderate
operating speed.
– Employ capacitors to stores electric charge whose
level represents a 1 or 0
– Capacitors dissipate with time and hence the
charge must be restored frequently

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DRAM ARCHITECTURE

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DRAM ARCHITECTURE

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 DRAM OPERATION
• Write cycle sequence:
– switches SW1 & SW2 = CLOSE, while SW3 &SW4 =
OPEN.
– This connects the input data to capacitor (C).
– A logic 1 at the data input charges C
– A logic 0 discharges it.
– Then the switches are open so that C is
disconnected from the rest of the circuit.

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 DRAM OPERATION
• Read cycle sequence:
– switches SW2, SW3, & SW4 = CLOSE, and SW1 = OPEN.
– This connects the stored capacitor voltage to the sense
amplifier.
– The sense amplifier compares the voltage to determine
if it is a logic 0 or 1, and it produces a solid 0 V or 5 V
for the data output
– This data output is also connected to C (SW2 and SW4
are closed) and refreshes the capacitor voltage by
recharging or discharging

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