OPERATORS & ATTRIBUTES

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Purpose of this chapter

• In this chapter:
• The purpose of this chapter, along with the
preceding chapters, is to lay the basic
foundations of VHDL.
• It is indeed impossible to write any code
efficiently without undertaking first the sacrifice
of understanding:
• data types,
• operators,
• attributes.

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OPERATORS

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Operators
• VHDL provides several kinds of pre-defined
operators:
• Assignment operators
• Logical operators
• Arithmetic operators
• Comparison operators
• Relational operators
• Shift operators
• Concatenation operators
• Matching comparison operators
• …
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Assignment operators
<= Used to assign a value to a SIGNAL.

:= Used to assign a value to a VARIABLE,

CONSTANT, or GENERIC. Used also for
establishing initial values.

=> Used to assign values to individual vector

elements or with OTHERS.

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Example (Assignment operators)

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Logical Operators
• Used to perform logical operations. The data
must be of type:
• BIT (BIT_VECTOR)
• STD_LOGIC (STD_LOGIC_VECTOR)
• STD_ULOGIC (STD_ULOGIC_VECTOR)
• BOOLEAN_VECTOR,
• UFIXED
• SFIXED
• FLOAT
• (UN)SIGNED can also be included in this list if
the chosen definition package is numeric_std
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Logical Operators …

• The logical operators are:

• NOT
• AND
• OR
• NAND
• NOR
• XOR
• XNOR

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Example (Logical Operators)

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Arithmetic Operators
• Used to perform arithmetic operations. The
data can be of type
• INTEGER
• SIGNED, UNSIGNED
• (numeric_std or std_logic_arith)
• REAL
• (Not synthesizable).
• STD_LOGIC_VECTOR
• (ieee.std_logic_signed and
ieee.std_logic_unsigned)
• UFIXED, SFIXED, and FLOAT
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Arithmetic Operators

• If one of the packages for (un)signed types

(numeric_std or std_logic_arith) is declared
in the code, then (UN)SIGNED can also be
used.
• If the package std_logic_unsigned,
std_logic_signed, or numeric_std_unsigned
is also declared, then
STD_LOGIC_VECTOR can be employed
as well.

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Arithmetic Operators …
+ Addition
- Subtraction
* Multiplication
/ Division
** Exponentiation
MOD Modulus (Not synthesizable except integer)
REM Remainder (Not synthesizable except
integer)
ABS Absolute (Not synthesizable except
integer)

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Comparison Operators

= Equal to
/= Not equal to
< Less than
> Greater than
<= Less than or equal to
>= Greater than or equal to

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Shift Operators

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Shift Operators

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Shift Operators

• BIT-VECTOR
• (un)signed types
• (numeric_std or std_logic_arith)
• STD-LOGIC-VECTOR
• (std_logic_unsigned, std_logic_signed)
• BOOLEAN_VECTOR,
• UFIXED, and SFIXED

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Shift Operators

• x is a BIT_VECTOR signal with value

x = "01001"

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Concatenation Operators

• BIT_VECTOR,
• BOOLEAN_VECTOR (VHDL 2008),
• INTEGER_VECTOR (VHDL 2008),
• STD_(U)LOGIC_VECTOR,
• (UN)SIGNED
• STRING

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Concatenation Operators

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Matching Comparison Operators

• Matching equality operator (?=)

• Matching inequality operator (?/=)
• Matching less than operator (?<)
• Matching
• Matching less than or equal to operator (?
<=)
• Matching greater than or equal to operator
(?>=) greater than operator (?>)

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Matching Comparison Operators
• BIT
• BIT_VECTOR (only equality and inequality),
• STD_(U)LOGIC
• STD_(U)LOGIC_VECTOR
• (UN)SIGNED (numeric_std).
• UFIXED and SFIXED.

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Matching Comparison Operators
• The purpose of this operator is to allow the comparison of
logic values instead of enumerated symbols in
STD_ULOGIC based data. For example,
• "IF 'H' = '1' . . ." returns FALSE because these symbols
are different,
• "IF 'H' ?= '1' . . ." returns '1' because both 'H' and '1' are
interpreted as logic value '1'.
• A similar reasoning is valid for 'L' and '0'.
• When 'X', 'Z', or 'W' are involved in the comparison, this
operator (?=) returns 'X', and so on.
• In the case of BIT, it simply returns '1' or '0' instead of
TRUE or FALSE.

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Other Operators
• MINIMUM and MAXIMUM
• "MAXIMUM(0, 55, 23)" returns 55
• Condition operator ("??"): Converts a BIT or STD_(U)LOGIC value
into a BOOLEAN value. For example, "?? a AND b" returns TRUE
when a AND b = '1' or FALSE otherwise.
• TO_STRING: Converts a value of type BIT, BIT_VECTOR,
STD_LOGIC_VECTOR, and so on into STRING.
• …

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Operation Synthesis
• There are no synthesis restrictions regarding
addition, subtraction, multiplication, or division
with integers.
• For exponentiation, expressions with static
exponent are supported; if the exponent is
nonstatic, then the base might be required to be
static or even a power of 2 (shift operation).
• The other three operators (ABS, REM, MOD) are
also synthesizable without restrictions for
integers.

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Operators Summary

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Operator Overloading

• As an example, the pre-defined ‘‘+’’

operator does not allow addition between
data of type BIT.
• We can define our own operators, using the
same name as the pre-defined ones. For
example, we could use ‘‘+’’ to indicate a
new kind of addition, this time between
values of type BIT_VECTOR. This
technique is called operator overloading.

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Example (Operator Overloading)

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ATTRIBUTES

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Data Attributes
• The pre-defined, synthesizable data
attributes are the following:
• d’LOW: Returns lower array index
• d’HIGH: Returns upper array index
• d’LEFT: Returns leftmost array index
• d’RIGHT: Returns rightmost array index
• d’LENGTH: Returns vector size
• d’RANGE: Returns vector range
• d’REVERSE_RANGE: Returns vector range in
reverse order

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Data Attributes (enumerated type)
• If the signal is of enumerated type, then:
• d’VAL(pos): Returns value in the position specified
• d’POS(value): Returns position of the value specified
• d’LEFTOF(value): Returns value in the position to the
left of the value specified
• d’VAL(row, column): Returns value in the position
specified; etc.

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Data Attributes of Scaler Types

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Data Attributes

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Data Attributes of Array Types

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Example (Data Attributes)

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Example (Data Attributes)

d'LOW=0
d'HIGH=7
d'LEFT=7
d'RIGHT=0
d'LENGTH=8
d'RANGE=(7 downto 0)
d'REVERSE_RANGE=(0 to 7)

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Example (Data Attributes) …

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Example (Data Attributes)

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Example (Data Attributes)

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Predefined Attributes of Signals

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 Signal Attributes
• Let us consider a signal s. Then:
• s’EVENT: Returns true when an event occurs on s
• s’STABLE: Returns true if no event has occurred on
s
• s’QUIET <time>: Returns true if no event has
occurred during the time specified
• s’LAST_EVENT: Returns the time elapsed since
last event
• s’LAST_VALUE: Returns the value of s before the
last event; etc.

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Example (Signal Attributes)

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