Introduction

to
Microprocessor and Microcontrollers
 Syllbus
• UNIT – I: Architecture of 8086Microprocessor
• UNIT – II: Instruction set of 8086:
• UNIT – III: Interfacing with 8086
• UNIT – IV: The 8051 Architecture
• UNIT – V: Instruction set of 8051
• UNIT VI: Applications of 8051

TEXT BOOKS :
• Advanced microprocessor & Peripherals - A.K.Ray&K.M.Bhurchandi, TMH,
2000.
• Microprocessors and interfacing – Douglas V. Hall, TMH, 2nd Edition, 1999.
Microprocessor and Microcontrollers
• Microprocessor ( CPU)

A processor, or "microprocessor,"
is a small chip that resides in
computers
Means small
• Processor means which executes
all instructions
 Microcontroller
• A microcontroller (MCU
for microcontroller unit) is a small computer on
a single integrated circuit (IC) chip.
• A microcontroller contains one or more CPUs
(processor cores) along with memory and
programmable input/output peripherals.
8086 Microprocessor
 What is a Microprocessor?

 A microprocessor is a multipurpose, programmable

logic device that reads binary instructions from a
storage device called memory accepts binary data as
input and processes data according to those
instructions and provides result as output.

 Computer's Central Processing Unit (CPU) built on

a single Integrated Circuit (IC) is called
a microprocessor.
Block Diagram of a Microcomputer
 microcomputer.
 A digital computer with one microprocessor which
acts as a CPU is called microcomputer.
 A microprocessor consists of an ALU, control unit
and register array. Where ALU performs arithmetic
and logical operations on the data received from an
input device or memory.
 Control unit controls the instructions and flow of data
within the computer and register array consists of
registers.
 Evolution of Microprocessors

 We can categorize the microprocessor according to the

generations or according to the size of the
microprocessor:
 First Generation (4 - bit Microprocessors)
 Second Generation (8 - bit Microprocessor)
 Third Generation (16 - bit Microprocessor)
 Fourth Generation (32 - bit Microprocessors)
 Fifth Generation (64 - bit Microprocessors)
 Other improved 64-bit processors are Celeron, Dual,
Quad, Octa Core processors.
Evolution of Microprocessors
Evolution of Microprocessors
 TYPES OF MICROPROCESSORS
There are basically 5 kinds of microprocessors namely
1. Complex Instruction Set Microprocessors
2. Reduced Instruction Set Microprocessors
3. Superscalar Processors
4. The Application Specific Integrated Circuit
5. Digital Signal Multiprocessors, etc.
Intel 8086
 8086 Microprocessor is
an enhanced version of
8085Microprocessor that
was designed by Intel in
1976.
 It was the first 16 bit
Microprocessor.
 It is available in 40 pin
DIP
 It consists of 29000
transistors.
 Unit 1
• UNIT – I: Architecture of 8086 Microprocessor:
• Contents of unit- 1
• Features of 8086
• Memory segmentation,
• BIU and EU.
• General purpose registers.
• 8086 flag register and function of 8086 Flags.
• Pin diagram of 8086-Minimum mode and maximum mode
of operation.
• Timing Diagram.
 Features of a microprocessor

• Speed: clock frequency or instruction per second

• Instruction set: number of instruction it can handle
• Data bus: the number of data lines it can process at a time
• Address bus: the number of address lines which will indicate
the maximum memory it can have
• Control bus: the number of control lines to control various
functions
• Register array: the number and their width
• Manufacturing technology: PMOS,NMOS,and HMOS
• Design technology: CISC or RISC
• Power :voltage and current requirement
• Architecture : vo-numen and Harvard
• Packaging shapes :size and number of pins
 Features of 8086
• Introduced in 1978 by intel .
• Comes in Dual-In-Line Package(DIP) IC.
• 8086 is a 16-bit N-channel HMOS microprocessor .
• Works on 5 volts power supply and draws a current of 360 ma,
with an internal circuitry made up of 29K transistors.
• It consists of an electronic circuitry built using 29000 transistors.
• It is built on single semiconductor chip and packaged in an 40-pin
IC.
• It has 20-bit address bus and 16-bit data bus.
• It can directly address upto 2 20 I.e., 1M bytes of memory.
• The 16-bit data word is divided into lower-order byte and higher
order byte. 2 16 =65536 I/O can be interfaced

8086 18
 Features of 8086
• The 20-bit address bus is time multiplexed:
• The lower order 16-bit address bus is time multiplexed
with data bus.
• The higher order 4-bit address bus is time multiplexed
with status signals.
• The maximum internal clock for 8086 is 5MHz.
• 8086 chip does not have the facility of internal clock
generation.
• (the INTEL 8284 clock generator/driver is used to
generate the clock signal for 8086 microprocessor
• The clock signal is divided by 3 in case of 8086 for
internal clock requirements.
8086 19
 Features of 8086
• 8086 uses I/O mapped I/O techniques hence I/O devices are
accessed by using separate 16-bit address
• 8086 operates in two different modes
 Minimum mode
( It works as a simple single processor system when configured
in minimum mode)
 Maximum mode
( It works as a multiprocessor system i.e., along with math
coprocessor and I/O coprocessor when configured in maximum
mode)

8086 20
 8086
Microprocessor

Overview
First 16- bit processor released by Addressable memory space is
INTEL in the year 1978 organized in to two banks of 512 kb
each; Even (or lower) bank and Odd (or
higher) bank. Address line A0 is used to
Originally HMOS, now manufactured select even bank and control signal
using HMOS III technique is used to access odd bank

Uses a separate 16 bit address for I/O

Approximately 29, 000 transistors, 40 mapped devices  can generate 216 =
pin DIP, 5V supply 64 k addresses.

Operates in two modes: minimum

Does not have internal clock; external mode and maximum mode, decided by
asymmetric clock source with 33% duty the signal at MN and pins.
cycle

20-bit address to access memory  can

address up to 220 = 1 megabytes of
memory space.

21
Architecture
 Microprocessor
Functional blocks
Various conditions of the
Computational Unit;
results are stored as
performs arithmetic and Internal storage of data
status bits called flags in
logic operations
flag register

Register array or Data Bus

internal memory
ALU
Generates the
address of the
Instruction
Flag instructions to be
decoding unit
Register fetched from the
memory and send
through address
bus to the
Timing and memory
control unit PC/ IP

Control Bus Address Bus

Generates control signals for

internal and external Decodes instructions; sends
operations of the information to the timing and
control unit 23
microprocessor
Microprocessor

Program controlled semiconductor device (IC)

which fetches (from memory), decodes and
executes instructions.

It is used as CPU (Central Processing Unit) in

computers.

24
 Microprocessor Fifth Generation Pentium

Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology  Faster speed, Higher Virtual memory space 240 bytes = 1 Tb
packing density Floating point hardware
16 bit processors  40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Dynamically relatable programs
Processor has multiply/ divide arithmetic Intel 80386
hardware
More powerful interrupt handling
capabilities Second Generation
Flexible I/O port addressing During 1973
NMOS technology  Faster speed, Higher
Intel 8086 (16 bit processor) density, Compatible with TTL
4 / 8/ 16 bit processors  40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors  16 pins nesting
8 and 16 bit processors  40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are 25
multiplexed Intel 8085 (8 bit processor)
Pins and signals
 8086
Common signals
Microprocessor

Pins and Signals

AD -AD (Bidirectional)
0 15

Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

multiplexed with status signals

27
 8086
Common signals
Microprocessor

Pins and Signals

BHE (Active Low)/S 7 (Output)

Bus High Enable/Status

It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7.

MN/ MX

MINIMUM / MAXIMUM

This pin signal indicates what mode the

processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.

It is an output signal.
It is active when low.
28
 8086
Common signals
Microprocessor

Pins and Signals TEST

input is tested by the ‘WAIT’ instruction.

8086 will enter a wait state after

execution of the WAIT instruction and
will resume execution only when the is
made low by an active hardware.

This is used to synchronize an external

activity to the processor internal
operation.

READY

This is the acknowledgement from the

slow device or memory that they have
completed the data transfer.

The signal made available by the devices

is synchronized by the 8284A clock
generator to provide ready input to the
8086.

The signal is active high. 29

 8086
Common signals
Microprocessor

Pins and Signals

RESET (Input)

Causes the processor to immediately

terminate its present activity.

The signal must be active HIGH for at

least four clock cycles.

CLK

The clock input provides the basic timing

for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.

INTR Interrupt Request

This is a triggered input. This is sampled

during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request
is pending, the processor enters the
interrupt acknowledge cycle.

This signal is active high and internally

synchronized. 30
 8086
Microprocessor
Min/ Max Pins

Pins and Signals

The 8086 microprocessor can work in two
modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/ MX(Active low).

When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.

31
 8086
Minimum mode signals
Microprocessor

Pins and Signals Pins 24 -31

For minimum mode operation, the MN/ is tied to

VCC (logic high)

8086 itself generates all the bus control signals

DT/ (Data Transmit/ Receive) Output signal from the

processor to control the direction of data flow through
the data transceivers

(Data Enable) Output signal from the processor used as

out put enable for the transceivers

ALE (Address Latch Enable) Used to demultiplex the address

and data lines using external latches

M/ Used to differentiate memory access and I/O access. For

memory reference instructions, it is high. For IN and OUT
instructions, it is low.

Write control signal; asserted low Whenever processor

writes data to memory or I/O port

(Interrupt Acknowledge) When the interrupt request is

accepted by the processor, the output is low on this line.

32
 8086
Minimum mode signals
Microprocessor

Pins and Signals Pins 24 -31

For minimum mode operation, the MN/ is tied to

VCC (logic high)

8086 itself generates all the bus control signals

HOLD Input signal to the processor form the bus masters as a

request to grant the control of the bus.

Usually used by the DMA controller to get the control of

the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the processor

to the bus master requesting the control of the bus
through HOLD.

The acknowledge is asserted high, when the processor

accepts HOLD.

33
 8086
Maximum mode signals
Microprocessor

Pins and Signals

During maximum mode operation, the MN/ is
grounded (logic low)

Pins 24 -31 are reassigned

,, Status signals; used by the 8086 bus controller to

generate bus timing and control signals. These are
decoded as shown.

34
 8086
Maximum mode signals
Microprocessor

Pins and Signals

During maximum mode operation, the MN/ is
grounded (logic low)

Pins 24 -31 are reassigned

, (Queue Status) The processor provides the status of

queue in these lines.

The queue status can be used by external device to track

the internal status of the queue in 8086.

The output on QS0 and QS1 can be interpreted as shown

in the table.

35
 8086
Maximum mode signals
Microprocessor

Pins and Signals

During maximum mode operation, the MN/ is
grounded (logic low)

Pins 24 -31 are reassigned

, (Bus Request/ Bus Grant) These requests are used by

other local bus masters to force the processor to release
the local bus at the end of the processor’s current bus
cycle.

These pins are bidirectional.

The request on will have higher priority than

An output signal activated by the LOCK prefix instruction.

Remains active until the completion of the instruction

prefixed by LOCK.

The 8086 output low on the pin while executing an

instruction prefixed by LOCK to prevent other bus
masters from gaining control of the system bus.

36
Architecture
Architecture of 8086 Microprocessor
 8086
Microprocessor

Architecture

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
39
 8086 Architecture
• Architecture of 8086 is pipeline type of architecture.
• The architecture of 8086 is divided into two functional parts i.e.,
i. Execution unit (EU)
ii. Bus interface unit (BIU)
iii. Dividing the work between these two units’ speeds up
processing.
These two units work asynchronously.
• Functional division of architecture speeds up the processing, since
BIU and EU operate parallel and independently i.e., EU executes
the instructions and BIU fetches another instruction from the
memory simultaneously.

• As the whole architecture is divided into two independent

functional parts and both the subsystem’s operations can be
overlapped, hence the architecture is PIPELINING type of
architecture.
8086 40
 8086 HAS PIPELINING ARCHITECTURE
• While the EU is decoding an instruction or executing an instruction,
which does not require use of the buses,
• the BIU fetches up to six instruction bytes for the following
instructions.
• The BIU stores these pre-fetched bytes in a first-in-first-out register
set called a queue.
• When the EU is ready for its next instruction from the queue in the
BIU. This is much faster than sending out
• an address to the system memory and waiting for memory to send
back the next instruction byte or bytes.
• Except in the case of JMP and CALL instructions, where the queue
must be dumped and then reloaded starting from a new address, this
pre-fetch and queue scheme greatly speeds up processing.
• Fetching the next instruction while the current instruction executes is
called pipelining.
 8086
Bus Interface Unit (BIU)
Microprocessor

Architecture Dedicated Adder to

generate 20 bit address

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

Segment Registers >> 42

 8086
Bus Interface Unit (BIU)
Microprocessor

Architecture
Segment
Registers

8086’s 1-megabyte memory The 8086 can directly address four Programs obtain access to code
is divided into segments of segments (256 K bytes within the 1 and data in the segments by
up to 64K bytes each. M byte of memory) at a particular changing the segment register
time. content to point to the desired
segments.

43
 8086
Bus Interface Unit (BIU)
Microprocessor

Architecture
Segment Code Segment Register
Registers
16-bit

CS contains the base or start of the current code segment; IP contains the
distance or offset from this address to the next instruction byte to be fetched.

BIU computes the 20-bit physical address by logically shifting the contents of CS
4-bits to the left and then adding the 16-bit contents of IP.

That is, all instructions of a program are relative to the contents of the CS
register multiplied by 16 and then offset is added provided by the IP.

44
 8086
Bus Interface Unit (BIU)
Microprocessor

Architecture
Segment Data Segment Register
Registers
16-bit

Points to the current data segment; operands for most instructions are fetched
from this segment.

The 16-bit contents of the Source Index (SI) or Destination Index (DI) or a 16-bit
displacement are used as offset for computing the 20-bit physical address.

45
 8086
Bus Interface Unit (BIU)
Microprocessor

Architecture
Segment Stack Segment Register
Registers
16-bit

Points to the current stack.

The 20-bit physical stack address is calculated from the Stack Segment (SS) and
the Stack Pointer (SP) for stack instructions such as PUSH and POP.

In based addressing mode, the 20-bit physical stack address is calculated from
the Stack segment (SS) and the Base Pointer (BP).

46
 8086
Bus Interface Unit (BIU)
Microprocessor

Architecture
Segment Extra Segment Register
Registers
16-bit

Points to the extra segment in which data (in excess of 64K pointed to by the
DS) is stored.

String instructions use the ES and DI to determine the 20-bit physical address
for the destination.

47
 8086
Bus Interface Unit (BIU)
Microprocessor

Architecture
Segment Instruction Pointer
Registers
16-bit

Always points to the next instruction to be executed

within the currently executing code segment.

So, this register contains the 16-bit offset address

pointing to the next instruction code within the 64Kb of
the code segment area.

Its content is automatically incremented as the execution

of the next instruction takes place.

48
49
Physical address calculations

50
51
52
 8086
Bus Interface Unit (BIU)
Microprocessor

Architecture Instruction queue

A group of First-In-First-Out (FIFO)

in which up to 6 bytes of
instruction code are pre fetched
from the memory ahead of time.

This is done in order to speed up

the execution by overlapping
instruction fetch with execution.

This mechanism is known as

pipelining.

53
 8086
Execution Unit (EU)
Microprocessor

EU decodes and Architecture

executes instructions.

A decoder in the EU
control system
translates instructions.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 54
DX can be used as DH and DL
 Bus Interface Unit (BIU)

• Bus Interface Unit (BIU):

• The BIU sends out addresses, fetches
instructions from memory, reads data from
ports and memory, and writes data to ports
and memory.
• In simple words, the BIU handles all transfers
of data and addresses on the buses for the
execution unit.
 Functions of EU
 The execution unit of the 8086 tells the BIU where to
fetch instructions or data from, decodes instructions,
and executes instructions.
 The EU contains control circuitry, which directs internal
operations.
 A decoder in the EU translates instructions fetched from
memory into a series of actions, which the EU carries
out.
 The EU has a 16-bit arithmetic logic unit (ALU) which
can add, subtract, AND, OR, XOR, increment, decrement,
 complement or shift binary numbers.
 The main functions of EU are:

• Decoding of Instructions
• Execution of instructions
 Steps
• EU extracts instructions from top of queue in BIU
• Decode the instructions
• Generates operands if necessary
• Passes operands to BIU & requests it to perform read or
write bus cycles to memory or I/O
• Perform the operation specified by the instruction on
operands
 8086
Execution Unit (EU)
Microprocessor

Architecture
EU Accumulator Register (AX)
Registers
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.

AL in this case contains the low order byte of the word,

and AH contains the high-order byte.

The I/O instructions use the AX or AL for inputting /

outputting 16 or 8 bit data to or from an I/O port.

Multiplication and Division instructions also use the AX or

AL.

58
 8086
Execution Unit (EU)
Microprocessor

Architecture
EU Base Register (BX)
Registers
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.

BL in this case contains the low-order byte of the word,

and BH contains the high-order byte.

This is the only general purpose register whose contents

can be used for addressing the 8086 memory.

All memory references utilizing this register content for

addressing use DS as the default segment register.

59
 8086
Execution Unit (EU)
Microprocessor

Architecture
EU Counter Register (CX)
Registers
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.

When combined, CL register contains the low order byte

of the word, and CH contains the high-order byte.

Instructions such as SHIFT, ROTATE and LOOP use the

contents of CX as a counter.

Example:

The instruction LOOP START automatically decrements

CX by 1 without affecting flags and will check if [CX] =
0.

If it is zero, 8086 executes the next instruction;

otherwise the 8086 branches to the label START.

60
 8086
Execution Unit (EU)
Microprocessor

Architecture
EU Data Register (DX)
Registers
Consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX.

When combined, DL register contains the low order byte

of the word, and DH contains the high-order byte.

Used to hold the high 16-bit result (data) in 16 X 16

multiplication or the high 16-bit dividend (data) before a
32 16 division and the 16-bit reminder after division.

61
 8086
Execution Unit (EU)
Microprocessor

Architecture
EU Stack Pointer (SP) and Base Pointer (BP)
Registers
SP and BP are used to access data in the stack segment.

SP is used as an offset from the current SS during

execution of instructions that involve the stack segment
in the external memory.

SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH
instruction.

BP contains an offset address in the current SS, which is

used by instructions utilizing the based addressing mode.

62
 8086
Execution Unit (EU)
Microprocessor

Architecture
EU Source Index (SI) and Destination Index (DI)
Registers
Used in indexed addressing.

Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination
addresses.

63
 8086
Execution Unit (EU)
Microprocessor

Architecture
EU Source Index (SI) and Destination Index (DI)
Registers
Used in indexed addressing.

Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination
addresses.

64
 8086
Execution Unit (EU)
Microprocessor

Flag Register
Architecture Auxiliary Carry Flag

This is set, if there is a carry from the

Carry Flag

lowest nibble, i.e, bit three during This flag is set, when there is
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case of
subtraction. subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction

Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 65
 Register organization of 8086
Example – 1
• CF (carry flag) — carry out of 0011 0100 1101
MSB 1100
• PF (parity flag) — set to 1 if low-
order 8 bits (low order byte) +0000 0111 0010
contain even number of 1’s 1110
• AF (auxiliary carry flag) —carry 0011 1100 0000
out of bit 3 1010
• ZF (zero flag) — set to 1 if result
is 0; to 0 if result is nonzero CF = 0
• SF (sign flag) —MSB of result PF = 1
• OF (overflow flag) — set if carry AF = 1
in to MSB is not equal to carry
out from MSB) ZF = 0
SF = 0
8086
OF = 0 66
 Register organization of 8086
Example – 2
• CF (carry flag) — carry out of 1111 1111
MSB 1110 0101
• PF (parity flag) — set to 1 if low- +1111 1111 1011
order 8 bits (low order byte) 0001
contain even number of 1’s 1 1111 1111 1001
• AF (auxiliary carry flag) —carry 0110
out of bit 3 CF = 1
• ZF (zero flag) — set to 1 if result
is 0; to 0 if result is nonzero PF = 1
• SF (sign flag) —MSB of result AF = 0
• OF (overflow flag) — set if carry
in to MSB is not equal to carry ZF = 0
out from MSB) SF = 1
OF = 0
8086 67
 8086
Microprocessor Architecture

8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

into 4 groups OF DF IF TF SF ZF AF PF CF

Sl.No. Type Register width Name of register

1 General purpose register 16 bit AX, BX, CX, DX

8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

68
 8086
Microprocessor Architecture Registers and Special Functions

Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations

BX Base register Used to hold base value in base addressing mode to access memory
data

CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP instructions

DX Data Register Used to hold data for multiplication and division operations

SP Stack Pointer Used to hold the offset address of top stack memory

BP Base Pointer Used to hold the base value in base addressing using SS register to
access data from stack memory

SI Source Index Used to hold index value of source operand (data) for string
instructions

DI Data Index Used to hold the index value of destination operand (data) for string
operations
69
 Minimum Mode 8086 System

• In a minimum mode 8086 system, the microprocessor 8086 is

operated in minimum mode by strapping its MN/MX pin to
logic 1.
• In this mode, all the control signals are given out by the
microprocessor chip itself. There is a single microprocessor in
the minimum mode system.
• The remaining components in the system are latches,
transreceivers, clock generator, memory and I/O devices.
Some type of chip selection logic may be required for
selecting memory or I/O devices, depending upon the address
map of the system.
Block Diagram of Minimum Mode 8086 System
 Minimum Mode 8086 System Contd..

• Latches are generally buffered output D-type flip-flops like

74LS373 or 8282. They are used for separating the valid
address from the multiplexed address/data signals and are
controlled by the ALE signal generated by 8086.
• Transreceivers are the bidirectional buffers and some times
they are called as data amplifiers. They are required to
separate the valid data from the time multiplexed address/data
signals.
• They are controlled by two signals namely, DEN and DT/R.
 Minimum Mode 8086 System Contd..

• The DEN signal indicates the direction of data, i.e. from or

to the processor. The system contains memory for the
monitor and users program storage.
• Usually, EPROM are used for monitor storage, while
RAM for users program storage. A system may contain I/O
devices.
 Minimum Mode 8086 System Contd..

• The clock generator generates the clock from the crystal

oscillator and then shapes it and divides to make it more
precise so that it can be used as an accurate timing reference
for the system.
• The clock generator also synchronizes some external signal
with the system clock. The general system organization is as
shown in below fig.
• It has 20 address lines and 16 data lines, the 8086 CPU
requires three octal address latches and two octal data buffers
for the complete address and data separation.
 Minimum Mode 8086 System Contd..

• The working of the minimum mode configuration system can

be better described in terms of the timing diagrams rather than
qualitatively describing the operations.
• The opcode fetch and read cycles are similar. Hence the timing
diagram can be categorized in two parts, the first is the timing
diagram for read cycle and the second is the timing diagram
for write cycle.
• The read cycle begins in T1 with the assertion of address latch
enable (ALE) signal and also M / IO signal. During the
negative going edge of this signal, the valid address is latched
on the local bus.
 Minimum Mode 8086 System Contd..

• The BHE and A0 signals address low, high or both bytes.

From T1 to T4 , the M/IO signal indicates a memory or I/O
operation.
• At T2, the address is removed from the local bus and is sent to
the output. The bus is then tristated. The read (RD) control
signal is also activated in T2.
• The read (RD) signal causes the address device to enable its
data bus drivers. After RD goes low, the valid data is available
on the data bus.
• The addressed device will drive the READY line high. When
the processor returns the read signal to high level, the
addressed device will again tristate its bus drivers.
 Minimum Mode 8086 System Contd..

• A write cycle also begins with the assertion of ALE and

the emission of the address. The M/IO signal is again
asserted to indicate a memory or I/O operation. In T2, after
sending the address in T1, the processor sends the data to
be written to the addressed location.
• The data remains on the bus until middle of T4 state. The
WR becomes active at the beginning of T2 (unlike RD is
somewhat delayed in T2 to provide time for floating).
• The BHE and A0 signals are used to select the proper byte
or bytes of memory or I/O word to be read or write.
• The M/IO, RD and WR signals indicate the type of data
transfer as specified in table below.
Minimum Mode 8086 System Contd..
Read Cycle Timing Diagram for Minimum Mode
writeCycle Timing Diagram for Minimum Mode
 Minimum Mode 8086 System Contd..

• Hold Response sequence: The HOLD pin is checked at

leading edge of each clock pulse. If it is received active by the
processor before T4 of the previous cycle or during T1 state of
the current cycle, the CPU activates HLDA in the next clock
cycle and for succeeding bus cycles, the bus will be given to
another requesting master.
• The control of the bus is not regained by the processor until
the requesting master does not drop the HOLD pin low. When
the request is dropped by the requesting master, the HLDA is
dropped by the processor at the trailing edge of the next clock.
Bus Request and Bus Grant Timings in Minimum Mode
 Maximum Mode 8086 System

• In the maximum mode, the 8086 is operated by strapping the

MN/MX pin to ground.
• In this mode, the processor derives the status signal S2, S1,
S0. Another chip called bus controller derives the control
signal using this status information .
• In the maximum mode, there may be more than one
microprocessor in the system configuration.
• The components in the system are same as in the minimum
mode system.
 Maximum Mode 8086 System Contd..

• The basic function of the bus controller chip IC8288, is to

derive control signals like RD and WR ( for memory and I/O
devices), DEN, DT/R, ALE etc. using the information by the
processor on the status lines.
• The bus controller chip has input lines S2, S1, S0 and CLK.
These inputs to 8288 are driven by CPU.
• It derives the outputs ALE, DEN, DT/R, MRDC, MWTC,
AMWC, IORC, IOWC and AIOWC. The AEN, IOB and CEN
pins are specially useful for multiprocessor systems.
 Maximum Mode 8086 System Contd..

• AEN and IOB are generally grounded. CEN pin is usually tied
to +5V. The significance of the MCE/PDEN output depends
upon the status of the IOB pin.
• If IOB is grounded, it acts as master cascade enable to control
cascade 8259A, else it acts as peripheral data enable used in
the multiple bus configurations.
• INTA pin used to issue two interrupt acknowledge pulses to
the interrupt controller or to an interrupting device.
 Maximum Mode 8086 System Contd..

• IORC, IOWC are I/O read command and I/O write command
signals respectively . These signals enable an IO interface to
read or write the data from or to the address port.
• The MRDC, MWTC are memory read command and memory
write command signals respectively and may be used as
memory read or write signals.
• All these command signals instructs the memory to accept or
send data from or to the bus.
• For both of these write command signals, the advanced signals
namely AIOWC and AMWTC are available.
 Maximum Mode 8086 System Contd..

• They also serve the same purpose, but are activated one clock
cycle earlier than the IOWC and MWTC signals respectively.
• The maximum mode system timing diagrams are divided in
two portions as read (input) and write (output) timing
diagrams.
• The address/data and address/status timings are similar to the
minimum mode.
• ALE is asserted in T1, just like minimum mode. The only
difference lies in the status signal used and the available
control and advanced command signals.
Block Diagram of Maximum Mode 8086 System
 Maximum Mode 8086 System Contd..

• Here the only difference between in timing diagram between

minimum mode and maximum mode is the status signals used
and the available control and advanced command signals.
• R0, S1, S2 are set at the beginning of bus cycle.8288 bus
controller will output a pulse as on the ALE and apply a
required signal to its DT / R pin during T1.
 Maximum Mode 8086 System Contd..

• In T2, 8288 will set DEN=1 thus enabling transceivers, and for
an input it will activate MRDC or IORC. These signals are
activated until T4. For an output, the AMWC or AIOWC is
activated from T2 to T4 and MWTC or IOWC is activated
from T3 to T4.
• The status bit S0 to S2 remains active until T3 and become
passive during T3 and T4.
• If reader input is not activated before T3, wait state will be
inserted between T3 and T4.
 Maximum Mode 8086 System Contd..

• Timings for RQ/ GT Signals :The request/grant response

sequence contains a series of three pulses. The request/grant
pins are checked at each rising pulse of clock input.
• When a request is detected and if the condition for HOLD
request are satisfied, the processor issues a grant pulse over
the RQ/GT pin immediately during T4 (current) or T1 (next)
state.
• When the requesting master receives this pulse, it accepts the
control of the bus, it sends a release pulse to the processor
using RQ/GT pin.
Memory Read Timing in Maximum Mode of 8086
Memory Write Timing in Maximum Mode of 8086
RQ / GT Timings in Maximum Mode
Basic Timing Diagram in 8086