MIT-WPU

School of Electronics and Communication Engineering

S.Y. B. Tech (SEM- IV)
Microcontroller and Applications
ECE2003B
 Unit- II : CIP-51 Architecture

• Reset sources
• Oscillator options
• Port structure
• Timers
• Timer programming
• Interrupt handler
• Power management modes
Timers in C8051F340 Microcontroller
 Timers
• Timers are used for: interval timing(delays), event counting(counter) or baud rate generation.
Software delay: The dummy method to produce delay is by using No Operation (NOP) in loop & repeat it ex. 100 times called software
delay.
• Processor is busy in execution of it.

Hardware delay: If you engage/use a timer to produce delay.

• Processor gives command to the timer to give delay or count, after it counts - inform processor, during this period processor is free
to do other work.

1) Interval timing applications: In this a timer is programmed to overflow at a regular interval and the following:
• Set the timer overflow flag or
• Generate an interrupt
• This can also be used to generate waveforms at set frequencies
2) Event counting: It is used to determine the number of occurrences of an event, rather than to measure the elapsed time between
events.
• In this case, the timer functions as a counter.
• An “event” is any external stimulus that provides a high-to-low transition at the selected input pin
• The timers can also function as the baud rate generators for the C8051F340’s internal serial ports (UART0 and UART1)
• “Baud rate” is the bit rate of the serial port (the time period of a bit).
• The baud rate is the rate at which information is transferred in a communication channel.
• Baud rate is commonly used in electronics that use serial communication.
• In the serial port context, "9600 baud" means that the serial port is capable of transferring a maximum of 9600 bits per second.
 Difference between Timer and Counter
Counter: Uses External Clock
Timer: Uses Internal Oscillator Clock
T0 T1

T0 T1
T2 T3

T2 T3
Fosc

Timer and counter both uses the clock.

• Timer & Counter are not same but almost same.
• Both have same formula & procedure. But depending upon programmer intension ie
weather used for delay that means timer or for counting that means counter.
Ex: At railway station:
1) Stand for 1 hr and count how many trains are passing in 1hr ________
2) Stand at station & count how much time the 100 trains are taking to pass_________
In both cases same work.

Timer: If we know the frequency of the clock which is fixed, then before counter finishes we
find the time in which it can count ie you are working as a timer . (Internal clk freq is fixed)
So, If the freq is fixed-------- it is a timer.

Counter: For variable freq (you are counting at different speed) then we don’t know when it
will finish. Then you are working as a counter.
So, If the freq is variable------- it is a Counter.
MCU includes four counter/timers:
• Total 4 timers in CIP-51.
• Two are 16-bit counter/timers compatible with those found in the
standard 8051, and
• Two are 16-bit auto-reload timer for use with the ADC, SMBus, USB
(frame measurements), Low-Frequency Oscillator (period
measurements), or for general purpose use.
• These timers can be used to measure time intervals, count external
events and generate periodic interrupt requests.
• Timer 0 and Timer 1 are nearly identical and have four primary modes
of operation.
• Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality
with auto-reload.
 Timers
• Software delay : Using NOP in a loop to produce a delay.
• Hardware delay: Using hardware/timers to produce a delay.

• CIP51 has four counter/timers: Timer 0, Timer 1,

Timer 2 and Timer 3
• Timer 0 and Timer 1 are nearly identical and have four primary modes of operation.
• Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload.
Timer/ Counter Registers
Description Register Function
Name
Timer Control Register TCON Enables and disables Timer0 and Timer1, Also has overflow flag and
interrupt related bits
Timer Mode Register TMOD Selects the timer or counter operation with C/T0 and C/T1 bits, Also
has mode selection for timer0 and timer1
Clock Control CKCON Controls clock supplied to timer0 and timer 1 if configured to use
prescaled clock inputs, or system clock
Timer 0 low byte TL0 Lower byte of timer0
Timer 0 high byte TH0 Higher byte of timer0

Timer 1 low byte TL1 Lower byte of timer1

Timer 1 high byte TH1 Higher byte of timer1

Timer 2 low byte TMR2L
Timer 2 High byte TMR2H
 SFR: TL0 & TH0

TL1: Timer1 low byte

register

Timer 0 and Timer 1 may also be operated as counters.

When functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin (T0 or T1).
SFR TCON: Timer Control: (8-bit register): used to ctrl timer Lower 4 byte : Interrupt
Higher 4 byte : Timer

Bit addressable
means u can use
these bits
individually.

When the interrupt is recognized on level trigger, it is Level triggered.

When the interrupt is recognized on edge trigger, it is Level triggered.

SFR TCON: Timer Control…..

As these timers are controlled or make 1 & 0 using instruction, it is

called software controlled & not software delay.
Both timers work independently.
Q: The programmer has loaded the value 69H in TCON, explain what is happened?

Ans: Draw the TCON dig, Explain about Timer 0 , Timer 1 and Interrupt 0 & Interrupt 1

0 1 1 0 1 0 0 1
SFR Definition 21.3. CKCON: Clock Control
SFR Definition 21.3. CKCON: Clock Control
TMOD : Timer mode register :
It has 4 modes, 8-bit, 4-bits for Timer 0 & 4-bits for Timer 1 (They are identical bits)
SFR TMOD: Timer Mode

Gate : Enables hardware control and

if gate = 1: counting controlled by INTX (external interrupt ie hardware button will used) ,
Gate = 0, counting controlled by independent od INTX

T0=00: Timer 0 Mode 0

T0=01: Timer 0 Mode 1
T0=10: Timer 0 Mode 2

T0= 11: Timer 0 Mode 3

SFR TMOD: Timer Mode

T1=00: Timer 1 Mode 0

T1=01: Timer 1 Mode 1
T1=10: Timer 1 Mode 2

T1= 11: Timer 1 Mode 3

 Q: If The programmer has to read the value D0H in TMOD, explain what will happen?

Ans: Draw the TMOD dig, Explain

1 1 0 1 0 0 0 0

• TCON & TMOD are summarized in one Logic Diagram (Timer/Counter Logic Diagram):
 Timer 0 & 1: Mode 0 (M0) : 13 bit Timer / Counter
(5-Bit) (8-Bit)
CLK

From i/p stage

TLX THX TFX INT

TLX: Timer 0 or Timer 1 Lower byte (LB)

THX: Timer 0 or Timer 1 Higher byte (HB)
TFX: Timer 0 or Timer 1 overflow flag
Note: Lower byte is written first then lower byte because we increase the lower byte for increment then HB.
Ex: H L
H L
As LB = 5 bits, it overflows after 25 = 32 pulses ie 00 to 31&
3 7
we get 1 pulse towards THX, again after 32 pulses next 1
3 8 more THX……
3 9
Therefore T0 mode is used to divide the
4 0 frequency by 32 .

As LB=5 & HB=8, the max count is 213 = 23 X210 = 8K = 1FFF

Note: For exam only Mode1 & Mode 2 only

 Timer 0 & 1: Mode 1 (M1) : 16 bit Timer / Counter

(8-Bit) (8-Bit)
CLK

From i/p stage

TLX THX TFX INT

• Same procedure like Mode 0 .

• As LB=8 & HB=8, the max count is 216 = 26 X210 = 64K = FFFF

Therefore T1 mode is used to produce the biggest delay and most preferred.
 Timer 0 & 1 Mode 1: 16bit Counter/Timer
• Mode 1 configures Timer 0 and Timer 1 to operate as 16-bit
counter/timers.
• TH0 and TL0 holds the count.
• When the count in TH0 and TL0 overflows from all ones to 0x00, the
timer overflow flag is set.
• If Timer 0 interrupts are enabled, an interrupt will occur when the TF0
flag is set.
• The count in TH0 and TL0 should be loaded for next iteration.
 T0 Mode 1 Block Diagram

Note: The diagram & explanation for T0 Mode 0 & Mode 1 are same, only Mode 0 is 13 bit and Mode 1 is 16 bit register
Mode 1 : 16 bit Counter / Timer
 Timer 0 & 1 Mode 2 (M2) : 8 bit Timer / Counter with “Auto-Reload”
(8-Bit)
CLK

From i/p stage

TLX TFX INT

THX
(8-Bit)

• This mode automatically reload the counter (with the original count & not the random count) after completing
previous count without intervention of programmer.
• The system has to keep the backup of count. So system has 2 count, 1 for counting & 1 for reloading. (8-bit)
• This is continuous mode and all other are single mode ie when they finish counting, they stop after overflow.

• Mode 2 is used for creating repetitive delay.

Timer 0 & 1 Mode 2: 8bit Counter/Timer with Auto-Reload
• Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with
automatic reload of the start value.
• TL0 holds the count and TH0 holds the reload value.
• When the counter in TL0 overflows from all ones to 0x00, the timer overflow flag
TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0.
• If Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set.
The reload value in TH0 is not changed.
• TL0 must be initialized to the desired value before enabling the timer for the first
count to be correct.
• When in Mode 2, Timer 1 operates identically to Timer 0.
• Both counter/timers are enabled and configured in Mode 2 in the same manner as
Mode 0.
• Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is
logic 0 or when the input signal INT0 is active as defined by bit IN0PL in register
T0 Mode 2 Block Diagram
 Timer 0 & 1 Mode 3 (M2) : Two , 8 bit Timer / Counter using T0

(8-Bit)
CLK
• T0 is divided into 2 independent timers of 8-bit,
From i/p stage
TL0 TF0 INT
TL0 & TH0,
• so total 3 timers T1, TL0 & TL0 .
(8-Bit)
Fosc÷12 • T1 is used in serial bit communication where
TH0 TF1 INT the data bit will be sent bit by bit & don’t
require the timer overflow flag TF1.

• We get 2 delay simultaneously, 1 T1- serial

communication & Processor is free for other
work.

• Note: TH0 is using Fosc/12, & is used as a

timer only & not counter.

• All other modes, T1 is used as a counter as well

as timer.

Note: Mode0 & Mode 3 is only for reference

Configure TMOD register for the following:

• Timer 1 in mode 1
• Timer 1 in mode 2
• Timer 0 in mode 1
• Timer 0 in mode 2
• Timer 1 in mode 2 and Timer 0 in mode 1
 Solution:

• Timer 1 in mode 1 : TMOD = 00010000 = 0x10

• Timer 1 in mode 2 : TMOD = 00100000 = 0x20
• Timer 0 in mode 1 : TMOD = 00000001 = 0x01
• Timer 0 in mode 2 : TMOD = 00000010 = 0x02
• Timer 1 in mode 2 and Timer 0 in mode 1 : TMOD = 00100001 = 0x21
Configure TMOD register for the following:
• Timer 1 in mode 1 - 10H
Gate1 C/T1 T1M1 T1M0 Gate0 C/T0 T0M1 T0M0

0 0 0 1 0 0 0 0

• Timer 1 in mode 2 – 20H

Gate1 C/T1 T1M1 T1M0 Gate0 C/T0 T0M1 T0M0

0 0 1 0 0 0 0 0

• Timer 0 in mode 1 – 01H

• Timer 0 in mode 2 – 02H
• Timer 1 in mode 2 and Timer 0 in mode 1 – 21H
Gate1 C/T1 T1M1 T1M0 Gate0 C/T0 T0M1 T0M0

0 0 1 0 0 0 0 1
 Time Delay Calculations – For Mode 1(16-bit)
Procedure for Time to Count Calculation – For Mode 1

The delay length depends on 3 factors:

1) The crystal freq 2) The no. of clocks per machine cycles 3) The compiler
The original 8051 used 1/12 of crystal oscillator freq as one machine cycle.
In other words, each machine cycle is equal to 12 clocks periods of the crystal freq connected to X1-X2 pins.

Time period of 1clock cycle = (1/System Clock)

Count = (Required delay/Time period of 1clock cycle)

Before loading
count, we have to
Value to be loaded in timer register, calculate the the
Value (in decimal)= 65536 - Count …..As it is 16 bit count bcaz it is
upcounter & not
downcouter.
Convert Value from decimal to hex (YYXX)

Load YY in THx, and XX in TLx register

Note: Assume SystemClock = 12MHz

Example for Time to
Count Calculation
Mode 1

Delay Required=
3mSec
Delay Required= 2mSec

1. System Clock =12 MHz

2.Time period of 1clock cycle = (1/System Clock)=1/12MHz=83.3 ηSec

3. Count = (Required delay/Time period of 1clock cycle)

Count = (2mSec/ 83.3 ηSec)= 24010

4. Value to be loaded in timer register,

Value (in decimal)= 65536-Count
Value (in decimal)= 65536- 24010 =41526
5. Convert Value from decimal to hex (YYXX) A236

6. Load YY in THx and XX TLx register

FIND THE VALUE TO BE LOADED INTO TIMER REGISTER IF REQUIRED
DELAY IS 4mSec (TIMER0 AND MODE 1)

ANS:
COUNT=(17517)d
= (446D)hex
TH0=44h TL0=6Dh
 Time Delay Calculations – For Mode 2(8-bit)
Procedure for Time to Count Calculation– For Mode 2

Time period of 1clock cycle = (1/SystemClock)

Count = (Required delay/Time period of 1 clock cycle)

Value to be loaded in timer register,

Value (in decimal)= 256-Count …..As it is 8 bit

Convert Value from decimal to hex (XX)

Load XX in THx register

Note: Assume SystemClock = 12MHz

Example for Time
20u
to Count
Calculation - Mode
2 20u

Delay Required=
20usec
Procedure for Count to Time Calculation – For Mode 1
Example for Count to time calculation – For Mode 1
Procedure for Count to Time Calculation – For Mode 2
Example for Count to time calculation – For Mode 2
 Steps to program in mode 1

1. Load the TMOD value to timer mode

2. Load the CKCON value to select the clock
3. Load registers TLx and THx
4. Start the timer (SETB TRx)
5. Keep monitoring the timer flag (TFx)
6. Stop the timer (CLR TR0 or CLR TR1)
7. Clear the TF flag
8. Go back to step 3
 Steps to program 8-Bit Auto-Reload Mode (Mode 2)

• Load the TMOD value to timer mode

• 2. Load the CKCON value to select the clock
• 3. Load the count in register THx
• 4. Start the timer (SETB TRx)
• 5. Keep monitoring the timer flag (TFx)
• 6. Stop the timer (CLR TR0 or CLR TR1)
• 7. Clear the TF flag
• 8. Go back to step 4
Timer Programs
 SFR- CKCON: Clock Control

SFR TMOD: Timer Mode

Write an embedded C program to flash the LED connected to Port P4 continuously at an interval of 3mSec. Use Timer 0 in Mode 1 for generating the delay.

Mode 1 : 3msec
Write an embedded C program to flash the LED connected to Port P4 continuously at an interval of 3mSec. Use Timer 0 in Mode 1 for generating the delay.

#include “c8051F340.h” void Delay()

void Delay(); {
TH0 = 0x73; //Load High Byte of Count in TH0
int main()
TL0 = 0x52; //Load Low Byte of Count in TL0
{
TR0 = 1; //Start the Timer
P4MDOUT = 0xFF; // Configure Port4 as output
while (TF0 ==0 )
TMOD = 0x01; // Select Timer 0 in Mode 1 {
CKCON = 0x04; // Select System Clock for Timer 0 ---------------------
while (1) } ; //Wait for overflow
{ TF0 = 0; //Clear overflow flag
P4 = ~P4; // Compliment Port4 for flashing TR0 = 0; //Stop the Timer

Delay(); // Delay of 3ms between ON and OFF }

status of LED
}
return 0;
}
Write an embedded C program to flash the LED connected to Port P4 continuously at an interval of 20usec Use Timer 1 in Mode 2 for generating the delay.

20u

20
u

Mode 2 : 2ousec
Write an embedded C program to flash the LED connected to Port P4 continuously at an interval of 20usec Use Timer 1 in Mode 2 for generating the delay.

#include “c8051F340.h” void Delay()

void Delay(); {

int main() TR1 = 1; //Start the Timer

{ while (TF1 ==0 )

P4MDOUT = 0xFF; // Configure Port4 as output {

TMOD = 0x20; // Select Timer 1 in Mode 2

CKCON = 0x08; // Select System Clock for Timer 1
}
TH1 = 0x10; //Load High Byte of Count in TH1
; //Wait for overflow
while (1)
TF1 = 0; //Clear overflow flag
{
TR1 = 0; //Stop the Timer
P4 = ~P4; // Compliment Port4 for flashing
}
Delay(); // Delay of 20us between ON and OFF
status of LED
}
return 0;
}
Delay Required= 1mSec

1. System Clock =12 MHz

2.Time period of 1clock cycle = (1/System Clock)=1/12MHz=83.3ηSec

3. Count = (Required delay/Time period of 1clock cycle)

Count = (1mSec/ 83.3 ηSec)= 12005

4. Value to be loaded in timer register,

Value (in decimal)= 65536-Count
Value (in decimal)= 6553-12005=53531
5. Convert Value from decimal to hex (YYXX) D11B

6. Load YY in THx and XX TLx register

Delay Required= 2mSec

1. System Clock =12 MHz

2.Time period of 1clock cycle = (1/System Clock)=1/12MHz=83.3 ηSec

3. Count = (Required delay/Time period of 1clock cycle)

Count = (2mSec/ 83.3 ηSec)= 24010

4. Value to be loaded in timer register,

Value (in decimal)= 65536-Count
Value (in decimal)= 6553- 24010 =41526
5. Convert Value from decimal to hex (YYXX) A236

6. Load YY in THx and XX TLx register

Delay Required= 2.5mSec
1. System Clock =12 MHz
2.Time period of 1clock cycle = (1/System Clock)=1/12MHz=83.3 ηSec

3. Count = (Required delay/Time period of 1clock cycle)

Count = (2.5mSec/ 83.3 ηSec)=--------

4. Value to be loaded in timer register,

Value (in decimal)= 65536-Count
Value (in decimal)= 6553- ---------= ------------
5. Convert Value from decimal to hex (YYXX) 8AC4

6. Load YY in THx and XX TLx register

Delay Required= 5μSec
1. System Clock =12 MHz
2.Time period of 1clock cycle = (1/System Clock)=1/12MHz=83.3 ηSec

3. Count = (Required delay/Time period of 1clock cycle)

Count = (5μSec / 83.3 ηSec)= 60.02=60

4. Value to be loaded in timer register,

Value (in decimal)= 256-Count
Value (in decimal)= 256- 60-= 196
5. Convert Value from decimal to hex (XX) C4

6. Load XX in THx register

Delay Required= 2.5μSec
1. System Clock =12 MHz
2.Time period of 1clock cycle = (1/System Clock)=1/12MHz=83.3 ηSec

3. Count = (Required delay/Time period of 1clock cycle)

Count = (2.5μSec / 83.3 ηSec)= 30

4. Value to be loaded in timer register,

Value (in decimal)= 256-Count
Value (in decimal)= 256- 30-=226
5. Convert Value from decimal to hex (XX) E2
6. Load XX in THx register
Delay Required= 20μSec
1. System Clock =12 MHz
2.Time period of 1clock cycle = (1/System Clock)=1/12MHz=83.3 ηSec

3. Count = (Required delay/Time period of 1clock cycle)

Count = (20μSec / 83.3 ηSec)= 240

4. Value to be loaded in timer register,

Value (in decimal)= 256-Count
Value (in decimal)= 256- 240=16
5. Convert Value from decimal to hex (XX) 10
6. Load XX in THx register
Delay Required= 3μSec
1. System Clock =12 MHz
2.Time period of 1clock cycle = (1/System Clock)=1/12MHz=83.3 ηSec

3. Count = (Required delay/Time period of 1clock cycle)

Count = (3μSec / 83.3 ηSec)=-----

4. Value to be loaded in timer register,

Value (in decimal)= 256-Count
Value (in decimal)= 256- -----=-------
5. Convert Value from decimal to hex (XX) ------
6. Load XX in THx register
Interrupt Structure of C8051F340
 Interrupt in Embedded System
• An interrupt is a signal to the processor emitted by hardware or software
indicating an event that needs immediate attention.

• Whenever an interrupt occurs, the controller completes the execution of the

current instruction and starts the execution of an Interrupt Service
Routine (ISR) or Interrupt Handler.

• ISR tells the processor or controller what to do when the interrupt occurs. The
interrupts can be either hardware interrupts or software interrupts.
 Hardware Interrupt and Software Interrupt
• Hardware Interrupt
A hardware interrupt is an electronic alerting signal sent to the processor from an external device, like a
disk controller or an external peripheral.
For example, when we press a key on the keyboard or move the mouse, they trigger hardware
interrupts which cause the processor to read the keystroke or mouse position.

• Software Interrupt
A software interrupt is caused either by an exceptional condition or a special instruction in the
instruction set which causes an interrupt when it is executed by the processor.
For example, if the processor's arithmetic logic unit runs a command to divide a number by zero, to
cause a divide-by-zero exception, thus causing the computer to abandon the calculation or display an
error message.
Software interrupt instructions work similar to subroutine calls.
 Introduction to Interrupts
• An interrupt is the occurrence of a condition that causes a temporary suspension
of a program while the condition is serviced by another (sub) program

• Interrupts are important because they allow a system to respond asynchronously

to an event and deal with the event while in the middle of performing another
task

• An interrupt driven system gives the illusion of doing many things

simultaneously

• The (sub) program that deals with an interrupt is called an interrupt service
routine (ISR) or interrupt handler
 Interrupts
• An interrupt is an external or internal event that interrupts the
microcontroller to inform it that a device needs its service.
Interrupts vs. Polling
• A single microcontroller can serve several devices.
• There are two ways to do that:
• interrupts
• polling.
• The program which is associated with the interrupt is called the interrupt
service routine (ISR) or interrupt handler.
 Interrupts
• When an interrupt occurs, the main program temporarily suspends execution and branches
to the ISR

• The ISR executes, performs the desired operation, and terminates with a “return from
interrupt” (RETI) instruction

• The RETI instruction is different from the normal “RET” instruction

• Finishes the current instruction and saves the contents of PC on stack.

• Jumps to a fixed location in memory depending on the type of an interrupt.

• Starts to execute the interrupt service routine until RETI (return from interrupt).

• Upon executing the RETI the microcontroller returns to the place where it was interrupted.
Get pop PC from stack
 What is Polling?
• The state of continuous monitoring is known as polling.
• The microcontroller keeps checking the status of other devices;
and while doing so, it does no other operation and consumes all its
processing time for monitoring.
• This problem can be addressed by using interrupts.
• In the interrupt method, the controller responds only when an
interruption occurs.
• Thus, the controller is not required to regularly monitor the status
(flags, signals etc.) of interfaced and inbuilt devices.
 Interrupt Service Routine
For every interrupt, there must be an interrupt service routine (ISR),
or interrupt handler.
When an interrupt occurs, the microcontroller runs the interrupt
service routine.
For every interrupt, there is a fixed location in memory that holds
the address of its interrupt service routine, ISR.
The table of memory locations set aside to hold the addresses of
ISRs is called as the Interrupt Vector Table.
Comparison of Polling and Interrupt Method
Execution Flow
 Interrupt handler
• Interrupt handler provides 16 interrupt sources into the CIP-51 (as opposed to 7 for
the standard 8051), allowing numerous analog and digital peripherals to interrupt
the controller.

• An interrupt driven system requires less intervention by the MCU, giving it more
effective throughput.

• Each interrupt source can be individually enabled or disabled through the use of an
associated interrupt enable bit in an SFR (IE-EIE2).

• However, interrupts must first be globally enabled by setting the EA bit (IE.7) to
logic 1 before the individual interrupt enables are recognized.
• Setting the EA bit to logic 0 disables all interrupt sources regardless of the
individual interrupt-enable settings.
Interrupt Summary
Interrupt
Summary
 Interrupt Registers
Sr. No Name of Register Function

1.
IE(Interrupt Enable) Enables and Disables interrupts for entire system and also enables interrupts from
SPI, Timer 2, UART0, Timer 1, Timer 0 and external interrupt 1 and 2
2.
IP (Interrupt Priority) Sets the priorities of enabled interrupts in IE register

3. …

Enabling and Disabling an Interrupt

• Upon Reset, all the interrupts are disabled even if they are activated.
• The interrupts must be enabled using software in order for the microcontroller to
respond to those interrupts.

• IE (interrupt enable) register is responsible for enabling and disabling the interrupt.
• IE is a bit addressable register.
IE: Interrupt Enable
IE: Interrupt Enable
IP: Interrupt Priority
IP: Interrupt Priority
 Power Management Modes

Power Management Modes

• The CIP-51 core has two software programmable power

management modes:

1. Idle

2. Stop.
 Power Control Register (PCON)

Power Control Register (PCON) is used to control the CIP-51's

power management modes.
• SFR Definition PCON: Power Control
Idle mode
• Idle mode-
• Halts the CPU
• internal registers and memory maintain their original data
• Peripherals and clocks active.
• Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU
and enter Idle.
• Idle mode is terminated when an enabled interrupt is asserted or a reset occurs.
• The assertion of an enabled interrupt will cause the Idle Mode Selection bit
(PCON.0) to be cleared and the CPU to resume operation.
• If enabled, the Watchdog Timer (WDT) will eventually cause an internal
watchdog reset and thereby terminate the Idle mode.
 Stop mode

• Stop mode-
• CPU is halted
• All interrupts inactive
• Internal oscillator is stopped
• All digital & analog peripherals stopped
• External oscillator circuit is not affected
• Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as
the instruction that sets the bit completes execution.
• Stop mode can only be terminated by an internal or external reset.
• If enabled, the Missing Clock Detector will cause an internal reset and there by terminate the
Stop mode.
• The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for
longer than the MCD timeout of 100 μsec
Reference

Datasheet:
https://www.silabs.com/documents/public/datasheets/C8051F34x.pdf