Digital Systems II

STM32L4

1
Analog-to-Digital Converter (ADC)

VREF

ADC

clock

Analog signal x(t) Digital values x(n)

• Resolution
continuous time • Quantization error discrete time
continuous amplitude • Sampling rate discrete amplitude

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ADC: Resolution
 Resolution: number of binary bits in ADC output.
VREF

Vinput ADC
𝐴𝐷𝐶𝑂𝑢𝑡𝑝𝑢𝑡=𝑟𝑜𝑢𝑛𝑑¿
clock • N: resolution
• VREF: the maximum input voltage that
can be converted by the ADC

Example: for 10-bit ADC, Vinput = 1V, VREF = 5V

𝐴𝐷𝐶 𝑂𝑢𝑡𝑝𝑢𝑡=𝑟𝑜𝑢𝑛𝑑 1 023 ×( 1

5 )
=𝑟𝑜𝑢𝑛𝑑 ( 204 .6 )=205=0 𝑥𝐶𝐷

3
ADC: Quantization Error
 Resolution N: number of binary bits in ADC output.

𝐷𝑖𝑔𝑖𝑡𝑎𝑙𝑅𝑒𝑠𝑢𝑙𝑡=𝑟𝑜𝑢𝑛𝑑¿
Example: Resolution = 3 bits
Least significant bit (LSB) voltage

Max quantization error = ±½ LSB

1 LSB Example: 3-bit ADC and input range [0, 5V]

½ LSB

4
Example of Quantization Error

½ LSB

- ½ LSB

LSB

Marek Gasior, Analog digital conversion, CERN Beam Instrumentation Group, BI CAS 2018,
Tusula, Finland
5
ADC: Sampling rate
 Number of ADC output samples available per unit time.

6
What sampling rate do we need?
Nyquist–Shannon Sampling Theorem

7
http://195.134.76.37/applets/AppletNyquist/Appl_Nyquist2.html
ADC Architecture
Popular ADC Architectures:
 Successive-approximation (SAR)
 Sigma-delta (Σ-Δ),
 Pipeline

8 https://www.analog.com/en/analog-dialogue/articles/the-right-adc-architecture.html
Successive-approximation (SAR)

9
Determining Minimum Sampling Time

½ LSB
R
VIN VC

sampling time

 Sampling time is software programmable

 Sampling time must large enough to settle within ½ LSB
10
Programming ADC Sampling Time

2.5 cycles
6.5 cycles
HSI Clock ADC Clock
Prescaler 12.5 cycles

Selection
16 MHz /1, /2, /4
24.5 cycles
default prescaler = 1 47.5 cycles
92.5 cycles
247.5 cycles
640.5 cycles

ADC sample time registers

(SMPR1 and SMPR2)

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Successive-approximation (SAR) ADC

• Binary search algorithm

to gradually approaches
the input voltage
• Settle into ±½ LSB
bound within the time
allowed

12 N cycles for N-bit ADC

ADC Conversion Time

𝑇 𝐴𝐷𝐶 =𝑇 𝑠𝑎𝑚𝑝𝑙𝑖𝑛𝑔 +𝑇 𝐶𝑜𝑛𝑣𝑒𝑟𝑠𝑖𝑜𝑛

Suppose ADC clock = 16 MHz, and Sampling time = 4 cycles

For 12-bit ADC

𝑇 𝐴𝐷𝐶 =4 +12=16 𝑐𝑦𝑐𝑙𝑒𝑠=1𝜇 𝑠

For 6-bit ADC

𝑇 𝐴𝐷𝐶 =4 +6=10 𝑐𝑦𝑐𝑙𝑒𝑠=0 . 625 𝜇 𝑠

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ADC: Regular vs injected

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ADC
 STM32L4 has three ADC modules, named ADC1, ADC2, and ADC3.

 Software can set ADC1 and ADC2 to the dual mode, in which both
ADC modules perform conversion simultaneously (ADC1 master).

 Each ADC consists of a 12-bit successive approximation analog-to-

digital converter.

 The resolution can be 12, 10, 8 or 6 bits, depending on the

application's need. By using a technique called oversampling, the
resolution can increase to 16 bits.

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ADC Registers

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ADC Registers

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ADC Registers

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ADC Registers

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ADC Registers

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ADC Registers

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ADC Registers

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ADC Registers

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ADC Registers

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ADC: Regular vs injected
 Each ADC has up to 20 multiplexed channels. A/D conversion of the
various channels can be performed in single, continuous, scan or
discontinuous mode. The result of the ADC is stored in a left-aligned
or right-aligned 16-bit data register.
 ADC1 is connected to 16 external channels + 3 internal channels
 ADC2 is connected to 16 external channels + 2 internal channels
 ADC3 is connected to 12 external channels + 4 internal channels
 Some ADC input channels are connected to internal signals, such as
internal temperature sensor, and battery monitor voltage.

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ADC: Regular vs injected
 Pin definition for analog input signal of STM32L4 processors

 A GPIO pin can only be connected to a pre-defined input channel of an ADC module.
 For example, Pin PC 0 can be internally connected to the input channel 1 of all ADC
modules (ADC123_IN 1), including ADC1, ADC2, and ADC3.
 Pin PA 1 can be internally connected to the input channel 6 of ADC1 and ADC2
(ADC12_IN 6).
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ADC:
 The program in Example 20-1connects pin PA.1 to the
channel 6 of ADC1 and ADC2.
 The GPIO mode bits must be set to select the analog
mode, which is the default GPIO mode when the
processor is reset.
 In this example, pin PA.1 is configured as no pull-up and
no pull-down internally. The pin will be floating, and the
ADC result is random if the pin is temporarily not driven.
Depending on the application's need, selecting pull-up or
pull-down (either internally or externally) may be a better
option to prevent the pin from floating.
 In addition, software sets a bit in the ASCR register to
connect the corresponding pin and ADC.
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ADC:

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ADC: Regular vs injected
 Input channels of an ADC module care divided into two
groups: injected group and regular group.
 A program can select up to four input channels to join
the injected group. A channel in the injected group is
referred to as an injected channel. Each injected channel
has its own ADC data register.
 Software can also put input channels into a regular
group. An input channel in the regular group is called a
regular channel. All regular channels share an ADC data
register.

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 ADC:
 The voltage input range of each channel is in [Vref-, Vref+],
where the Vref- and Vref+ are two dedicated input pins on
some processors and serve as external voltage references.

 Most processors also provide an internal reference voltage,

which is measured individually at the manufacturing stage.

 For example, the internal reference voltage of STM32L is

3±0.01 V, and its corresponding converted value is stored in
a protected memory area during the manufacturing
process.

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ADC:
 Each channel can be single-ended input or differential input by
configuring register DIFSEL.
 In single-ended input mode, the analog voltage to be
converted for channel “i” is the difference between the external
voltage ADC_INP[i] and VREF− .
 In the differential mode, the ADC input is the difference
between two external voltage inputs:
 ADC_INP[i] and ADC_INN[i] or ADC_INP[i+1]

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ADC:
 When configuring the channel “i” in differential input mode, its
negative input voltage ADC_INN[i] is connected to
ADC_INP[i+1].
 As a consequence, channel “i+1” is no longer usable in single-
ended mode or in differential mode and must never be
configured to be converted.

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ADC:
 ADC_INN[i] is connected
to ADC_INP[i+1].

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ADC Conversion Modes
 The ADC module performs conversions on selected conversion
channels in either the single conversion mode or the continuous
conversion mode, as shown in Figure.

Single Channel Mode Scan Mode

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 ADC Conversion Modes
 One Input Channel
 For a channel in the regular group, the target channel is determined
by the SQi[4:0] bits in the ADC_SQRi register (i=1 to 4). The 16-bit
ADC data register (ADC_DR) holds the conversion result. After the
conversion, the end of regular conversion flag (EOC) is set in the
ADC_ISR register. The ADC module generates an interrupt request
if the EOCIE bit is set in the interrupt enable register (ADC_IER).

 For a channel in the injected group, the JSQi[4:0] bits in the

ADC_JSQR register selects the conversion channel. The 16-bit
register ADC_JDRy (y=1 to 4) holds the conversion result. After the
conversion, the end of injected conversion flag (JEOC) is set in the
ADC_ISR register. An ADC interrupt will be generated if the JEOCIE
bit is set in the interrupt enable register (ADC_IER).

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ADC Conversion Modes
 One Input Channel
 If the continuous conversion mode is used on one input
channel, the ADC module automatically starts a new
conversion immediately after it finishes one.
 The last conversion result is saved in the ADC_DR register
for a regular channel and register ADC_JDRy (y=1 to 4)) for
an injected channel.
 The CONT bit in the ADC_CFGR register enables the
continuous mode.

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ADC Conversion Modes
 Multiple Input Channels
 The ADC module can perform sampling and conversions on
a set of pre-defined input channels in a round-robin fashion.
This conversion scheme is called scan mode.

 For a regular group, this mode scans all channels defined in

registers ADC_SQR1, ADC_SQR2, ADC_SQR3, and
ADC_SQR4. For an injected group, the channels to be
scanned are selected by the ADC_JSQR register. The ADC
converts one channel of the group and then continues
successively to convert the next channel of the group.

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ADC Conversion Modes
 Multiple Input Channels
 The conversion operation can be set up to perform only
once or repeatedly, depending on bit CONT bit in the
ADC_CFGR register.

 For the injected group, there is one data register for each
injected channel. However, for a regular group, there is only
one data register that is shared by all channels in this group.
Therefore, after each conversion in a regular group, the
software needs to read the data register between continuous
sampling.

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ADC Conversion Modes
 Multiple Input Channels
 After each conversion, ADC result should be copied to a
user buffer because ADC may overwrite the ADC data
registers (ADC_DR, ADC_JDR1, ADC_JDR2, ADC_JDR3,
and ADC_JDR4).

 An interrupt request or a DMA request can be triggered at

the end of each conversion if enabled. Thus, to reduce the
software overhead, we often use the ADC interrupt handler
or the DMA controller to copy the ADC results to a user
buffer.

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ADC Conversion Modes
Single Channel Mode Scan Mode

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 ADC Conversion Modes:
Single Channel Mode for ADC1 1. Set ADC_CR_ADSTART bit
in ADC1CR register
2. The channel is selected by
ADC_SQR1_SQ1 bits in
ADC1SQR1 register
3. Result is stored in ADClDR
register
4. ADC_ISR_EOS bit in
ADC_CFGR_CONT bit=0
in ADC1CFGR register
ADC_CFGR_CONT bit=1
in ADC1_CFGR register
ADClISR register is set
after conversion
5. Interrupt is generated if
ADC_IER_EOC bit in
ADC1IER register is set
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ADC Conversion Modes
Scan Mode
 Channels are selected by
ADC_SQRx registers for regular
channels, and by ADC_JSQR
register for injected channel

 All channels in a regular group

share the same result register
ADC_DR. Make sure to read data
between consecutive sampling.

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ADC:
 The ADC conversion can be triggered by using
software or external signals.
 Software trigger
 External trigger

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 ADC: Software trigger
 If EXTEN[1:0] bits in the ADC_CFGR register are zero, software
trigger is selected. ADC conversion for the regular group starts
immediately after software sets the ADSTART bit in the ADC_CR
register.
 Similarly, if JEXTEN[1:0] bits are zero, setting the JADSTART bit
starts the ADC conversion for the injected group immediately.
 Hardware automatically clears the ADSTART and JADSTART bits
when
 (1) ADC is in the single conversion mode with software trigger,
or
 (2) software sets the ADSTP or JADSTP bits to stop conversion.
Therefore, if single conversion with software trigger is used,
software needs to set ADSTART or JADSTART again to make
another
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ADC conversion.
 Example 1: ADC with Polling (Busy Waiting)
Main program
(ADC in single conversion mode)

Software starts one ADC

ADC1->CR |= conversion on a single channel.
ADC_CR_ADSTART;
ADC

Wait until EOC_MST is set in Hardware sets

ADC common status register EOC_MST if done.
(ADC_CSR)

Result = ADC1-
>DR;

Repeat if more
conversions are needed
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 Example 2: ADC with Interrupts
Main program

Configure and
Starts ADC
void ADC1_2_IRQHandler(void){
if (ADC1->ISR | ADC_ISR_EOC){
An ADC interrupt buffer[i] = ADC1->DR;
request arrives. i++;
}
...
}

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ADC: Software trigger
 When ADC uses the software trigger, one common
programming error is that the software does not set up the
length of delay at the end of each regular conversion.

 Accordingly, the ADC conversion was only performed

once, instead of continuously.

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 ADC: Software trigger
 In defaulting setting, there is no delay before a new regular
conversion can start. If the system clock is slow, there is no
enough time for the processor to read the ADC data register
(ADC_DR) before a new conversion completes. Therefore, it
is a good practice to set the delay (DELS[2:0] bits in the
ADC_CR2 register) as waiting until software has read the
ADC_DR register or hardware has cleared the EOC flag
(end of conversion) in the ADC_SR register. This delay
setting is also called ADC freeze mode.

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ADC: External trigger
 Hardware signals can be used to trigger ADC
conversions, leading to reduced CPU workload. External
triggers can be selected from the outputs of a timer
(channel outputs CC1, CC2, CC3, CC4, trigger output
TRGO) and external processor pins.

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 ADC: External trigger
 Trigger polarity. The EXTEN[1:0] bits in the ADC_CFGR
register and the JEXTEN[1:0] bits in the ADC_JSQR
register select trigger edges for regular channels and
injected channels, respectively. The trigger edge can be
rising edges, falling edges, or both rising and falling edges.

 Trigger source. The trigger source is selected by the

JEXTSEL [3:0] bits in the ADC_CFGR register and the
JEXTSEL[1:0] bits in the ADC_JSQR register select trigger
source for regular channels and injected channels,
respectively.

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Example 3: ADC Triggered by a Timer

VREF

ADC
Vinput Digital Output
clock trigger

ADC clock

Timer TRGO
Timer clock clock
OC1REF
Channel #1

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Example 3: ADC Triggered by a Timer
main program

start timer
Timer TRGO
signals
ADC interrupt request

ADC ISR
Wait for
ADC_Done =
1 volatile uint ADC_Done = 0;

Process Data void ADC1_2_IRQHandler(void){

if (ADC1->ISR | ADC_ISR_EOC){
result[i] = ADC1->DR;
Repeat i++;
if (i >= N)
ADC_Done = 1;
}
...
}

52 Make N sampling
Example 4: ADC Triggered by a Timer with DMA
main program
DMA copies ADC
start timer DR register to
memory after each
Timer TRGO
DMA conversion.
signals
ADC request
DMA interrupt
Wait for controller request
DMA_Done =
1 DMA ISR

Process Data
volatile uint DMA_Done = 0;

Repeat void DMA1_Channel1_IRQHandler(void){

...
DMA_Done = 1;
...
}

Make N sampling
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 ADC: External trigger example
 The following C program sets the trigger output (TRGO)
of timer 4 as the trigger signal of the ADC converter, as
shown in Figure 20-10. Suppose the ADC sampling rate
is 10 kHz.

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 ADC: External trigger example
 Therefore, timer 4 needs to generate 10,000 TRGO
outputs per second.
 The master mode selection bits (MMS[2:0]) in the CR2
register select which timer's internal signal is used as the
TRGO.
 This example selects the reference output of channel 1
(OC1REF) as TRGO.

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ADC: External trigger example

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ADC: External trigger example
 The following C code selects ADC 1's trigger signal.
 These trigger signals are hardware signals generated
by timers or external clock signal applied to a GPIO pin
(EXTI 11).
 This example selects the external trigger 12 (EXT12),
i.e., the trigger output (TRGO) of timer 4, as the trigger
signal for the regular group. For regular channels, if
ADC has not been started, i.e., ADSTART = 0, ADC
ignores selected trigger signals.
 Similarly, the injected group also ignores hardware
trigger signals if JADSTART = 0.

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ADC: External trigger example

58
ADC: External trigger example

59
 ADC: Measuring the Input Voltage
 A potentiometer, informally a pot, is a three-terminal
variable resistor.

 It uses a sliding contact and works as an adjustable voltage

divider.

 When two outer terminals are connected to Vcc and the

ground respectively, the center terminal generates a
voltage that varies from 0 to Vcc depending on the position
of the sliding contact.

60
 ADC: Measuring the Input Voltage
 In the following sections, we use the internal voltage
reference, which is 3V.

 In this example, we measure the input voltage adjusted by a

potentiometer. If the input voltage Vinput is larger than 1/2 of
Vcc, then we turn on an LED.

 An interesting application is that we use the potentiometer to

control the brightness of an LED dynamically if a PWM
controls the LED.

 The Vinput is used to adjust the duty cycle of the PWM output
signal.
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 ADC: Measuring the Input Voltage
 Suppose the ADC result has 12 bits and ADC is configured
as single-ended. Then, we have the following conversion
result. 𝑉 𝑖𝑛𝑝𝑢𝑡
𝐴𝐷𝐶 𝑅𝑒𝑠𝑢𝑙𝑡=4096 ×
𝑉 𝑅𝐸𝐹

 Therefore, we have.

𝐴𝐷𝐶 𝑅𝑒𝑠𝑢𝑙𝑡
𝑉 𝑖𝑛𝑝𝑢𝑡 = × 𝑉 𝑅𝐸𝐹
4096

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 ADC Configuration Flowchart
 Figure 20-12 shows the flowchart of initializing the continuous
ADCl conversion for channel 6 (GPIO Port A Pin 1, i.e., PA 1)
with a software start of conversion.
 ADC generates an interrupt request at the end of each ADC
conversion if the corresponding ADC interrupt is enabled.

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ADC Configuration Flowchart

64
 ADC Configuration Flowchart
 At the beginning of the
flowchart, the program turns
on the HSI clock and waits
until it is ready.
 The processor clock is
independent of the ADC
clock and can be higher or
lower than the HSI clock.

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ADC Configuration Flowchart

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 ADC Configuration Flowchart
 By default, ADC modules are in the deep-power-down mode to
improve energy efficiency. In this mode, ADC modules are
disconnected from the internal power supply to reduce leakage
currents. Example 20-4 shows the C function that wakes up the
ADC 1.

67
ADC Configuration Flowchart

68
 ADC Configuration Flowchart
 The following is an example C code of the ADC interrupt handler.

69
 ADC Configuration Flowchart
 The following shows how to select a conversion sequence in a
regular group.
 Configuring the ADC regular sequence takes two steps. The
first step is to set the total number of regular input channels.
 The second step is to place the target input channels in the
regular sequence registers (SQR), starting from ADC_SQR1 to
ADC_SQR4. The following shows the code for setting up an
ADC sequence that includes only one regular channel.

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 ADC Configuration Flowchart
 Suppose we want to perform a sequence of ADC conversion on
three regular channels:
 Channel 8 (PA 3), channel 9 (PA 4) and channel 10 (PA 5), as
shown in Figure. We sample channel 9 first, channel 8, channel
10, and again channel 8. The following is the C program code.

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 ADC Configuration Flowchart
 All channels in a regular group share the data register (ADC-
>DR). Therefore, the interrupt handler needs to differentiate
the results of these channels. We use a simple counter to
indicate which channel is being sampled, i.e., which channel
the value in the data register (ADC- >DR) belongs to.

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ADC Configuration Flowchart

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 ADC Configuration Flowchart
 For a regular channel, hardware sets the end of conversion
(EOC) flag at the end of each conversion, indicating that new
ADC result has been stored in the ADC_DR register. Software
must clear the EOC flag explicitly by writing 1 to it or implicitly by
reading register ADC_DR.

 For an injected channel, hardware sets the injected end of

conversion (JEOC) flag at the end of the conversion of each
injected channel in the injected group. Only software can clear
the JEOC flag.

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 ADC Configuration Flowchart
 For a regular group, hardware sets the end of regular
sequence (EOS) flag when ADC converts all channels in this
group. Software clears EOS by writing 1 to it.

 Similarly, for an injected group, hardware sets the end of

injected sequence (JEOS) flag when all channels in this group
have been converted. Writing 1 to JEOS clears this flag.

75
 ADC with DMA
 ADC1 can be connected by the channel 1 of the DMA
controller 1 on STM32L4.

 Suppose the conversion sequence of a regular group is

as follows: channel 9, 8, 10, and 8.

 Whenever the end of conversion flag (EOC) is a set,

ADC generates a trigger signal and sends it to the
DMA.

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 ADC with DMA
 Immediately after receiving the trigger signal, DMA
automatically transfers the ADC result (stored in the
AD's date register DR) to the memory buffer.

77
 ADC with DMA
 In the previous section, we give a short example code
to set up a sequence of 4 conversions: channel 9, 8,
10, and 8. As shown in Figure, DMA automatically
saves the results in the memory buffer ADC_Results.

78
 ADC with DMA
 In the previous section, we give a short example code to set up
a sequence of 4 conversions: channel 9, 8, 10, and 8. As
shown in Figure, DMA automatically saves the results in the
memory buffer ADC_Results.
 ADC_Results[0] holds the result of channel 9. ADC_Results[1]
holds the result of channel 8. ADC_Results[2] holds the result
of channel 10, ADC_Results[3] holds the result of channel 8.

79
 ADC with DMA
 If the DMA channel 1 is in circular mode, the memory
buffer ADC_Results is reused for the next round of ADC
conversions.

 The circular mode allows the processor to reuse the

result array ADC_Results repeatedly during each
sequence of ADC conversions.

 At the end of the third ADC conversion, hardware

automatically resets the destination memory address
register (CMAR) to the address of ADC_Results[0],
making the array continuously serve DMA requests.
80
 ADC with DMA
 The following programs DMA 1 channel 1 to transfer
the results of ADC 1 to ADC_Results.

 Because all regular channels share the same data

register (ADCl->DR), as shown in Figure, the address
increment mode for the peripheral is turned off.

81
 ADC with DMA
 The following programs DMA 1 channel 1 to transfer
the results of ADC 1 to ADC_Results.

 Because all regular channels share the same data

register (ADCl->DR), as shown in Figure, the address
increment mode for the peripheral is turned off.

82
ADC with DMA

83
ADC with DMA

84
Analog Watchdog
Analog voltage
Two programmable thresholds

Higher threshold (HTR)

Guarded Area
Lower threshold (LTR)

 If V < VLTR or V > VHTR, the analog watchdog (AWD) flag (in ADC Status Register)
is set, generating an interrupt to the processor
 The monitor is automatically performed by hardware, not software
 Convenient and efficient feature
 Help processor detect exceptions and recover from specific situations
 For example, monitor sensor data and raise alarm on some level.

85
VREF
 Some chips does not expose VREF to a pin
 STM32L LQFP64 does not have V REF pin
 STM32L LQFP100 does
 Infer internal VREF Corresponds to
 How?

86
Data Alignment
 Software can change the ADC resolution.

 The resolution can be either 12, 10, 8 or 6 bits,

determined by the RES[1:0] bits in the ADC
configuration register ADC_CFGR.

 However, each ADC data register (DR, JDR1, JDR2,

JDR3, and JDR4) has 16 bits. Because ADC results
have fewer bits than ADC data registers, alignment
must be considered when a data result is stored in a
data register.

87
 Data Alignment
 Figure shows different
data alignment formats.

 ADC output data

registers can be either
right-aligned or left-
aligned.

88
Data Alignment
 ADC results are signed when an offset is applied to
a channel. If the OFFSET_EN bit flag is set in the
ADC offset register (OFR), ADC results are
subtracted by a constant defined in the OFR register
before they are saved into ADC data register.

 If the OFFSET_EN bit is set in the OFR register, sign

extension must be performed for both right and left
alignment.

89
Data Alignment
 A sign extension operation duplicates the left-most bit of a
signed number (i.e., the sign bit) to all bits to the left.

 All output data except 6-bit ones are aligned based on half
words, and their memory addresses are a multiple of 2.

 For 6-bit output, the alignment of the data portion is aligned

to the byte boundary. Two zero bits are appended at the
end of the 6-bit output for a regular channel, and one zero
bit is added for an injected channel.

90
91
 Voltage

111 7

110 6

101 5

100 4

011 3

010 2

001 1

000 0
1 2 3 4 5 6 7 8 time (ms)

92
ADC with DMA
 ADC1 can be connected by the channel 1 of the DMA
controller 1 on STM32L4.
 Suppose the conversion sequence of a regular group is
as follows: channel 9, 8, 10, and 8.
 Whenever the end of conversion flag (EOC) is a set,
ADC generates a trigger signal and sends it to the DMA.
Immediately after receiving the trigger signal, DMA
automatically transfers the ADC result (stored in the
AD's date register DR) to the memory buffer.
 In the previous slides, we give a short example code to
set up a sequence of 4 conversions: channel 9, 8, 10,
and 8.
93
ADC with DMA
 As shown in Figure, DMA automatically saves the results in
the memory buffer ADC_Results.
 ADC_Results[0] holds the result of channel 9.
 ADC_Results[l] holds the result of channel 8.
 ADC_Results[2] holds the result of channel 10.
 ADC_Results[3] holds the result of channel 8.

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ADC with DMA
 If the DMA channel 1 is in circular mode, the memory buffer
ADC_Results is reused for the next round of ADC conversions.
 The circular mode allows the processor to reuse the result array
ADC_Results repeatedly during each sequence of ADC conversions.
 At the end of the third ADC conversion, hardware automatically resets
the destination memory address register (CMAR) to the address of
ADC_Results [0], making the array continuously serve DMA requests.

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ADC with DMA
 The following programs DMA 1 channel 1 to transfer the
results of ADC 1 to ADC_Results.

 Because all regular channels share the same data

register (ADC1->DR), the address increment mode for
the peripheral is turned off.

96
ADC with DMA

97
ADC with DMA

98
ADC with DMA with Ping-Pong Buffering
 Ping-pong buffering, also called double buffering, is a
software technique that uses two buffers to overlap data
transfer and data processing, as shown in Figure.

 Software alternates between processing the ping buffer

and the pong buffer. This scheme gives the processor
more time to process data without pausing ADC
conversion.

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ADC with DMA with Ping-Pong Buffering
 While the OMA controller is filling the ping buffer with
ADC data, the processor is processing the data
stored in the pong buffer. Once the ping buffer is full,
the processor starts to process the pong buffer while
new data is being filled into the pong buffer.
 Therefore, data transfer and data processing are
performed in parallel.

100
ADC with DMA with Ping-Pong Buffering
 As shown in Figure, when DMA completes its data
transfer, an interrupt request can be generated, and
the DMA interrupt handler swaps the DMA source
memory address between these buffers.

101
ADC with DMA with Ping-Pong Buffering
 Example shows the basic code that implements the
ping-pong buffering.

102
ADC with DMA with Ping-Pong Buffering
 Example shows the basic code that implements the
ping-pong buffering.

103
ADC with DMA with Ping-Pong Buffering
 Example shows the basic code that implements the
ping-pong buffering.

104