Government Polytechnic Jintur

Department of Computer Engg

Course Name: Operating System (OSY)

Course Code : 22516

M.A. Zahed
Lecturer
Unit V: Memory Management
Free space management
techniques
⚫The OS must manage the
memory when allocated
dynamically.
⚫There are two approaches to
keep track of memory usages

-Bit Map
-Linked List
Bit Map
⚫With a bit map, memory is
divided into allocation units.
⚫Corresponding to each allocation
unit there is a bit in a bitmap.
⚫Bit is 0 if unit is free and it is 1 if
unit is occupied.
⚫The size of allocation unit is an
important issue, the smaller the
size, the larger size of bitmap
Bit Map
⚫The main problem is that when it
has been decided to bring a k
unit process the memory
manager must search a bitmap
to find a run of k consecutive 0
bits in the map.
⚫Searching a bitmap for a run of
given length is a slow operation.
⚫It is tedious to keep the bitmap
in memory for large disks.
Bit Map
Linked List
⚫Another way of keeping track of
memory is to maintain a linked
list of allocated and free memory
segments, where a segment
either contains a process or is an
empty hole between two
processes.
Linked List
⚫The segment list is kept sorted
by address. Sorting this way has
the advantage that when a
process is swapped out or
terminates, updating the list is
straightforward.

⚫Linked list maintenance can be a

difficult one.
Memory Management

⚫ Background
⚫ Swapping
⚫ Contiguous Memory Allocation
⚫ Paging
⚫ Structure of the Page Table
⚫ Segmentation
 Learning Outcomes
⚫ To provide a detailed description of various
ways of organizing memory hardware
⚫ To discuss various memory-management
techniques, including paging and
segmentation
Background

⚫ Program must be brought (from disk) into

memory to run
⚫ Main memory and registers are only storage
CPU can access directly
⚫ Register access in one CPU clock (or less)
⚫ Main memory can take many cycles
⚫ Cache sits between main memory and CPU
registers
⚫ Protection of memory required to ensure
correct operation
 Base and Limit Registers
⚫ A pair of base and limit registers define the logical
address space
Multistep Processing of a User Program
 Logical vs. Physical Address Space

⚫ The concept of a logical address space that is

bound to a separate physical address
space is central to proper memory
management
◦ Logical address – generated by the CPU;
also referred to as virtual address
◦ Physical address – address seen by the
memory unit
⚫ Logical and physical addresses are the same
in compile-time and load-time address-
binding schemes; logical (virtual) and physical
addresses differ in execution-time address-
binding scheme
Memory-Management Unit (MMU)

⚫ Hardware device that maps virtual to

physical address
⚫ In MMU scheme, the value in the
relocation register is added to every
address generated by a user process at
the time it is sent to memory
⚫ The user program deals with logical
addresses; it never sees the real
physical addresses
Dynamic relocation using a
relocation register
 Dynamic Loading
⚫ Routine is not loaded until it is called.

⚫ Better memory-space utilization;

unused routine is never loaded.

⚫ Useful when large amounts of code are

needed to handle infrequently occurring
cases
 Swapping
⚫ A process can be swapped temporarily out of
memory to a backing store, and then brought
back into memory for continued execution
⚫ Backing store – fast disk large enough to
accommodate copies of all memory images
for all users; must provide direct access to
these memory images
⚫ Roll out, roll in – swapping variant used for
priority-based scheduling algorithms; lower-
priority process is swapped out so higher-
priority process can be loaded and executed
⚫ Major part of swap time is transfer time; total
transfer time is directly proportional to the
amount of memory swapped
⚫ System maintains a ready queue of ready-
to-run processes which have memory images
on disk
Schematic View of Swapping
Contiguous Allocation

⚫ Main memory usually into two partitions:

◦ Resident operating system, usually held in low
memory with interrupt vector
◦ User processes that held in high memory
⚫ Relocation registers used to protect user processes
from each other, and from changing operating-
system code and data
◦ Base register contains value of smallest physical
address
◦ Limit register contains range of logical addresses
– each logical address must be less than the limit
register.MMU maps logical address dynamically
Hardware Support for Relocation
and Limit Registers
Contiguous Allocation (Cont.)

⚫ Multiple-partition allocation
◦ Hole – block of available memory; holes of various
size are scattered throughout memory
◦ When a process arrives, it is allocated memory from
a hole large enough to accommodate it
◦ Operating system maintains information about:
a) allocated partitions b) free partitions (hole)

OS OS OS OS

process 5 process 5 process 5 process 5

process 9 process 9

process 8 process 10

process 2 process 2 process 2 process 2

 Dynamic Storage-Allocation Problem

How to satisfy a request of size n from a list of free holes

⚫ First-fit: Allocate the first hole that is big enough
⚫ Best-fit: Allocate the smallest hole that is big
enough; must search entire list, unless ordered by size

◦ Produces the smallest leftover hole

⚫ Worst-fit: Allocate the largest hole; must also search
entire list

First-fit and best-fit better than worst-fit in terms of

speed and storage utilization (according to
simulations)
Fragmentation

⚫ External Fragmentation – total memory

space exists to satisfy a request, but it is not
contiguous
⚫ Internal Fragmentation – allocated memory
may be slightly larger than requested
memory; this size difference is memory
internal to a partition, but not being used
⚫ Reduce external fragmentation by
compaction
◦ Shuffle memory contents to place all free
memory together in one large block
◦ Compaction is possible only if relocation is
dynamic, and is done at execution time
 Paging
⚫ Logical address space of a process can be
noncontiguous; process is allocated physical memory
whenever the latter is available
⚫ Divide physical memory into fixed-sized blocks called
frames (size is power of 2, between 512 bytes and
8,192 bytes)
⚫ Divide logical memory into blocks of same size called
pages
⚫ Keep track of all free frames
⚫ To run a program of size n pages, need to find n free
frames and load program
⚫ Set up a page table to translate logical to physical
addresses
⚫ Internal fragmentation
Address Translation Scheme

⚫ Address generated by CPU is divided into:

◦ Page number (p) – used as an index into a page
table which contains base address of each page in
physical memory
◦ Page offset (d) – combined with base address to
define the physical memory address that is sent to
the memory unit
page number page offset

p d

m-n n

◦ For given logical address space 2m and page size 2n

Paging Hardware
Paging Model of Logical and
Physical Memory
Paging Example

32-byte memory and 4-byte pages

 Segmentation
⚫ Memory-management scheme that supports user view
of memory
⚫ A program is a collection of segments
◦ A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays
User’s View of a Program
Logical View of Segmentation

4
1

3 2
4

user space physical memory space

Segmentation Architecture
⚫ Logical address consists of a two tuple:
<segment-number, offset>,
⚫ Segment table – maps two-dimensional physical
addresses; each table entry has:
◦ base – contains the starting physical address
where the segments reside in memory
◦ limit – specifies the length of the segment
⚫ Segment-table base register (STBR) points to
the segment table’s location in memory
⚫ Segment-table length register (STLR)
indicates number of segments used by a program;
segment number s is legal if s < STLR
Segmentation Hardware
Example of Segmentation
Paging vs Segmentation
Page Fault
Page replacement algorithms
⚫FIFO (First in first out)
⚫LRU (Least recently used)
⚫Optimal
FIFO (First in first out)
⚫Consider a reference string
as

1,2,3,4,1,2,5,1,2,3,4,5

Find no. of page faults when

there are 3 frames
FIFO (First in first out)
⚫It is very simple and easy to
implement.
⚫It suffers from Belady’s
anomaly.
⚫System needs to keep track
of each frame
LRU (Least recently used)
⚫It chooses the page which
has not been referenced for
the longest time.

⚫System maintains a
timestamp for every page
that indicates the time of last
access.
Optimal page
replacement
⚫The page which will not be
accessed permanently or for
the longest period of time
should be replaced.
⚫It gives less page fault
compared with FIFO and LRU.
⚫Difficult to implement
because of future reference.
Learning Outcome
⚫Explain FIFO, LRU, OPTIMAL page
replacement algorithms
Thank You..!!!