Module-4

Subsystem Design and Layout-1 : Switch logic pass transistor, Gate logic inverter, NAND gates, NOR gates,
pseudo nMOS, Dynamic CMOS, example of structured design, Parity generator, Bus arbitration, multiplexers,
logic function block, code converter.

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Module-4
Subsystem Design and Layout-1 : Switch logic pass transistor, Gate logic inverter, NAND gates, NOR gates,
pseudo nMOS, Dynamic CMOS, example of structured design, Parity generator, Bus arbitration, multiplexers,
logic function block, code converter.

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Module-4
Subsystem Design and Layout-1 : Switch logic pass transistor, Gate logic inverter, NAND gates,
NOR gates, pseudo nMOS, Dynamic CMOS, example of structured design, Parity generator, Bus
arbitration, multiplexers, logic function block, code converter.

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Module-4
Subsystem Design and Layout-1 : Switch logic pass transistor, Gate logic inverter, NAND gates,
NOR gates, pseudo nMOS, Dynamic CMOS, example of structured design, Parity generator, Bus
arbitration, multiplexers, logic function block, code converter.

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To change the Vt only in mos
technology not in BJT PUSH PULL
configuration
Transistors

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NAND=AB

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 Pseudo=partial
Pull up=pmos=always on =act as resistor
Pull down=nmos logic realization based on logic
function
Partially using half nmos & half pmos

Z=ABC
Advantages
1) Uses less number of transistors as compared to CMOS logic.
2) Geometrical area and delay gets reduced as it requires less transistors.
3) Low power dissipation.
Disadvantages
2) The main drawback of using a pseudo nMOS gate instead of a CMOS gate is
that the always on PMOS load conducts a steady current when the output
voltage is lower than VDD.
2) Layout problems are critical.
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1. Charge sharing may be a problem unless the inputs are
constrained not to change during the on period of the clock.
2. Single phase dynamic logic structures cannot be cascaded since,
owing to circuit delays, an incorrect input to the next stage may be
present when evaluation begins, so that its output is inadvertently
discharged and the wrong output results.

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Delay reduced
Improve the signals

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Examples of structured design
(combinational logic)

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A parity generator

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Bus arbitration logic for n-line bus

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 Explain bus arbitration logic for n-line bus moving from unstructured design to structured design.

• A direct but unstructured implementation of these expressions may

be readily envisaged and a suitable arrangement of switch (pass
transistor) logic.
• we have shown only the top three lines in Figure , but it will be seen that:
• A requires one diffusion path and no switches
• An-1 requires two diffusion paths and two switches
• An-2 requires three diffusion paths and four switches

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This is not a regular structure and is not well suited for VLSI implementation.
Therefore, we must take a cellular approach by setting out the requirements in
alternative fashion as in Figure6.21 .
A regular structure having been arrived at, the requirements for each cell may be expressed
as follows:

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These requirements may be met by the circuit of Figute 6-22, but care must be taken not to cascade more than four cells
without buffering the grant line. The' art of arriving at conveniently expressed relationships which allow a structured,
design is one which must be cultivated and it is often helped by adopting an 'if, then, else (or otherwise)' approach. The
solution to the problem under consideration can be formulated after expressing the need of each cell in words:

However, there is a danger with expressions of the conventional

Boolean type - a tendency to ignore the fact that MOS switch logic is
such that not only must the logic 1 condition be satisfied, but it is also
necessary to deliberately satisfy the logic 0 conditions. The TTL logic
designer is used to working with logic circuits in which the output
must be logic 0 if the logic I output conditions are not satisfied.
However, some MOS switch-based logic circuits have the property
that if the logic 1 output conditions are not met, then the output can
be indeterminate or, if some storage capacitance is present (for
example, input capacitance Cg of an inverter), then the output can
remain at logic I even after the conditions which caused it no longer
exist. Thus, it is necessary to deliberately implement the 'else'
conditions. We must, therefore, write expressions for both the logic 1
and logic 0 conditions of the output lines, thus

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which is the circuit realized in Figure 6-22. This circuit is suitable for implementation in nMOS or in CMOS
technology. Although in the CMOS case there is the possibility of replacing the n-type pass transistors by
transmission gates; there is no advantage to be gained from this as the degrading of logic 1 level is
counteracted by the presence of buffers after every fourth cell. There is clearly an area advantage in using
simple n-type pass transistors and the only difference, therefore, between an nMOS and a CMOS design will be
the type of buffer (inverter) stages.

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 A general logic function block
• An arrangement to generate any function of two variables (A, B) is readily formed from
any form of four-way multiplexer. The general approach is indicated in Figure 6-26. It will
be seen that the required function is generated by driving the multiplexer select inputs
from the required two variables A and B and by 'programming' the inputs I0_I3
appropriately with Os and is, as indicated in the figure. Larger multiplexers may be
similari' employed to generate any function of up to four variables (16-way multiplexer).

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A four-line Gray code to binary code
converter
• A very widely used logic arrangement (the Exclusive-Or gate),
consider the requirement for code conversion from Gray to binary as
set out.

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Module-4:Subsystem Design and Layout-2 : Clocked sequential circuits,
dynamic shift registers, bus lines,
subsystem design processes: General considerations, 4-bit arithmetic
processes, 4-bit shifter.
Some clocked sequential circuits
• 6.5.1 Two-phase clocking

The clocked circuits to be considered here will be based on a two-phase nonoverlapping clock signal as defined by Figure 6-31. A
two-phase clock offers a great deal of freedom in sequential circuit design if the clock period and the duration of the signals 4)
and 4)2 are correctly .hosen. If this is the case, data is allowed to become stable before any further transfer takes place and
there is no chance of race conditions occurring. Clocked circuitry is considerably easier to design than the corresponding
asynchronous sequential circuitry. It does, however, usually pay the penalty of being slower. However, at this stage of learning
VLSI design we will concentrate on two-phase clocked sequential circuits alone and thus simplify design proced. When studying
Figure 6-31, it is necessary to recognize the fact that 4) and 4)2 do not need to be symmetrical as shown. For a given clock
period, each clock phase period and its associated underlap period can be varied if the need arises in optimizing a design. A
number of techniques are used to generate the two clock phases. One popular method is illustrated in Figure 6-32 and it will be
seen that the output frequency is one-quarter of that of the input clock.

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• A very simple arrangement using combinational logic and generating a twophase clock at the
frequency of a single-phase input clock is set out in Figure 6-33(a). The input clock signal C is used
to provide a delayed version of itself (CD) by passing it through an even number of inverters. The
delay thus produced determines the underlap period for the two-phase clock. Waveforms are as
shown in Figure 6-33(b). The phase I signal 4) (PHI) is generated by Anding C with CD whilst the
phase 2 signal 4)2 (PH2) is produced by Noring C with CD (that is, Anding C'with CD’). Clearly, the
minimum underlap period will be that generated by the delay through two inverters and this is
also the increment by which the delay may be increased by adding further inverter pairs.

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Since clock lines often feed many stages and are associated with long bus tines, they often
present quite considerable capacitance to the clock line drivers. Here then is a case where a
bipolar capability can be used to advantage to drive the high capacitance load. This approach is
demonstrated in Figure 6-34, which uses bipolar-based output stages and also produces the
complements of the two phases since complementary clocks are almost invariably required.
Simulation waveforms are given in Figure 6-34(b) and a possible mask layout is presented as
Color plate 12.

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A dynamic shift register

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Basic arrangements for bus lines

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The precharged bus concept

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4-bit arithmetic processor

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Design of a 4-bit shifter

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