MICROPROCESSOR

AND
MICROCONTROLLER
1

UNIT I - THE 8086

MICROPROCESSOR
• – INTRODUCTION TO 8086
• – MICROPROCESSOR ARCHITECTURE
• – ADDRESSING MODES
• – INSTRUCTION SET AND ASSEMBLER DIRECTIVES
• – A S S E M B LY L A N G U A G E P R O G R A M M I N G
• – MODULAR PROGRAMMING
• – L I N K I N G A N D R E L O C AT I O N
• – S TA C K S – P R O C E D U R E S – M A C R O S
• – I N T E R R U P T S A N D I N T E R R U P T S E RV I C E
R O U T ,IAP/ECE
S.KARTHICK NES
 UNIT-I
8086
16-BIT
MICROPROCESSORS

S.KARTHICK, AP/ECE 2
 8086
Microprocessor

S.KARTHICK., AP/ECE 3
Introduction to 8086 Microprocessor
 Features:
1. Intel 8086 was launched in 1978.
2. It was the first 16-bit microprocessor.
3. It is available as 40-pin Dual-Inline-Package (DIP).
4 It requires +5 V power supply.
5. It consists of 29,000 transistors.
6. It operates in two modes Minimum and
Maximum.
7. 8086 has a 20 bit address bus can access up to
220 Memory locations (1 MB).
8. It provides fourteen 16 -bit registers.
9. It has multiplexed address and data bus
AD0- AD15 and A16 – A19.

S.KARTHICK., AP/ECE 4
8086
PIN DIAGRAM

S.KARTHICK., AP/ECE 5
 Pin Description
1. AD15 ± AD0: ADDRESS DATA BUS - These lines constitute the time
multiplexed memory/IO address and data bus.

2. NMI: NON-MASKABLE INTERRUPT: an edge triggered input which

causes
an interrupt request to the MP. NMI is not maskable internally by
software.

3. INTR: INTERRUPT REQUEST

4. VCC & VSS: Power supply VCC=+5 V & VSS=GND reference.

5. RESET: causes the processor to immediately terminate its present

activity. It restarts execution.

6. READY: is the acknowledgement from the addressed memory or I/O

device that it will complete the data transfer.

7. TEST‾ : This input is examined by a ‘WAIT’ instruction. If the TEST

pin goes low, execution will continue, else the processor remains in
an idleAP/ECE
S.KARTHICK., state. 6
 Pin Description
8. RD ‾ : READ - This signal on low indicates that the processor is
performing memory or I/O read operation.

9. MN/MX ‾ :
• MINIMUM MODE - The 8086 processor works in a single
processor environment. All control signals for memory and I/O are
generated by the μp.
• MAXIMUM MODE - is designed to be used when a coprocessor
exists in the system. 8086 works in a multiprocessor environment.
Control signals for memory and I/O are generated by an external
BUS Controller

10.BHE ‾/S7 : BUS HIGH ENABLE - used to indicate the transfer of

data over the higher order ( D15-D8 ) data bus .

11. A19/S6,A18/S5,A17/S4,A16/S3 : 20 -bit Address Bus

These are the time multiplexed address and status lines.

S.KARTHICK., AP/ECE 7
 Pin Description
MINIMUM MODE:

1. INTA: INTERRUPT ACKNOWLEDGE

2. ALE: ADDRESS LATCH ENABLE – when HIGH µP is using AD0-

AD7,A19/S6,A18/S5,A17/S4,A16/S3 as address lines

3. DEN: DATA ENABLE. It is LOW when processor wants to receive data

or processor is giving out data

4. DT/R‾: DATA TRANSMIT/RECEIVE.

When High, data from µP to memory, When Low, data is from memory
to µP.

5. M/IO‾: If High µP access Memory Device, If Low µP access I/O Device.

6. WR‾: WRITE data on memory or an I/O device.

7. HLDA: HOLD Acknowledge signal

8. HOLD: HOLD signal

S.KARTHICK., AP/ECE 8
 Pin Description
MAXIMUM MODE

1. QS1, QS0: QUEUE STATES

QS1 QS0 Indication
0 0 No operation
0 1 First byte of opcode from the Queue
1 0 Empty queue
1 1 Subsequent byte from the queue

2. S2‾, S1‾, S0‾: STATUS signals

S2 S1 S0 Indication
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code Access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive

3. LOCK ‾: Other system bus master will be prevented from gaining the
system bus
4. RQ‾/GT1‾: REQUEST/GRANT1 5. RQ‾/GT0‾: REQUEST/GRANT0
S.KARTHICK., AP/ECE 9
 8086
ARCHITECTUR
E

S.KARTHICK., AP/ECE 10
 8086 ARCHITECTURE

S.KARTHICK., AP/ECE 11
 8086 Architecture
 8086 has two blocks Bus Interfacing Unit (BIU) and Execution Unit
(EU).

 The BIU performs all bus operations such as instruction fetching,

reading and writing operands for memory and calculating the
addresses of the memory operands.
 BIU contains Instruction queue, Segment registers, Instruction
pointer, Address adder.

 The EU executes instructions from the instruction system byte

queue.
 EU contains Control circuitry, Instruction decoder, ALU, Pointer
and Index register, Flag register.

S.KARTHICK., AP/ECE 12
 BUS INTERFACE UNIT (BIU)
The function of BIU is to
 Fetch the instruction or data from memory.
 Write the data to memory.
 Write the data to the port.
 Read data from the port.

Instruction Queue:
1. To increase the execution speed, BIU fetches as many as six
instruction bytes
ahead to time from memory.
2. All six bytes are then held in FIFO 6 byte register called instruction
queue.
3. Then all bytes have to be given to EU one by one.
4. This pre fetching operation of BIU may be in parallel with execution
S.KARTHICK., AP/ECE 13
operation of EU, which improves the speed execution of the
 EXECUTION UNIT (EU)
The functions of EU are
 To tell BIU where to fetch the instructions or data from.
 To decode the instructions.
 To execute the instructions.
The EU contains the control circuitry to perform various internal
operations.
A decoder in EU decodes the instruction fetched memory to generate
different internal or external control signals required to perform the
operation.
EU has 16-bit ALU, which can perform arithmetic and logical
operations on 8-bit as well as 16-bit.
Both units operate asynchronously to give the 8086 an overlapping
instruction fetch and execution mechanism which is called as
S.KARTHICK., AP/ECE 14
Pipelining. This results in efficient use of the system bus and system
 8086 REGISTERS
The 8086 microprocessor has a total of fourteen registers
that are accessible to the programmer. It is divided into four
groups.
They are:

 4 General purpose registers

 4 Index/Pointer registers
 4 Segment registers
 2 Other registers

S.KARTHICK., AP/ECE 15
 General Purpose Registers of 8086
• It can be used as 8 bit registers individually or can be used as 16 bit
in pair.
1. AX Register: AX register is also known as accumulator register that
stores operands for arithmetic operations.
2. BX Register: This register is mainly used as a base register. It holds
the starting base location of a memory region within a data segment.
3. CX Register: It is defined as a counter. It is primarily used in loop
instruction to store loop counter.
4.DX Register: Data register is used to hold 16 bit data result

S.KARTHICK., AP/ECE 16
 Index & Pointer Registers

• The 8086 has four other general purpose registers, two

pointer registers Stack Pointer and Base Pointer and two
index registers Source Index and Destination Index. Used
to store the offset addresses
• An offset address Refers to a value added to a
base address to produce a second address.

S.KARTHICK., AP/ECE 17
 Segment Register
• Segment register is used to hold the upper 16 bits of the starting
address for each of the segments.
• The four segment registers are:
1. Code segment (CS) : The CS register is used for addressing a
memory location in the Code Segment of the memory, where the
executable program is stored.
2. Data Segment (DS): The DS contains most data used by program.
Data are accessed in the Data Segment by an offset address or the
content of other register that holds the offset address.
3. Stack Segment (SS): SS defined the area of memory used for the
stack.
4. Extra Segment (ES): used to hold the starting address of Extra
segment. Extra segment is provided for programs that need to access a
second data segment. Segment registers cannot be used in arithmetic
S.KARTHICK., AP/ECE 18
operations.
 Segment Register

S.KARTHICK., AP/ECE 19
 Other Register
1. Instruction Pointer (IP) is a 16-bit register. This is a important
register which is used to control which instruction the CPU executes.
The IP or program counter, is used to store the memory location of the
next instruction to be executed.

2. Flag Register contains a group of status bits called flags that

indicate the status of the CPU or the result of arithmetic operations.
There are two types of flags:
1. The status flags which reflect the result of executing an
instruction. The programmer cannot set/reset these flags directly.
2. The control flags enable or disable certain CPU operations. The
programmer can set/reset these bits to control the CPU's operation.
S.KARTHICK., AP/ECE 20
Status Flags: There are six status flags
1. The Carry Flag (C):
2. The Overflow Flag (O):This flag is set when the result of a signed
arithmetic operation is too large to fit in the destination register.
A value of 1 = overflow and 0 = no overflow.
3. The Sign Flag (S):
4. The Zero Flag (Z):
5. The Auxiliary Carry Flag (A):
6. The Parity Flag (P):

S.KARTHICK., AP/ECE 21
Control Flags: There are three control flags

1. The Direction Flag (D): Affects the direction of moving data blocks by
such instructions as MOVS, CMPS and SCAS. The flag values are 0 = up and 1
= down and can be set/reset by the STD (set D) and CLD (clear D) instructions.
2. The Interrupt Flag (I): Dictates whether or not system interrupts can
occur. The flag values are 0 = disable interrupts or 1 = enable interrupts and
can be manipulated by the CLI (clear I) and STI (set I) instructions.
3. The Trap Flag (T): Determines whether or not the CPU is halted after the
execution of each instruction. When this flag is set (i.e. = 1), the programmer
can single step through his program to debug any errors. When this flag = 0
this feature is off. This flag can be set by the INT 3 instruction.

S.KARTHICK., AP/ECE 22
 Programmers model of 8086

S.KARTHICK., AP/ECE 23
 8086
ADDRESSING
MODES

S.KARTHICK., AP/ECE 24
 Operand Types of 8086
The 8086 supports the following types of operand

1. Bytes (8-bit)
2. Words (16-bit)
3. Short integers (8-bit)
4. Integers (16-bit)
5. Double words (32-bit)
6. Long integers (32-bit)
7. Strings (Series of alphanumeric characters
defined by ASCII codes)
S.KARTHICK., AP/ECE 25
 Operand Addressing
Addressing mode indicates a way of locating data or operands, We can
classify the addressing modes of 8086 into 6 groups:

 Register addressing mode

 Immediate addressing mode
 Memory addressing mode
 Port addressing mode
 Relative addressing mode
 Implied addressing mode

S.KARTHICK., AP/ECE 26
 ADDRESSING MODES of 8086

1. Register Addressing Mode:

8086 CPU contains 8 General-Purpose Registers or Working Registers
AX,BX,CX,DX,BP,DI,SI,SP and 4 Segment Registers CS,DS,ES,SS
Source Registers: AX,BX,CX,DX,DI,SI,BP,SP,CS,DS,ES,SS
Destination Registers: AX,BX,CX,DX,DI,SI,BP,SP, DS,ES,SS
Ex.1: MOV AL,CL Ex.2: MOV DS,SI

2. Immediate Addressing Mode: 8 or 16 bit data can be specified as part

of the instruction
Ex: MVI AL,34H MVI SI,1212H

S.KARTHICK., AP/ECE 27
 ADDRESSING MODES of 8086
3. Memory addressing mode
 One of the operands is in memory
 8086 must use
 a segment register
 a 16-bit offset (effective address)
 By default, DS register is used for accessing data from memory
 16-bit offset can be specified in many ways

1. Direct Addressing mode

2. Register Indirect or Indirect Addressing mode
3. Base plus index Addressing mode
4. Register Relative Addressing mode
5. Base Relative plus Index Addressing mode
6. String Addressing mode
S.KARTHICK., AP/ECE 28
cont…
 ADDRESSING MODES of 8086
3. Memory addressing mode
1. Direct addressing mode

Ex:
MOV AL, DS
MOV DS, DL

MOV AX, DS

cont…
S.KARTHICK., AP/ECE 29
 ADDRESSING MODES of 8086
3. Memory addressing mode
2. Register Indirect or Indirect Addressing mode

• In this mode, the Effective Address is specified in either a pointer register (BX or
BP) or an index register (SI or DI).
Ex: MOV BX,[CX] ;DS=10000H CX=2000H
;Physical Address: 12000H=30 12001H=40
;BX=4030H BH=40H BL=30H

3. Base plus index Addressing mode

Ex: MOV CX,[BX+DI] ;DS=10000H BX=2000H DI=0030H
;Physical Address: 12030H=20 12031H=10
;CX=1020H CH=10H CL=20H

cont…
S.KARTHICK., AP/ECE 30
 ADDRESSING MODES of 8086
3. Memory addressing mode
4. Register Relative Addressing mode
CH CL

CX

Ex: MOV CX,[BX+0003H] ;DS=10000H BX=1000H

;Displacement=3 Base+Disp=1003H
;11003H=30H 11004H=40H
;CX=4030H CH=40H CL=30H
cont…
S.KARTHICK., AP/ECE 31
 ADDRESSING MODES of 8086
3. Memory addressing mode
5. Base Relative plus Index Addressing mode

Ex: MOV AL,[BX+SI+10H]

cont…
S.KARTHICK., AP/ECE 32
 ADDRESSING MODES of 8086

3. Memory addressing mode

6. String Addressing mode
• Used when string related instructions are executed. It uses index
registers.
• The string instructions automatically assumes SI to point the first byte
or word of the source operand and DI to point the first byte or word of
the destination operand.

Ex: MOVS BYTE

initially:
[DF]=0 [DS]=30000H [SI]=0600H
[ES]=50000H [DI]=0400H
30600H=38H 50400H=45H
after execution:
50400H=38H [SI]=0601H [DI]=0401H

S.KARTHICK., AP/ECE 33
 ADDRESSING MODES of 8086
4. Port addressing
Two I/O port addressing modes can be used
Direct (e.g. IN AL, 02H)
Indirect (e.g. IN AL, DXH)

5. Relative addressing

Ex: JNC 08H ;IF carry = 0, PC is loaded with current PC contents

+ 8-bit signed value

6. Implied addressing mode

No operands are specified
Ex: CLC ;Means clear carry flag

S.KARTHICK., AP/ECE 34
 8086
ASSEMBLER
DIRECTIVES

S.KARTHICK., AP/ECE 35
 Assembler Directives of 8086
 Assembler is a program which converts assembly language to machine language.
 Syntax errors, logical errors and other program errors are not found out by the
assembler.
 For completing all these tasks the assembler needs some hints from the program,
these hints are given to the assembler using some predefined alphabetical strings
called “Assembler Directives”

1. ASSUME: The directive is used to inform the assembler the names of the logical
segment which are to be assigned to the different segments used in an assembly
language program
2. DB (Define Byte): It defines a byte type variable which occupies 1byte of memory
space.

S.KARTHICK., AP/ECE 36
 Assembler Directives of 8086
3. DW (Define Word): It defines a word type variable which occupies 2bytes of
memory space.
4. DD (Define Double Word): It defines a double word type variable which occupies
4bytes of memory space.
5. DQ (Define Quad Word): It defines a quad word type variable which occupies
8bytes of memory space.
6. DT (Define Ten Bytes): It defines a variable which occupies 10bytes of memory
space.
7. END (End of Program): It informs assembler the end of program module.
8. ENDP (End Procedure): It informs assembler the end of procedure (subroutines)
9. ENDM (End Macro): It informs assembler the end of the macro. It used with the
directive MACRO to enclose macro instructions.
10. ENDS (End Segment): It informs assembler that it is the end of a segment.
S.KARTHICK., AP/ECE 37
 Assembler Directives of 8086
11. EQU (Equate): It is used to give a name to certain value or symbol which is used
many times in an assembly language program to make programming easy.
12. EVEN (Align or Even memory address): It informs assembler to increment the
content of the location counter to the next memory address, if it is already no at
an even address.
13. EXTRN (External): It informs that the names, procedures and labels following this
directive have already been defined in some other program module.
14. GLOBAL: It can be used in place of public or external directive.
15. GROUP: It informs assembler to form a logical group of the segments named after
this directive.
16. INCLUDE (Include source code from file): It informs assembler to insert a block of
codes from a named file in to the current program module. It is convenient to keep
all data and macros in a file called header file or include file.
S.KARTHICK., AP/ECE 38
 Assembler Directives of 8086
17. LABEL: In assembly language program, labels are used to give names to memory
addresses.
18. LENGTH: It is an operator to determine the no. of elements in a data item such as
an array or a string.
19. LOCAL: When certain variables, constants, procedures or labels are to be used in
only one program module, they are declared local using LOCAL directive
20. MACRO: A sequence of instructions to which a name is assigned. Same as
subroutines.
21. NAME: A large program module contain several program modules so specific
name can be given to each program module using NAME directive.
22. OFFSET: It is an operator to determine the offset of a variable or procedure with
respect to the base of the segment which contains the named variable or
procedure.
S.KARTHICK., AP/ECE 39
 Assembler Directives of 8086
23. ORG (Originate): The ORG directive directs the assembler to set the location
counter at memory address specified after the directive.
24. PROC (Procedure): It indicate the start of a procedure. The type of the procedure
FAR or NEAR is to be specified after the directive.
NEAR is used to call a procedure which is within the program module and FAR is
used to call from some other program module.
25. PTR (Pointer): It indicates the type (BYTE, WORD or DW) of a variable or label.
26. PUBLIC: a large program usually consist of several program modules. The
variables, constants, procedures and labels defined in a program module may be
used in some other program module. So such items are to be declared public using
PUBLIC directive.
27. RECORD: It defines the bit pattern within a byte or word
28. SEG(Segment): It is an operator used before a variable, procedures and label
S.KARTHICK., AP/ECE 40
 Assembler Directives of 8086
29. SEGMENT (Logical Segment): It indicates the beginning of a logical segment. The
SEGMENT and ENDS directives are used to enclose a logical segment containing
code or data.
30. SHORT: It is an operator. It informs assembler that only one byte for the
displacement is required to code a jump instruction.
31. SIZE: it is an operator to determine the number of bytes allocated to a data item.
It differs from the LENGTH operator as it determines the no. of elements in a data
item.
32. STRUCK or STRUC (Structure Declaration): It defines the beginning of a data
structure which is a collection of primary data types such as DB, DW, DD is
declared.
33. TYPE: It is an operator that determines the type of a variable. It actually
determines the no. of bytes allocated to the variable and substitutes the no. in
place ofAP/ECE
S.KARTHICK., the variable before which TYPE
41appears.
 8086
INSTRUCTION
SET

S.KARTHICK., AP/ECE 42
 8086 INSTRUCTION SET
It is classified into 7 Categories.
They are:

1. DATA TRANSFER INSTRUCTIONS

2. ARITHMETIC INSTRUCTIONS
3. LOGICAL INSTRUCTIONS
4. CONTROL INSTRUCTIONS
5. PROCESSOR CONTROL INSTRUCTIONS
6. STRING MANIPULATION INSTRUCTIONS
7. INTERRUPT CONTROL INSTRUCTIONS

S.KARTHICK., AP/ECE 43
 1.DATA TRANSFER INSTRUCTIONS
GENERAL PURPOSE BYTE OR WORD TRANSFER
INSTRUCTIONS

 MOV Instruction - MOV destination, source

Example: MOV DL,[BX] : Copy byte from memory at BX to DL
 PUSH Instruction - PUSH source
Example: PUSH BX
 POP Instruction - POP destination
Example: POP DX
 XCHG Instruction - Exchange XCHG destination, source
Example: XCHG AX, DX
 XLAT/XLATB Instruction - Translate a byte in AL with byte pointed in BX
Example: MOV AL, [BX+AL]
S.KARTHICK., AP/ECE 44
 1.DATA TRANSFER INSTRUCTIONS
SIMPLE INPUT AND OUTPUT PORT TRANSFER INSTRUCTION
 IN Instruction - Copy data from a port IN accumulator, port
Example: IN AL,0C8H

 OUT Instruction - Output a byte or word to a port – OUT port, accumulator AL or

AX. Example: OUT 3BH, AL

SPECIAL ADDRESS TRANSFER INSTRUCTIONS

 LEA Instruction - Load Effective Address
Syntax – LEA register, source
Example: LEA BX, PRICE ;Load BX with offset of PRICE in DS

 LDS Instruction - Load register and DS with words from memory

Syntax – LDS register, memory address of first word
Example: LDS BX, [4326] ; copy the contents of the memory at 4326H
in DS to BL, contents of the 4327H to BH.

 LES Instruction - Load register and ES with words from memory

Syntax – LES register, memory address of first word
S.KARTHICK., AP/ECE 45
 1.DATA TRANSFER INSTRUCTIONS
FLAG TRANSFER INSTRUCTION

 LAHF Instruction - Load Register AH From Flags

copies the value of SF, ZF, AF, PF, and CF, into bits of 7, 6, 4, 2, 0 respectively of
AH register.
 SAHF instruction - Store AH Register into FLAGS
SAHF instruction transfers the bits 0-7 of AH of SF, ZF, AF, PF, and CF, into the
Flag register.
 PUSHF Instruction - Push flag register on the stack
This instruction decrements the SP by 2 and copies the word in flag register
to the memory location pointed by SP.
 POPF Instruction - Pop word from top of stack to flag – register.
S.KARTHICK., AP/ECE 46
 2.ARITHMETIC INSTRUCTIONS

ADDITION INSTRUCTIONS
 ADD Instruction - ADD destination, source
Example: ADD DX, BX
 ADC Instruction - Add with carry
Example: ADC CL,BL
 INC Instruction - Increment - INC destination
Example: INC BL
 AAA Instruction - ASCII Adjust after Addition
We can add two ASCII numbers directly and use AAA after addition
so as to get result directly in BCD. (Works with AL only)
 DAA Instruction - Decimal Adjust Accumulator

S.KARTHICK., AP/ECE 47
 2.ARITHMETIC INSTRUCTIONS
SUBTRACTION INSTRUCTION
 SUB Instruction - Subtract two numbers
Example: SUB CX, BX
 SBB Instruction - Subtract with borrow SBB destination, source
Example: SBB CX, BX
 DEC Instruction - Decrement destination register or memory.
 NEG Instruction - Form 2’s complement – Syntax: NEG destination
 CMP Instruction - Compare byte or word and sets the flag
Syntax: CMP destination, source.
 AAS Instruction - ASCII Adjust for Subtraction
 DAS Instruction - Decimal Adjust after Subtraction

S.KARTHICK., AP/ECE 48
 2.ARITHMETIC INSTRUCTIONS
MULTIPLICATION INSTRUCTION
 MUL Instruction - Multiply unsigned bytes or words
Syntax: MUL source Example: MUL BL
 IMUL Instruction - Multiply signed number
Syntax: IMUL source Example: IMUL BH
 AAM Instruction - ASCII adjust after Multiplication

DIVISION INSTRUCTION
 DIV Instruction - Unsigned divide Syntax: DIV source
Example: DIV BH ; AX / BH
; AX =Quotient & AH =Remainder.
 IDIV Instruction - Divide by signed byte or word Syntax: IDIV source
Example: IDIV BL ; Signed word in AX is divided by signed byte in BL
 AAD Instruction - ASCII adjust before Division
 CBW Instruction - Convert signed Byte to signed word
 CWD Instruction - Convert Signed Word to Signed Double word
S.KARTHICK., AP/ECE ( CBW and
49 CWD works only with AL,AX and DX registers.)
 3.LOGICAL INSTRUCTIONS
LOGICAL INSTRUCTION
 NOT Instruction - Invert each bit of operand
Ex: NOT BX ; Complement contents of BX register.
 AND Instruction - AND corresponding bits of two operands
Ex: AND BH, CL ; AND byte in CL with byte in BH ;result in BH
 OR Instruction - Logically OR corresponding of two operands
Ex: OR AH, CL ; CL is OR’ed with AH, result in AH.
 XOR Instruction - Exclusive XOR destination, source
Ex: XOR BX, CX ; Exclusive OR CX with BX and Result BX
 TEST Instruction – AND operand to update flags
Ex: TEST AL, BH ; AND BH with AL. no result is stored .
S.KARTHICK., AP/ECE Update 50
PF, SF, ZF
 3.LOGICAL INSTRUCTIONS

SHIFT INSTRUCTION
 SAL/SHL Instruction - Shift operand bits left, put zero in LSB(s)
Ex: ; CF = 0, BX = 11100101 11010011
SAL BX, 1 ; Shift BX contents by 1 bit position towards left
; CF = 1, BX = 11001011 10100110
 SHR Instruction - Shift operand bits right, put zero in MSB
Ex: ; SI = 10010011 10101101 , CF = 0
SHR SI, 1 ; Result: SI = 01001001 11010110 and CF = 1
 SAR Instruction - Shift operand bits right, new MSB = old MSB
Ex: ; AL = 00011101 = +29 decimal, CF = 0
SAR AL, 1 ; Shift signed byte in AL towards right
; AL = 00001110 = +14 decimal, CF = 1

S.KARTHICK., AP/ECE 51
 3.LOGICAL INSTRUCTIONS
ROTATE INSTRUCTION
 ROL Instruction - Rotate all bits of operand left, MSB to LSB
Ex: ;CF =0, BX = 10111011 01110101
ROL BX, 1 ;Result: CF =1, BX = 01110110 11101011
 ROR Instruction - Rotate all bits of operand right, LSB to MSB
Ex: ;CF =0, BX = 00111011 01110101
ROR BX, 1 ;Result: CF =1, BX = 10011101 10111010
 RCL Instruction - Rotate operand around to the left through CF
Ex: ;CF=0, BH = 10110011
RCL BH, 1 ;Result : BH =01100110, CF = 1
 RCR Instruction - Rotate operand around to the right through CF
Ex: ;CF = 1, BL = 00111000
RCR BL, 1 ;Result: BL = 10011100, CF =0
S.KARTHICK., AP/ECE 52
 4.CONTROL INSTRUCTIONS

UNCONDITIONAL TRANSFER INSTRUCTIONS

 CALL – call a procedure

 RET – return execution from procedure

 JMP – unconditional jump to specified destination

S.KARTHICK., AP/ECE 53
 4.CONTROL INSTRUCTIONS
CONDITIONAL TRANSFER INSTRUCTIONS
 JA/JNBE - Jump if above/Jump if not below or not equal
 JAE/JNB - jump if above or equal/Jump if not below
 JB/JNAE - jump if below/jump if not above or not equal
 JBE/JNA - jump if below or equal/jump if not above
 JC – jump if carry
 JE/JZ – jump if equal/jump if zero
 JG/JNLE – jump if greater/jump if not less or not equal
 JGE/JNL - jump if greater or equal/jump if not less than
 JL/JNGE- jump if less/jump if not greater or not equal
Cont…
S.KARTHICK., AP/ECE 54
 4.CONTROL INSTRUCTIONS
Cont…

CONDITIONAL TRANSFER INSTRUCTIONS

 JLE/JNG - jump if less or equal/jump if not greater
 JNC – jump if no carry
 JNE/JNZ - jump if not equal/jump if not zero
 JNO – jump if no overflow
 JNP/JPO - jump if no parity/jump if parity odd
 JNS – jump if no signed
 JO- jump if overflow
 JP/JPE - jump if parity/jump if parity even
 JS- jump if sign
S.KARTHICK., AP/ECE 55
 4.CONTROL INSTRUCTIONS

ITERATION CONTROL INSTRUCTIONS

 LOOP – decresae CX, jump to label if CX not equal to 0. Count is

loaded in CX register
 LOOPE/LOOPZ – decresae CX, jump to label if CX equal/decresae CX,
jump to label if CX not zero.
 LOOPNE/LOOPNZ - decresae CX, jump to label if CX not
equal/decresae CX, jump to label if CX not zero.
 JCXZ – jump if CX is zero.

S.KARTHICK., AP/ECE 56
 5.PROCESSOR CONTROL INSTRUCTIONS
 These instructions are used to change the process of the Microprocessor.

FLAG SET/CLEAR EXTERNAL HARDWARE

INSTRUCTIONS SYNCHRONIZATION INSTRUCTIONS

 STC - set carry flag  HLT - halt the system

 CLC - clear carry flag  WAIT - idle condition

 CMC - complement carry flag  ESC - When 8086 fetches an ESC instruction,

 STD - set direction flag the coprocessor decodes the instruction and
carries out the action specified by the 6 bit
 CLD - clear direction flag
code. In case of 8086 it treats ESC instruction
 STI - set interrupt enable flag
as an NOP. The coprocessor treats all of the
 CLI- clear interrupt enable
8086 instruction as an NOP except ESC.
flag  LOCK - bus lock signal
 NOP - no operation
S.KARTHICK., AP/ECE 57
 6.STRING CONTROL INSTRUCTIONS
• The string instructions function easily on blocks of memory. help for easy
program writing and execution. They can speed up the manipulating code.

 REP/REPE/REPZ/REPNE/REPNZ - Repeat String instruction until

specified condition exist
 MOVS/MOVSB/MOVSW - Move string byte or string word
Syntax: MOVS destination, source
 COMPS/COMPSB/COMPSW – compare string
 SCAS/SCASB/SCASW – Scan string byte or a string word.
 LODS/LODSB/LODSW - This instruction copies a byte from a string
location pointed to by SI to AL or a word from a string location pointed to
by SI to AX. If DF is cleared to 0, SI will automatically incremented to point
to the next element of string.
 STOS/STOSB/STOSW- Store byte or word in string.
S.KARTHICK., AP/ECE 58
 7.INTERRUPT CONTROL INSTRUCTIONS

 INT Interrupt type

 INTO Interrupt on overflow
 IRET Interrupt return

S.KARTHICK., AP/ECE 59
 ASSEMBLY
LANGUAGE
PROGRAMMIN
G

S.KARTHICK., AP/ECE 60
 PROCEDURES
&
MACROS

S.KARTHICK., AP/ECE 61
 PROCEDURES

 Set of code that performs a specific task is called

PROCEDURE
 The branch to procedure is known as CALL and the
corresponding branch back is known as RETURN.
 When a procedure is nested each return is made to the
corresponding calling procedure.
 Need for a stack and time required to call the procedure
and return to the calling program is the main
disadvantage

S.KARTHICK., AP/ECE 62
 PROCEDURES

Multiple Call

Nested Call

S.KARTHICK., AP/ECE 63
 MACROS
 MACRO is a group of instructions given with a name
 Each time we call the macro in our program, the assembler will
insert the defined group of instructions in place of the call
 Macro call is like a short hand expression which tells the
assembler “every time you see a macro name in the program,
replace it with the group of instructions defined as that macro at
the start of the program”
 Using a macro reduces the time involved in calling and returning
from a procedure
 More memory taken is the disadvantage

S.KARTHICK., AP/ECE 64
 COMPARISION OF PROCEDURE
&MACROS
PROCEDURE
 Accessed by CALL and RET mechanism during program execution
 Machine code for instruction put in memory only once
 Parameters passed in register memory location or stack
 Length of machine code is less
 It does a specific task and return value
MACROS
 Accessed during assembly with the name given to MACRO when
defined
 Machine code generated for instruction each time called
 Parameters passed as part of statement which calls macro
 Length of the machine code is more
 It just substitute the group of statements and does not return
S.KARTHICK., AP/ECE 65
value
 INTERRUPTS & ISR

 Interrupt is to break the sequence of operation while CPU is

executing the program
 Diverting the execution to some other program is called ISR
 After executing ISR the control will back to the main program
 Two types of interrupts
1.External Interrupt:
generated outside the processor Ex: keyboard interrupt
2. Internal Interrupt:
generated internally by the processor circuit or by execution of
interrupt instruction Ex: Overflow interrupt, interrupt due to INT
instruction

S.KARTHICK., AP/ECE 66
S.KARTHICK., AP/ECE 67