Computer

Organization
Course Topics
1. Chapter 1: Basic Structures of Computers: Functional Units, Operational concepts, Bus
structures, Software, Performance, Computer Architecture vs Computer Organization
2. Chapter 2: Machine Instructions and Programs: Memory location and addresses, Big-
Module I endian and Little-endian representation, Memory Operations, Instructions and
instruction sequencing, Addressing modes, Assembly Language, Basic Input / Output
operations, subroutine, additional instructions

3. Chapter 6: Arithmetic: Addition and subtraction of signed Numbers, Design of Fast

Adders, Multiplication of positive Numbers, Signed-operand multiplication, Fast
Module II multiplication, Integer Division, Floating-point Numbers (IEEE754 s. . .) and operations.

4. Chapter 5: The Memory System: Basic Concepts, cache Memory, Cache memory
mapping policies, Cache updating schemes, performance consideration, Virtual
Memories, Paging and Page replacement policies, Memory Management requirement,
Module III secondary storage.
5. Chapter 7: Basic Processing Units: Fundamental concepts, Execution of complete
Instructions, Multi bus organization, Hardwired control, Micro programmed control,
RISC vs CISC architecture
 Addition and subtraction of
signed numbers
• Suppose we want to add
two numbers X and Y.
• The following figure shows
the logic truth table for the
sum and carry-out functions
for adding xi and yi.
• Let ci represents the carry in
the ith stage which is the
carry out of (i1)th stage.
Addition and subtraction of
signed numbers
• Suppose we need to develop the algorithm for addition and subtraction of data
represented in signed-magnitude representation.
• Let the magnitude of the two numbers to be added (or subtracted) are A and B.
• When the signed numbers are added or subtracted, we find the following eight
different conditions to be considered:
 Addition and subtraction of
signed numbers
• The logic expression of
si can be implemented
by a 3-input XOR gate.
• The carry-out function
ci+1 is implemented with
a two-level AND-OR
logic circuit.
• We can use a complete
circuit for a single stage
addition, called a full
adder (FA).
 Addition and subtraction of
signed numbers
• The first figure shows a cascaded
connection of n full adder blocks
which can be used to add two n-bit
numbers.
• Since the carry must propagate or
ripple, through this cascade, the
configuration is called an n-bit
ripple-carry adder.
• The second figure shows the
interconnection of k n-bit adders to
form an adder capable of handling
input number that is kn bit long.
 Logic Circuit for Addition & Subtraction
• The logic circuit network perform either
addition or subtraction based on the value
applied to add / sub input control line.
• This line is set to 0 for addition, making the
Y vector unchanged to one of the adder
input along with a carry in signal c0 of 0.
• When add / sub control is set to 1, the Y
vector is 1’s complemented by the XOR
gate, and c0 is set to 1 to compute the 2’s
complement of Y.
• An XOR gate can be added to detect the
overflow condition cncn1.
 Addition and Subtraction Logic
Unit
• The n-bit adder can be used to add 2’s complement numbers X and Y where xn1
and yn1 are the sign bits.
• Overflow can only occurs when the signs of the two operands are the same. In
this case, overflow occurs if the sign of the result is different. To detect the
overflow a circuit can be added to the n-bit adder by implementing the logic
expression:

• Also overflow occurs when the carry bits cn and cn1 are different. A simpler
alternative circuit for detecting overflow can be obtained by implementing the
expression cn cn1with an XOR gate.
• For the subtraction operation XY on 2’s complement of X and Y, we perform 2’s
complement of Y and add it to X.
Design of Fast Adder
• Delay is calculated by adding up the number of logic-gate delays along
the longest signal propagation path through the network.
• In the n-bit ripple-carry adder:
• cn1 is available in 2(n1) gate delays. [For each pair of xi and yi one delay for 3
AND gates and one for OR gate]
• sn1 is available in = number of gate delays of cn1+ 1 [For XOR gate] = 2(n1) +1
= 2n  1
• cn is available in 2n gate delays.
• Therefore to implement addition/subtraction unit using ripple-carry
adder:
• All sum bits are available in 2n gate delays. [2n 1 gate delays for availability of
sn1 + 1 gate delay for XOR gate on Y input]
• We need some approaches to reduce the delay.
Carry-Lookahead Addition
• The logic expression for sum (si) and carry (ci) of stage i are:

where Gi= xi yi(Generate function)

andPi= xi + yi(Propagate function)
• If Gi = 1, then ci+1 = 1, independent of the input carry ci.
• The propagate function means that and input carry will
produce an output carry when either xi or yi is 1.
• All Gi and Pi functions can be formed independently and in
parallel in one logic gate delay after the X and Y vectors are
applied to the inputs of an n-bit adder.
 Carry-Lookahead Addition
• Each bit stage contains:
• An AND gate to form Gi
• An OR gate to form Pi
• XOR gate to form Si
• We can write Pi = xi  yi instead of Pi = xi + yi as
it satisfies all cases except when xi = yi = 1.
However, in this case Gi =1 and it does not
matter whether Pi is 0 or 1.
• Therefore, we can use a cascade of two 2-
input XOR gates in place of one 3 input XOR
gate to get the desired outputs in each bit
stage.
Carry-Lookahead Addition
• Expanding ci in terms of i1 subscripted variables and
substituting into ci+1 expression we have:

• So all carries can be obtained in three delays after the

input signals X, Y and c0 are applied because:
• One gate delay to produce all Pi and Gi signals.
• Two gate delays in AND-OR circuit for ci+1.
• All sum bits can be obtained after one XOR gate delay.
 Example: Design of a 4-bit adder
• Using carry lookahead adder:
• Number of gate delays for
obtaining all carry bits = 3
• Number of gate delays for
obtaining all sum bits = 4
• Using 4-bit ripple-carry adder:
• Number of gate delays for
obtaining s3 = 7
• Number of gate delays for
obtaining c4 = 8
Performing n-bit addition in 4 gate delays independent of n is good
only theoretically because of fan-in constraints.

Last AND gate and OR gate require a fan-in of (n+1) for a n-bit adder.
For a 4-bit adder (n=4) fan-in of 5 is required.
Practical limit for most gates.
 Problem
Find the number of delays for obtaining
c16 in the following 16-bit carry-lookahead
adder built from four 4-bit adders.
Ans:
• Number of gate delays for obtaining c4 =
3
• Number of gate delays for obtaining c8 =
3 + 2 (Since Gi and Pi are already
calculated)
• Number of gate delays for obtaining c16
=3+2+2+2=9
• Number of gate delays for obtaining all
sum bits = 9 + 1 = 10
Addition (Subtraction)
Algorithm
1. When the signs of A and B are identical, add the two
magnitudes and attach the sign of A to the result.
2. When the signs of A and B are different, compare the
magnitudes and subtract the smaller number from the
larger.
a) Choose the sign of the result to be the same as A if A > B or the
complement of the sign of A if A < B.
3. If the two magnitudes are equal, subtract B from A and
make the sign of the result positive.
 Multiplication of Positive Numbers
• The product of two n-digit numbers
can be accommodated in 2n digit.
• During multiplication if the multiplier
bit is 1, the multiplicand is entered in
the appropriate position to be added
to the partial product.
• If the multiplier bit is 0, then 0s are
entered.
Block diagram of the hardware to
implement Addition (Subtraction)
• The hardware consists of the following items:
• Register A and B: Contains the two numbers
• Flip-flop As and Bs: Contains the sign of A and B respectively.
• Flip-Flop E: Stores the output carry which is used to determine
the relative magnitude of the two numbers.
• Add-overflow flip-flop AVF: Holds the overflow bit when A and B
are added.
• Parallel Adder: Used for the addition of A plus B
• Complementer: Takes the input as B and produces the output B
or complement of B depending on the mode control M.
• Subtraction is performed by adding 2’s complement of B to A.
• The signal M is also applied to the input carry of the adder.
• When M = 0, the output of B is transferred to the adder, the
input carry is 0 and the output of the adder is A + B
• When M = 1, 1’s complement of B is transferred to the adder,
the input carry is 1 and the output of the adder is A + + 1 which
is A  B.
Algorithm for Addition (Subtraction)
Combinational, two-dimensional
logic array for Multiplication
Multiplication of Positive Numbers
• The main component in each cell is a full adder.
• The AND gate in each cell determines whether a multiplicand bit mj, is
added to the incoming partial-product bit, based on the value of the
multiplier bit qi.
• Each row i, where 0  i  3,
• adds the shifted multiplicand to the incoming partial produce, PP i to generate
the outgoing partial product PP(i+1) if qi = 1.
• Pass PPi vertically downward (without any change), if qi = 0.
• PP0 is all 0s and PP4 is the desired product.
• The multiplicand is shifted left one position per row by the diagonal
path.
• Limitation: The above combinatorial multiplier uses many gates for multiplying
 Multiplication Hardware for Signed-Magnitude Data
• Q: Stores the multiplier
• Qn: the rightmost flip-flop in register
• Qs: Stores the sign of multiplier Q, hold the bit of the multiplier which
• B: Stores the multiplicand will be inspected next.
• Bs: Stores the sign of multiplicand
• SC (sequence counter): Stores number
of bits in the multiplier. It is
decremented by 1. The process
continues until SC is non zero.
• Sum of A and B forms a partial
product which is transferred to EA
register. Initially EA stores zero.
• Both partial product and multiplier
are shifted to the right. 0 is shifted
 Flowchart for Multiplication
• First the signs of the multiplicand (Bs) and the multiplier
(Qs) are compared and both A and Q are set to
correspond to the sign of the product. A and E are
cleared and SC is initialized.
• If the lower order bit, Qn is 1:
• Multiplicand B is added to the partial product A.
• Register EAQ is shifted one position to the right to form
the new partial product.
• SC is decremented by 1.
• If it becomes 0, the process is stopped, else the process
is repeated and new partial product is formed.
• Final product is available in both A and Q.
Hardware arrangement of
sequential circuit
 Multiplication of Positive Numbers
• The circuit uses a single n-bit adder n times to implement the addition performed
by the n rows of ripple-carry adder.
• Register A and Q combined hold PPi.
• The multiplier bit qi generates the signal Add/NoAdd which controls the addition
of the multiplicand, m, to PPi to generate PP(i+1).
• The product is computed in n cycles.
• The partial product grows in length by one bit per cycle from the initial vector
PP0, of n zeros.
• The carry-out from the adder is stored in flip-flop C.
• At the beginning the multiplier is loaded into register Q, multiplicand into register
M, and C and A are cleared to 0.
• At the end of each cycle, C, A and Q are shifted one bit position to allow for
Example
Limitation: Multiplication
takes much more time to
execute than addition because
of sequential hardware
structure.
 Signed Operand Multiplication
• Let Multiplier: 11
Multiplicand (-13).
• To add a negative multiplicand to a
partial product, we must extend the
sign-bit value of the multiplicand to
the left as far as the product will
extend.
• The hardware used for multiplication
of two positive numbers can be used
for this purpose if it provides sign
extension of the partial product.
• If the multiplier is negative, find the
2’s-complement of both the multiplier
and multiplicand and proceed as in
the case of positive multiplier.
Booth Algorithm
• This algorithm can be used for multiplication for both
negative and positive multipliers.
• It generates a 2n-bit product and treats both positive
and negative 2’s-complement n-bit operands
uniformly.
• The mechanism of operation is that strings of 0s in the
multiplier requires no addition but shifting.
Booth Scheme
• Suppose we have a multiplier 0011110 (30). To find the product with a
multiplicand, M we have to add four appropriately shifted versions of M in the
standard method.
• We can reduce the number of operations by regarding this multiplier as the
difference between two numbers:
0 1 0 0 0 0 0 (32)
 0 0 0 0 0 1 0 (2)
---------------------------------------------
0 0 1 1 1 1 0 (30)
• Which means the product can be generated by adding 2 5 times M to the 2’s-
complement of 21 times M.
• So we recode the multiplier 0011110 (30) as 0 +1 0 0 0 1 0. This transformation is
called as skipping over 1s.
• Booth Scheme:
 1 times the shifted multiplicand is selected when moving from 0 to 1.
 +1 times the shifted multiplicand is selected when moving from 1 to 0.
Booth algorithm vs the normal
multiplication scheme