Operating Systems

CSE 231 (Section B)

Instructor: Sambuddho Chakravarty
(Semester: Monsoon 2022)
Week 1: Aug 29 – Sept 2
Introduction
• What is a Computer ?

• What is an Operating System?

• Why does a computer need an Operating System ?

Class Objective: What CSE 231 Would Teach You

• Introductory course to operating systems

• The basics – blah blah blah.

• Processes and their siblings.
• Process synchronization.
• Threads and thread synchronization.
• Issues with processes – deadlocks and deadlock detection
• Memory Management.
• I/O Management.
• Storage Management.
• Virtualization
What you should expect at the end of this class
• Pretty conversant in C programming. NO fear of pointers, debuggers, assemblers (A C
ninja – as per the TA who taught the refresher module)
• Pretty conversant with Linux internals.
• Compiling kernel.
• Mucking around the kernel
• Strong understanding of processes, threads and the likes.
• Good understanding of memory management as it happens inside the OS.
• Basics of storage management – aka filesystems and how data is stored on disks.
• How a program (aka binary) runs!
• How a computer boots up! – (ps: get ready for an extra credit assignment)
Grade Distribution and Administrativia
• Grading:
• 20% Mid-term exam
• 25% Final exam
• 55% Assignments
• 10% Bonus
• Textbook:
• Operating Systems Concepts: A. Silberschatz, P. B. Galvin and G. Gagne, Ninth Edn.,
2014, Wiley India Pvt Ltd., ISBN: 973-1-118-06333-0.

• Linux Systems Programming, R. Love, Second Edn, 2013, O'Rielly Media, ISBN-13:
978-1449339531.
• Linux Kernel Development, R. Love, Third Edn., ISBN-13: 978-0672329463.
• Contact email: [email protected]
• Office Hours: Fri. 1500hrs – 1600hrs (Or by appointment).
• TA office hours: TBA
Exactly What is a Computer
Most Basic Computer aka Turing Machine
• Proposed by Alan Turing (circa. 1936)
• Model consists of infinite tape divided into cells which contain input
symbols.
• Head reads the top of the symbol and changes the internal state of
the machine when the symbol is something that is not unexpected.
• The machine thus moves to the next state until it reaches a terminal
state which makes that the input is invalid…
Evolution of Computers
• Abacus – Chinese, Roman and Russian – ancient form of calculator.
• Relies on a series of beads and their movements to perform calculations.
Babbage Analytical Machine
• Mechanical form of the Abacus used for calculating polynomial
functions.
• Separation of storage and processing…
 20th Century – Enigma Machine
- Designed by Arthur Scherbius (Axis Germany) towards end of
WW1 to send encrypted messages

Used during WW2

Inside the Enigma

Input

Output
(via
Glowlamps)
 Collosus Machine
- Designed by Britain (Allied) to break encrypted messages of
enigma...
Post WW2 – Electronic Numerical Integrator and Computer (ENIAC)

-Designed by Univ of Pennsylvania, in Feb 15, 1946.

-General purpose computer designed based on Turing Machine principle

Operation time samples: 10-digit num x 10-digit num took 2800 µsec,

https://www.youtube.com/watch?v=rO2SScF6rrM
Post WW2 – General Purpose Computers Post 1960s

-Greatest invention for computing world – Transistor – improvement in size and

speed of operation – lower power consumption

- Majority of general purpose mainframes evolved in this era – the PDP

(Programmed Data Processors) – PDP 1 .. PDP 16
- Different processing capabilities

- UNIVAC (UNIVersal Automatic Computer) – Mid 1960s. Used as general

purpose mainframes – quite ahead of their times 36-bit word size (modern
Intel x86_64 – 64bit word size).

- Big challenge in increasing word size in computers…

Era of IC based design 1970s
- Jack Kilby (Noble laureate), father of IC semi-conductors.
- Integrated circuits – semi-conductors were ``grown’’ over silicon substrates.
Faster than ordinary BJTs.
- Many ``fast’’ transistors could be integrated into a single physical ``chip’’
- Beginning of VLSI age..
- Computer chips become even smaller, faster and consume lesser power
(overall faster computation speeds).
- ICs had combinations of transistors arranged to form series of logic gates – the
building blocks of modern computers – can be used for all kinds of operations
but the classical ones are for storage (aka memory).
- More advanced – microcontrollers and microprocessors.
Intel x86 Processors
• Totally dominate laptop/desktop/server market

• Evolutionary design
• Backwards compatible up until 8086, introduced in 1978
• Added more features as time goes on

• Complex instruction set computer (CISC)

• Many different instructions with many different formats
• But, only small subset encountered with Linux programs
• Hard to match performance of Reduced Instruction Set Computers (RISC)
• But, Intel has done just that!
• In terms of speed. Less so for low power.
Era of Digital Computers
- ICs used to design a microcontrollers and microprocessors.
- Main parts – registers, ALU, control unit, PC, I/O buffers, address bus
and data bus
Intel – 1970s and Beyond
-First microprocessor by Intel – 4044 (4-bit microprocessor) – release date: Nov 15, 1971
-The first commercial product to use a microprocessor was the Busicom calculator 141-PF.
- The 4004 was also used in the first microprocessor-controlled pinball game, a prototype produced
by Dave Nutting Associates for Bally in 1974
Intel x86 Evolution: Milestones
Name Date Transistors MHz
• 8086 1978 29K 5-10
• First 16-bit Intel processor. Basis for IBM PC & DOS
• 1MB address space
• 386 1985 275K 16-33
• First 32 bit Intel processor , referred to as IA32
• Added “flat addressing”, capable of running Unix
• Pentium 4F 2004 125M 2800-3800
• First 64-bit Intel processor, referred to as x86-64
• Core 2 2006 291M 1060-3500
• First multi-core Intel processor
• Core i7 2008 731M 1700-3900
• Four cores
Rise of the Desktops
- Xerox Alto (by Xerox PARC) developed in 1973, the first PC ever designed – used, mouse keyboard
etc.
- Closely correlated to the rise of microprocessors.
- Series of systems by IBM using IBM PALM processor, running
and interpretive language (BASIC).
- Altair 8800 – spawned several computer manufacturers to start to produce
personal computers – Processor : Zilog Z80 or Intel 8085, running CP/M-80
operating systems.

Home computing:
- IBM PC – Intel 8088 microprocessor
- 8 bit microprocessor, booted using floppy disks…
- 5MB HDDs with 640KB of RAM
- PC-DOS operating system.
- Apple Lisa and Macintosh – GUI based interface.
- Motorola 68000 microprocessor with about 128 KB of RAM (upgraded to 512 KB of RAM)
- Newer faster processors evolved post 1990s – Intel 80386/486/Pentium processor – 32-bit
- RAM sizes increased to 16MB 🡪 32 MB 🡪 64 MB
Cellular Communication Married to Computers – Smart Phones

-A different revolution was brewing since the 1970s… (??)

-ARPANET – 1969 – connection established
- First message transmitted – “Login”

- Wireless communication has been there since 19th century.

- Telephony (1876, Bell)
- Wireless telephony – Cellular communication – 1970s.

- Computers
Age of wearables and implantables…
- Microprocessors are now fitted into wearable devices (e.g. watches)
- Watches + smartphones = smart-watches
- Temperature and vital statistics monitoring
- Implantables….
- Often specific purpose (not so generic…)
Components of Computer System
Layered Architecture
User Programs
P6 P5 P4 P3 P2 P1

File System I/O Mem

Task
Management Management Management
Scheduler Kernel
Unit (MMU)

Device Drivers and Firmware

Interrupt handlers

Hardware
Interrupts and Interrupt Handling (Heart of the OS)
• Interrupts:
- ALL devices send a signal to the CPU whenever they require to ``communicate”
with the CPU.
- CPU is switched to Interrupt Handler program (part of the OS/supplied
externally).
- The Interrupt Handler ``saves’’ various information with respect to the running
program and it is jumped to a fixed location in memory – the IH routine.
- The IH routing – binaries (programs) that involve instructions and commands to
communicate with the device.
- The IH routine may either handle the device interrupt and jump back to executing
the saved task
- In case of task scheduler timer clock interrupt the CPU scheduler handles the
tasks/process and handles it.
Processes/Tasks/Threads
• Running program binary
• The OS loads up the binary
• Runtime linker supplies the necessary address bindings – the address of memory
where local variables are stored – MMU Used.
• Saves ``state’’ of the running program in Process Control Block (PCB) for each
process.
• Loads the ``state’’ of the new program and starts executing it.
• Every so often a timer interrupt ``interrupts’’ the CPU to switch the
process/task.
• Timer interrupt handler 🡪 invokes 🡪 process scheduler.
Multi-Processing (Why you exactly need an OS)
• Multiple processes running in tandem giving the illusion that multiple
programs are running.
• Process executions synchronized with the help of the process/task
scheduler.
• Scheduler is invoked periodically by the timer interrupt handler which saves the
state of a task and loads up another.
• Gives illusion of multi-processing.
• Task state –
• Every running program has a task / process state which includes:
• Process ID (PID)
• CPU registers
• Memory addresses for code, stack, data, heap and BSS
• I/O operations in progress.
• Interrupts that are unhandled.
• Previous process running and next process that needs to be run (in the process queue).
Processes
P6 P5 P4 P3 P2 P1

Application Layer

Process Scheduler Kernel

Functions

Real Time
Clock

Timer
Interrupt
Handler
Intel’s 64-Bit
• Intel Attempted Radical Shift from IA32 to IA64
• Totally different architecture (Itanium)
• Executes IA32 code only as legacy
• Performance disappointing
• AMD Stepped in with Evolutionary Solution
• x86-64 (now called “AMD64”)
• Intel Felt Obligated to Focus on IA64
• Hard to admit mistake or that AMD is better
• 2004: Intel Announces EM64T extension to IA32
• Extended Memory 64-bit Technology
• Almost identical to x86-64!
• All but low-end x86 processors support x86-64
• But, lots of code still runs in 32-bit mode
Assembly Programmer’s View
CPU Memory
Addresses
Registers
Data Code
PC Data
Condition Instructions Stack
Codes

Programmer-Visible State
• PC: Program counter • Memory
• Address of next instruction • Byte addressable array
• Called “EIP” (IA32) or “RIP” (x86-64) • Code and user data
• Register file • Stack to support procedures
• Heavily used program data
• Condition codes
• Store status information about most
recent arithmetic operation
• Used for conditional branching
What are registers?
1. Computer main memory latency : 80 nanoseconds.
2. A 3.3 GHz CPU takes ~ 0.3 nsecs per cycle memory latency is about 240
cycles.
3. The Core i7 has 3 levels of cache with different latencies.
I. Level 3 ~ 48 nsec (~ 150 cycles).
II. Level 2 ~ 10 nsec (~ 39 cycles).
III. Level 1 ~ 4 nsec (~12 cycles).

Registers = ultra fast memory.

Some register-register instructions require only 1 cycle.
Turning C into Object Code
• Code in files p1.c p2.c
• Compile with command: gcc –O1 p1.c p2.c -o p
• Use basic optimizations (-O1)
• Put resulting binary in file p
text C program (p1.c p2.c)

Compiler (gcc -S)

text Asm program (p1.s p2.s)

Assembler (gcc or as)

binary Object program (p1.o p2.o) Static libraries
(.a)
Linker (gcc or ld)
binary Executable program (p)
Compiling Into Assembly
C Code Generated IA32 Assembly
int sum(int x, int y) sum:
{ pushl %ebp
int t = x+y; movl %esp,%ebp
return t; movl 12(%ebp),%eax
} addl 8(%ebp),%eax
popl %ebp
ret

Obtain with command

/usr/local/bin/gcc –O1 -S code.c
Produces file code.s
Assembly Characteristics: Data Types
• “Integer” data of 1, 2, or 4 bytes
• Data values
• Addresses (untyped pointers)

• Floating point data of 4, 8, or 10 bytes

• No aggregate types such as arrays or structures

• Just contiguously allocated bytes in memory
Assembly Characteristics: Operations
• Perform arithmetic function on register or memory data

• Transfer data between memory and register

• Load data from memory into register
• Store register data into memory

• Transfer control
• Unconditional jumps to/from procedures
• Conditional branches
Object Code • Assembler
Code for sum • Translates .s into .o
0x401040 <sum>: • Binary encoding of each instruction
0x55
• Nearly-complete image of executable
0x89 code
0xe5 • Missing linkages between code in
0x8b
different files
0x45
0x0c • Linker
0x03
0x45 • Resolves references between files
0x08 • Total of 11 bytes • Combines with static run-time
0x5d
• Each instruction libraries
0xc3
1, 2, or 3 bytes • E.g., code for malloc, printf
• Starts at address • Some libraries are dynamically linked
0x401040 • Linking occurs when program begins
execution
Machine Instruction Example
• C Code
int t = x+y;
• Add two signed integers
• Assembly
addl 8(%ebp),%eax • Add 2 4-byte integers
• “Long” words in GCC parlance
Similar to expression: • Same instruction whether signed
x += y or unsigned
More precisely: • Operands:
int eax; x: Register %eax
int *ebp; y: Memory M[%ebp+8]
eax += ebp[2] t: Register %eax
• Return function value in %eax

0x80483ca: 03 45 08
• Object Code
• 3-byte instruction
• Stored at address
0x80483ca
Disassembling Object Code
Disassembled
080483c4 <sum>:
80483c4: 55 push %ebp
80483c5: 89 e5 mov %esp,%ebp
80483c7: 8b 45 0c mov 0xc(%ebp),%eax
80483ca: 03 45 08 add 0x8(%ebp),%eax
80483cd: 5d pop %ebp
80483ce: c3 ret

• Disassembler
objdump -d p
• Useful tool for examining object code
• Analyzes bit pattern of series of instructions
• Produces approximate rendition of assembly code
• Can be run on either a.out (complete executable) or .o file
Alternate Disassembly
Object Disassembled
0x401040:
0x55 Dump of assembler code for function sum:
0x89 0x080483c4 <sum+0>: push %ebp
0xe5 0x080483c5 <sum+1>: mov %esp,%ebp
0x8b 0x080483c7 <sum+3>: mov 0xc(%ebp),%eax
0x45 0x080483ca <sum+6>: add 0x8(%ebp),%eax
0x0c 0x080483cd <sum+9>: pop %ebp
0x03 0x080483ce <sum+10>: ret
0x45
0x08
0x5d • Within gdb Debugger
0xc3 gdb p
disassemble sum
• Disassemble procedure
x/11xb sum
• Examine the 11 bytes starting at sum
 What Can be Disassembled?
% objdump -d WINWORD.EXE

WINWORD.EXE: file format pei-i386

No symbols in "WINWORD.EXE".
Disassembly of section .text:

30001000 <.text>:
30001000: 55 push %ebp
30001001: 8b ec mov %esp,%ebp
30001003: 6a ff push $0xffffffff
30001005: 68 90 10 00 30 push $0x30001090
3000100a: 68 91 dc 4c 30 push $0x304cdc91

• Anything that can be interpreted as executable code

• Disassembler examines bytes and reconstructs assembly
source
 Origin
Integer Registers (IA32) (mostly obsolete)

%eax %ax %ah %al accumulate

general purpose %ecx %cx %ch %cl counter

%edx %dx %dh %dl data

%ebx %bx %bh %bl base

source
%esi %si index

destination
%edi %di index
stack
%esp %sp
pointer
base
%ebp %bp
pointer

16-bit virtual registers

(backwards compatibility)
Moving Data: IA32 %eax

• Moving Data %ecx

movl Source, Dest: %edx

• Operand Types %ebx

• Immediate: Constant integer data %esi

• Example: $0x400, $-533 %edi
• Like C constant, but prefixed with ‘$’
• Encoded with 1, 2, or 4 bytes %esp
• Register: One of 8 integer registers %ebp
• Example: %eax, %edx
• But %esp and %ebp reserved for special use
• Others have special uses for particular instructions
• Memory: 4 consecutive bytes of memory at address given by
register
• Simplest example: (%eax)
• Various other “address modes”
movl Operand Combinations

Source Dest Src,Dest C Analog

Reg movl $0x4,%eax temp = 0x4;

Imm
Mem movl $-147,(%eax) *p = -147;

Reg movl %eax,%edx temp2 = temp1;

movl Reg
Mem movl %eax,(%edx) *p = temp;

Mem Reg movl (%eax),%edx temp = *p;

Cannot do memory-memory transfer with a single instruction

 Simple Memory Addressing Modes

• Normal (R) Mem[Reg[R]]

• Register R specifies memory address
• Aha! Pointer dereferencing in C

movl (%ecx),%eax

• Displacement D(R) Mem[Reg[R]+D]

• Register R specifies start of memory region
• Constant displacement D specifies offset

movl 8(%ebp),%edx
Move with sign extend or zero extend
1. If you move a double word into a double word register, the upper half is zeroed out.
2. If you move a 32 bit immediate into a 64 bit register it is sign extended.
3. Load a smaller value from memory and fill the rest of the register with zeroes. Or sign
extend a small value from memory.

movsxb (%rax),%rbx /*move byte, sign extend*/

movzxs (%rsi),%rax /*move short, zero extend*/
movsxl (%rdi),%rcx /*move long, sign extend*/
 Using Simple Addressing Modes
swap:
pushl %ebp
void swap(int *xp, int *yp) Setup
movl %esp,%ebp
{
pushl %ebx
int t0 = *xp;
int t1 = *yp;
*xp = t1; movl 8(%ebp), %edx
*yp = t0; movl 12(%ebp), %ecx
} movl (%edx), %ebx Body
movl (%ecx), %eax
movl %eax, (%edx)
movl %ebx, (%ecx)

popl %ebx
popl %ebp Finish
ret
 Using Simple Addressing Modes
swap:
pushl %ebp
void swap(int *xp, int *yp) Set
movl %esp,%ebp Up
{
pushl %ebx
int t0 = *xp;
int t1 = *yp;
*xp = t1; movl 8(%ebp),
*yp = t0; %edx
} movl 12(%ebp), Body
%ecx
movl (%edx),
%ebx
movl (%ecx),
%eax
movl %eax, Finish
(%edx)
movl %ebx,
(%ecx)

popl %ebx
 Understanding Swap
•
•
void swap(int *xp, int *yp)
{
• Stack
Offset
int t0 = *xp; (in memory)
int t1 = *yp; 12 yp
*xp = t1; 8 xp
*yp = t0;
} 4 Rtn adr
0 Old %ebp %eb
-4 Old %ebx p
%esp
Register Value
movl 8(%ebp), %edx # edx = xp
%edx xp
movl 12(%ebp), %ecx # ecx =
%ecx yp
yp
%ebx t0 movl (%edx), %ebx # ebx = *xp
%eax t1 (t0)
movl (%ecx), %eax # eax = *yp
(t1)
movl %eax, (%edx) # *xp = t1
movl %ebx, (%ecx) # *yp = t0
 Address
Understanding Swap 123 0x124
456 0x120
0x11c
%eax
0x118
%edx Offset
0x114
%ecx yp 12 0x120 0x110
xp 8 0x124 0x10c
%ebx
4 Rtn adr 0x108
%esi
%eb 0 0x104
%edi p -4
0x100
%esp movl 8(%ebp), %edx # edx = xp
movl 12(%ebp), %ecx # ecx =
%ebp 0x104 yp
movl (%edx), %ebx # ebx = *xp
(t0)
movl (%ecx), %eax # eax = *yp
(t1)
movl %eax, (%edx) # *xp = t1
movl %ebx, (%ecx) # *yp = t0
 Address
Understanding Swap 123 0x124
456 0x120
0x11c
%eax 0x118
%edx 0x124 Offset
0x114
%ecx yp 12 0x120 0x110
xp 8 0x124 0x10c
%ebx
4 Rtn adr 0x108
%esi
%eb 0 0x104
%edi p -4
0x100
%esp
movl 8(%ebp), %edx # edx = xp
%ebp 0x104 movl 12(%ebp), %ecx# ecx = yp
movl (%edx), %ebx # ebx = *xp (t0)
movl (%ecx), %eax # eax = *yp (t1)
movl %eax, (%edx) # *xp = t1
movl %ebx, (%ecx) # *yp = t0
 Address
Understanding Swap 123 0x124
456 0x120
0x11c
%eax
0x118
%edx 0x124 Offset
0x114
%ecx 0x120 yp 12 0x120 0x110
xp 8 0x124 0x10c
%ebx
4 Rtn adr 0x108
%esi
%eb 0 0x104
%edi p -4
0x100
%esp
movl 8(%ebp), %edx # edx = xp
%ebp 0x104 movl 12(%ebp), %ecx# ecx = yp
movl (%edx), %ebx # ebx = *xp (t0)
movl (%ecx), %eax # eax = *yp (t1)
movl %eax, (%edx) # *xp = t1
movl %ebx, (%ecx) # *yp = t0
 Address
Understanding Swap 123 0x124
456 0x120
0x11c
%eax
%eax 0x118
%edx
%edx 0x124 Offset
0x114
%ecx
%ecx 0x120 yp 12 0x120 0x110
xp 8 0x124 0x10c
%ebx
%ebx 123
4 Rtn adr 0x108
%esi
%esi
%eb 0 0x104
%edi
%edi p -4
0x100
%esp
%esp
movl 8(%ebp), %edx # edx = xp
%ebp
%ebp 0x104 movl 12(%ebp), %ecx# ecx = yp
movl (%edx), %ebx # ebx = *xp (t0)
movl (%ecx), %eax # eax = *yp (t1)
movl %eax, (%edx) # *xp = t1
movl %ebx, (%ecx) # *yp = t0
 Address
Understanding Swap 123 0x124
456 0x120
0x11c
%eax 456 0x118
%edx 0x124 Offset
0x114
%ecx 0x120 yp 12 0x120 0x110
xp 8 0x124 0x10c
%ebx 123
4 Rtn adr 0x108
%esi
%ebp 0 0x104
%edi -4
0x100
%esp
movl 8(%ebp), %edx # edx = xp
%ebp 0x104 movl 12(%ebp), %ecx# ecx = yp
movl (%edx), %ebx # ebx = *xp (t0)
movl (%ecx), %eax # eax = *yp (t1)
movl %eax, (%edx) # *xp = t1
movl %ebx, (%ecx) # *yp = t0
 Address
Understanding Swap 456 0x124
456 0x120
0x11c
%eax
%eax 456
456 0x118
%edx
%edx 0x124 Offset
0x114
%ecx
%ecx 0x120 yp 12 0x120 0x110
xp 8 0x124 0x10c
%ebx
%ebx 123
4 Rtn adr 0x108
%esi
%esi
%ebp 0 0x104
%edi
%edi -4
0x100
%esp
%esp
movl 8(%ebp), %edx # edx = xp
%ebp 0x104 movl 12(%ebp), %ecx# ecx = yp
movl (%edx), %ebx # ebx = *xp (t0)
movl (%ecx), %eax # eax = *yp (t1)
movl %eax, (%edx) # *xp = t1
movl %ebx, (%ecx) # *yp = t0
 Address
Understanding Swap 456 0x124
123 0x120
0x11c
%eax 456 0x118
%edx 0x124 Offset
0x114
%ecx 0x120 yp 12 0x120 0x110
xp 8 0x124 0x10c
%ebx 123
%es 4 Rtn adr 0x108
i %ebp 0 0x104
%edi -4
0x100
%esp
movl 8(%ebp), %edx # edx = xp
%ebp 0x104 movl 12(%ebp), %ecx # ecx =
yp
movl (%edx), %ebx # ebx = *xp
(t0)
movl (%ecx), %eax # eax = *yp
(t1)
movl %eax, (%edx) # *xp = t1
Complete Memory Addressing Modes
• Most General Form
D(Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]+ D]
• D: Constant “displacement” 1, 2, or 4 bytes
• Rb: Base register: Any of 8 integer registers
• Ri: Index register: Any, except for %esp
• Unlikely you’d use %ebp, either
• S: Scale: 1, 2, 4, or 8 (why these numbers?)

• Special Cases
(Rb,Ri) Mem[Reg[Rb]+Reg[Ri]]
D(Rb,Ri) Mem[Reg[Rb]+Reg[Ri]+D]
(Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]]
Data Representations: IA32 + x86-64
• Sizes of C Objects (in Bytes)
C Data Type Generic 32-bit Intel IA32 x86-64
• unsigned 4 4 4
• int 4 4 4
• long int 4 4 8
• char 1 1 1
• short 2 2 2
• float 4 4 4
• double 8 8 8
• long double 8 10/12 10/16
• char * 4 4 8
• Or any other pointer
 64-bits)
32-bits
Registers
16-bits

rax eax ax ah al accumulator

rcx ecx cx ch cl accumulator

rdx edx dx dh dl accumulator

accumulator
rbx ebx bx bh bl
general purpose

accumulator
rsi esi si
rdi edi accumulator
di
rsp esp sp stack pointer

rbp ebp bp base / frame pointer

r8 r8d accumulator

r15 r15d accumulator

Instructions
• Long word l (4 Bytes) ↔ Quad word q (8 Bytes)

• New instructions:
• movl ➙ movq
• addl ➙ addq
• sall ➙ salq
• etc.

• 32-bit instructions that generate 32-bit results

• Set higher order bits of destination register to 0
• Example: addl
32-bit code for swap
swap:
pushl %ebp
void swap(int *xp, int *yp) Set
{
movl %esp,%ebp Up
int t0 = *xp; pushl %ebx
int t1 = *yp;
*xp = t1; movl 8(%ebp), %edx
*yp = t0; movl 12(%ebp), %ecx
} movl (%edx), %ebx Body
movl (%ecx), %eax
movl %eax, (%edx)
movl %ebx, (%ecx)

popl %ebx
popl %ebp Finish
ret
64-bit code for swap
swap: Set
void swap(int *xp, int *yp) Up
{
int t0 = *xp; movl (%rdi), %edx
int t1 = *yp; movl (%rsi), %eax Body
*xp = t1; movl %eax, (%rdi)
*yp = t0;
movl %edx, (%rsi)
}
Finish
ret
• Operands passed in registers (why useful?)
• First (xp) in %rdi, second (yp) in %rsi
• 64-bit pointers
• No stack operations required
• 32-bit data
• Data held in registers %eax and %edx
• movl operation
64-bit code for long int swap
swap_l:

void swap(long *xp, long *yp)

{ movq (%rdi), %rdx Set
long t0 = *xp; movq (%rsi), %rax Up
long t1 = *yp; movq %rax, (%rdi)
*xp = t1; movq %rdx, (%rsi)
*yp = t0; Body
} ret

• 64-bit data Finish

• Data held in registers %rax and %rdx
• movq operation
• “q” stands for quad-word
Calling conventions : X86
int callee(int, int, int); caller:
push ebp ; save old call frame
mov ebp, esp ; initialize new call frame
int caller(void) push 3
{ push 2
return callee(1, 2, 3) + 5; push 1
call callee ; call subroutine 'callee'
} add esp, 12 ; remove call arguments from frame
add eax, 5 ; modify subroutine result
mov esp, ebp ; most calling conventions dictate ebp be callee-
saved,
pop ebp ; restore old call frame
ret ; return
Calling conventions : X86_64
long myfunc(long a, long b, long c, long d,
long e, long f, long g, long h)
{
long xx = a * b * c * d * e * f * g * h;
long yy = a + b + c + d + e + f + g + h;
long zz = utilfunc(xx, yy, xx % yy);
return zz + 20;
}