+
William Stallings
Computer Organization
and Architecture
10th Edition
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NJ. All rights reserved.
+ Chapter 5
Internal Memory
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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
Table 5.1
Semiconductor Memory Types
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+
Dynamic RAM (DRAM)
RAM technology is divided into two technologies:
Dynamic RAM (DRAM)
Static RAM (SRAM)
DRAM
Made with cells that store data as charge on capacitors
Presence or absence of charge in a capacitor is interpreted
as a binary 1 or 0
Requires periodic charge refreshing to maintain data storage
The term dynamic refers to tendency of the stored charge to
leak away, even with power continuously applied
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+
Static RAM
(SRAM)
Digital device that uses the
same logic elements used in
the processor
Binary values are stored using
traditional flip-flop logic gate
configurations
Will hold its data as long as
power is supplied to it
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SRAM versus DRAM
SRAM
Both volatile
Power must be continuously supplied to the
memory to preserve the bit values
Dynamic cell
Simpler to build, smaller
More dense (smaller cells = more cells per unit DRAM
area)
Less expensive
Requires the supporting refresh circuitry
+ Tend to be favored for large memory
requirements
Used for main memory
Static
Faster
Used
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+
Read Only Memory (ROM)
Contains a permanent pattern of data that cannot be
changed or added to
No power source is required to maintain the bit values
in memory
Data or program is permanently in main memory and
never needs to be loaded from a secondary storage
device
Data is actually wired into the chip as part of the
fabrication process
Disadvantages of this:
No room for error, if one bit is wrong the whole batch of
ROMs must be thrown out
Data insertion step includes a relatively large fixed cost
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+
Programmable ROM (PROM)
Less expensive alternative
Nonvolatile and may be written into only once
Writing process is performed electrically and may be
performed by supplier or customer at a time later than
the original chip fabrication
Special equipment is required for the writing process
Provides flexibility and convenience
Attractive for high volume production runs
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Read-Mostly Memory
EEPRO Flash
EPROM
M Memory
Electrically erasable Intermediate between
Erasable programmable read- EPROM and EEPROM in
programmable read- only memory both cost and
only memory
functionality
Can be written into at
any time without
erasing prior contents Uses an electrical
Erasure process can be erasing technology,
performed repeatedly Combines the does not provide byte-
advantage of non- level erasure
volatility with the
flexibility of being
updatable in place
More expensive than Microchip is organized
PROM but it has the so that a section of
advantage of the More expensive than memory cells are
multiple update EPROM erased in a single
capability action or “flash”
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RAS = Row Address Select
CAS = Column Address Select
WE = Write Enable
OE = Output Enable
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+
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Interleaved Memory Composed of a collection of
DRAM chips
Grouped together to form a
memory bank
Each bank is independently
able to service a memory
read or write request
K banks can service K
requests simultaneously,
increasing memory read or
write rates by a factor of K
If consecutive words of
memory are stored in
different banks, the transfer
of a block of memory is
speeded up
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+
Error Correction
Hard Failure
Permanent physical defect
Memory cell or cells affected cannot reliably store data but
become stuck at 0 or 1 or switch erratically between 0 and 1
Can be caused by:
Harsh environmental abuse
Manufacturing defects
Wear
Soft Error
Random, non-destructive event that alters the contents of one
or more memory cells
No permanent damage to memory
Can be caused by:
Power supply problems
Alpha particles
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Dalam contoh
kasus ini
M=4
(4-bit words)
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Table 5.2
Increase in Word Length with Error Correction
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Catatan:
Posisi check bit ada posisi kelipatan 2
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SEC = single-error-correcting
DED = double-error-detecting
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Advanced DRAM
SDRAM
Organization
One of the most critical system bottlenecks
DDR-DRAM
when using high-performance processors is
the interface to main internal memory
The traditional DRAM chip is constrained
both by its internal architecture and by its
interface to the processor’s memory bus RDRAM
A number of enhancements to the basic
DRAM architecture have been explored
+
The schemes that currently dominate the
market are SDRAM and DDR-DRAM
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Synchronous DRAM (SDRAM)
One of the most widely used forms of DRAM
Exchanges data with the processor
synchronized to an external clock signal and
running at the full speed of the
processor/memory bus without imposing wait
states
With synchronous access the DRAM moves
data in and out under control of the system
clock
• The processor or other master issues the
instruction and address information which is
latched (dipalangi) by the DRAM
• The DRAM then responds after a set number of
clock cycles
• Meanwhile the master can safely do other tasks
while the SDRAM is processing
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Table 5.3
SDRAM
Pin
Assignmen
ts
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+
Double Data Rate SDRAM
(DDR SDRAM)
Developed by the JEDEC Solid State Technology
Association (Electronic Industries Alliance’s
semiconductor-engineering-standardization body)
Numerous companies make DDR chips, which are
widely used in desktop computers and servers
DDR achieves higher data rates in three ways:
First, the data transfer is synchronized to both the rising
and falling edge of the clock, rather than just the rising
edge
Second, DDR uses higher clock rate on the bus to increase
the transfer rate
Third, a buffering scheme is used
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Table 5.4
DDR Characteristics
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+
Flash Memory
Used both for internal memory and external memory
applications
First introduced in the mid-1980’s
Is intermediate between EPROM and EEPROM in both cost and
functionality
Uses an electrical erasing technology like EEPROM
It is possible to erase just blocks of memory rather than an
entire chip
Gets its name because the microchip is organized so that a
section of memory cells are erased in a single action
Does not provide byte-level erasure
Uses only one transistor per bit so it achieves the high density of
EPROM
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+ Summary Internal
Memory
Chapter 5
Semiconductor main
memory DDR DRAM
Organization Synchronous DRAM
DRAM and SRAM DDR SDRAM
Types of ROM Flash memory
Chip logic Operation
Chip packaging NOR and NAND flash
Module organization memory
Interleaved memory
Newer nonvolatile solid-state
Error correction memory technologies
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