Conversion from JK to T flipflop

Analysis of Clocked Sequential Circuits

 Design of MOD-8 asynchronous
counter using JK flipflop

Analysis of Clocked Sequential Circuits

Analysis of Clocked Sequential Circuits
 Analysis of
Clocked
Sequential
Circuits

Analysis of Clocked Sequential Circuits

 Presentation
Outline
 Analysis of Clocked Sequential circuits

 State and Output Equations

 State Table

 State Diagram

 Mealy versus Moore Sequential Circuits

 State and Timing Diagrams

Analysis of Clocked Sequential Circuits
 Analysis of Clocked Sequential
Circuits
Analysis is describing what a given circuit will do
The output of a clocked sequential circuit is determined by
1. Inputs
2. State of the Flip-Flops

Analysis Procedure:
3. Obtain the equations at the inputs of the Flip-Flops
4. Obtain the output equations
5. Fill the state table for all possible input and state values
6. Draw the state diagram
Analysis of Clocked Sequential Circuits
 Analysis
 Is this a clocked Example
sequential circuit?
YES!
 What type of Memory?
D Flip-Flops
 How many state variables?
Two state variables: A and B
 What are the Inputs?
One Input: x
 What are the Outputs?
One Output: y
Analysis of Clocked Sequential Circuits
 Flip-Flop Input
equations on the D inputs of the flip-flops?
Equations
 What are the

DA = A x + B x

D B = Ai x
 A and B are the current state

A(t) = A, B(t) = B
 D A and D B are the next state

A(t + 1) = D A , B(t + 1) = D B
 The values of A and B will be D A

and D B at the next clock edge

Analysis of Clocked Sequential Circuits
 Next State and Output
Equations
 The next state equations define the next state

At the inputs of the Flip-Flops

 Next state equations?

A t + 1 = DA = A x

+B x B t+1

= D B = Ai x

 There is only one output y

 What is the output

equation?
Analysis of Clocked Sequential Circuits
 State Table
 State table shows the Next State and Output in a tabular form

 Next State Equations: A t + 1 = A x + B x and B t+

1 = Ai x
 Output Equation: y = A + B x′

Another form of the state table

Analysis of Clocked Sequential Circuits

 State
 State diagram is a Diagram
graphical representation of a state table
 The circles are the states
 Two state variable  Four states (ALL values of A and B )
 Arcs are the state transitions
Labeled with: Input x / Output
y

Analysis of Clocked Sequential Circuits

 Combinational versus Sequential
Analysis
Analysis of Combinational Circuits
 Obtain the Boolean Equations
Output is a function of
 Fill the Truth Table input only

Analysis of Sequential Circuits

 Obtain the Next State Equations
Next state is a function of
 Obtain the Output Equations input and current state

 Fill the State Table Output is a function of

input and current
 Draw the State Diagram
state
Analysis of Clocked Sequential Circuits
 Example with Output = Current
Statethe sequential circuit shown below
 Analyze
 Two inputs: x and y
 One state variable A
 No separate output  Output = current state A
 Obtain the next state equation, state table, and state diagram

Analysis of Clocked Sequential Circuits

 Example with Output = Current
State

 Flip-Flop Input Equation:

DA = A ⨁ x ⨁ y
 Next State Equation: A t+1=A⨁x
⨁y

Analysis of Clocked Sequential Circuits

 Sequential Circuit with T Flip-
Flops

Circuit has two T Flip-Flops

One Input x
One output y
Two state variables: A and B
Obtain the T-FF input equations
Obtain the next state
equations Fill the state table
Draw the state diagram

Analysis of Clocked Sequential Circuits

 Recall: Flip-Flop Characteristic
Qt +1=D
Equation
 For D Flip-Flop:

Qt +1=T⨁
These equations

Q(t)
 For T Flip-Flop: define the Next State

Q t + 1 = J Qr t +
K r Q(t)
 For JK Flip-Flop:

D Flip-Flop T Flip-Flop JK Flip-Flop

D Q(t+1) T Q(t+1) J K Q(t+1)
0 0 0 Q(t) No change 0 0 Q(t) No change
Reset
1 Q'(t) Complement 0 1 0 Reset
1 1 Set
1 0 1 Set
1 1 Q'(t) Complement

Analysis of Clocked Sequential Circuits

 Sequential Circuit with T Flip-
Flops

T Flip-Flop Input Equations:

TA = B
x TB =
x
Next
State
Equatio
ns:

A(t + 1) = TA ⨁ A = (B x)
Analysis of Clocked Sequential Circuits
 From Next State Equations to State
Table
T Flip-Flop Input Equations:

TA = B

x TB =

Next State Equations:

A t + 1 = (B x) ⨁

A B(t Equation:
+ 1) = x ⨁
Output Notice that the output is a function

y =A
B
of the present state only.

B x
It does NOT depend on the input
Analysis of Clocked Sequential Circuits
 From State Table to State
Diagram

 Four States: AB = 00, 01, 10, 11 (drawn as circles)

 Output Equation: y = A B
x)
(does not depend on input

 Output y is shown inside the state circle (AB/y)

Analysis of Clocked Sequential Circuits
 Sequential Circuit with a JK Flip-
One Input x and two state variables: A and B (outputs of Flip-
Flops
Flops)

No separate output  Output = Current state A B

Obtain the JK input equations

Obtain the next state equations

Fill the state table

Draw the state diagram

Analysis of Clocked Sequential Circuits

 JK Input and Next State
Equations
JK Flip-Flop Input Equations:
JA = B and KA = B x′
JB = x′ and KB = A ⨁ x

A t + 1 = JA Ai + AK i
Next State Equations:

A
B t + 1 = JB B i + BK i
B
Substituting:
A t + 1 = B Ai +Bx i i A = A i B + AB i + Ax
B t + 1 = x i B i +A ⨁ x iB = Bi xi + A B x
+ A i B x′
Analysis of Clocked Sequential Circuits
 From JK Input Equations to State
Table
JK Input Equations: JA = B , KA = B x′ , JB = x′ and
KB = A ⨁ x

Analysis of Clocked Sequential Circuits

 From State Table to State
Four states: A B = 00, 01, 10, and 11 (drawn as
Diagram
circles) Arcs show the input value x on the state
transition

Analysis of Clocked Sequential Circuits

 Mealy versus Moore Sequential
Circuits
There are two ways to design a clocked sequential circuit:
1. Mealy Machine: Outputs depend on present state and
inputs
2. Moore Machine: Outputs depend on present state only

Analysis of Clocked Sequential Circuits

 Mealy Machine
 The outputs are a function of the present state and Inputs

 The outputs are NOT synchronized with the clock

 The outputs may change if inputs change during the clock cycle

 The outputs may have momentary false values (called glitches)

 The correct outputs are present just before the edge of the clock

Analysis of Clocked Sequential Circuits

 Mealy State Diagram
 An example of a Mealy state
diagram is shown on the right

 Each arc is labeled with:

Input / Output

 The output is shown on the

arcs of the state diagram

 The output depends on the

current state and input

 Notice that State 11 cannot be

reached from the other states
Analysis of Clocked Sequential Circuits
 Moore Machine
 The outputs are a function of the Flip-Flop outputs only

 The outputs depend on the current state only

 The outputs are synchronized with the clock

 Glitches cannot appear in the outputs (even if inputs change)

 A given design might mix between Mealy and Moore

Analysis of Clocked Sequential Circuits

 Moore State Diagram

0
 An example of a Moore state
0
diagram is shown on the right
00 1 01
0 0
 Arcs are labeled with input only

 The output is shown inside the 0 0 1

state: (State / Output)

1 10
 The output depends on the 1 1 0
1
current state only
1
 Summary
 To analyze a clocked sequential circuit:
1. Obtain the equations at the Inputs of the flip-flops
2. Obtain the Next State equations
 For a D Flip-Flop, the Next State = D input equation
 For T and JK, use the characteristic equation of the Flip-Flop

3. Obtain the Output equations Fill the

4. State Table
 Put all the combinations of current state and input
 Fill the next state and output columns

5. Draw the State Diagram

 Two types of clocked sequential circuits: Mealy versus Moore