FSMs in Verilog

Vasudeva Murthy T

1
 Session Objectives

• To understand a FSM and model it in verilog

• To learn about functions and tasks
• To learn to use re-entrant functions and tasks
• To provide a basic idea about UDPs
• To give insight on Specify blocks
• `ifdef, `else and `endif

2
 Session Topics

• FSMs
• Functions
• Tasks
• Automatic
• UDPs
• Specify Blocks

3
 Finite State Machines

• Any Circuit with Memory Is a Finite State Machine

– Even computers can be viewed as huge FSMs
• Design of FSMs Involves
– Defining states
– Defining transitions between states
– Optimization / minimization
• Above Approach Is Practical for Small FSMs Only

4
 Moore FSM
• Output Is a Function of Present State Only
• Describe Outputs as Concurrent Statements Depending on State
Only

Transition state 1/
Inputs function output 1
Next State Present State transition
condition 1
Memory
(register)
transition
condition 2
Output Outputs state 2/
function output 2

5
 Mealy FSM
• Output Is a Function of a Present State and Inputs
• Describe Outputs as Concurrent Statements Depending on State
and Inputs

Inputs Transition state 1

function
transition
Next State Present State condition 1/
Memory output 1
(register)
transition
Output Outputs condition 2/
function output 2

state 2

6
 Moore vs. Mealy FSM

• Moore and Mealy FSMs can be functionally equivalent

– Equivalent Mealy FSM can be derived from Moore FSM and vice versa
• Mealy FSM has richer description and usually requires smaller
number of states
– Smaller circuit area
• Mealy FSM computes outputs as soon as inputs change
– Mealy FSM responds one clock cycle sooner than equivalent Moore FSM
• Moore FSM has no combinational path between inputs and outputs
– Moore FSM is less likely to have a shorter critical path

7
 Moore FSM - Example 1
Moore FSM that Recognizes Sequence 10

0 1
0
1
S0 / 0 S1 / 0 1 S2 / 1

reset 0

S0: No
Meaning S1: “1” S2: “10”
elements
of states: observed observed
of the
sequence
observed
8
 Mealy FSM - Example 1
Mealy FSM that Recognizes Sequence 10

0/0 1/0 1/0

S0 S1

reset 0/1
S0: No S1: “1”
Meaning elements observed
of states: of the
sequence
observed
9
 Moore & Mealy FSMs – Example 1

clock
0 1 0 0 0
input

S0 S1 S2 S0 S0
Moore
S0 S1 S0 S0 S0
Mealy

10
 Finite string pattern recognizer (step 1)
• Finite string pattern recognizer
– one input (X) and one output (Z)
– output is asserted whenever the input sequence …010… has
been
observed, as long as the sequence …100… has never been seen

• Step 1: understanding the problem statement

– sample input/output behavior:

X: 0 0 1 0 1 0 1 0 0 1 0 …
Z: 0 0 0 1 0 1 0 1 0 0 0 …

X: 1 1 0 1 1 0 1 0 0 1 0 …
Z: 0 0 0 0 0 0 0 1 0 0 0 …
11
 Finite string pattern recognizer (step 2)

Step 2: draw state diagram

– for the strings that must be recognized, i.e., 010
and 100
– a Moore implementation
reset S0
[0]
0 1
S1 S4
[0] [0]
1 0

S2 S5
[0] [0]
0 0

S3 S6 0 or 1
[1] [0]

12
 Finite string pattern recognizer
• Exit conditions from state S3: have
recognized …010
– if next input is 0 then have …0100
= ...100 (state S6)
– if next input is 1 then have …0101
= …01 (state S2) reset S0
[0]
• Exit conditions from S1: recognizes 0 1
strings of form …0 (no 1 seen) S1 S4
0 1
– loop back to S1 if input is 0 [0] ...0 ...1 [0]
• Exit conditions from S4: recognizes 1 0
strings of form …1 (no 0 seen) S2 S5
– loop back to S4 if input is 1 [0] [0]
...01
0 1 0

S3 S6 0 or 1
...010 [1] ...100 [0]

13
 Finite string pattern recognizer
• S2 and S5 still have incomplete transitions
– S2 = …01; If next input is 1,
then string could be prefix of (01)1(00)

S4 handles just this case

– S5 = …10; If next input is 1, reset S0
then string could be prefix of (10)1(0) [0]
0 1
S2 handles just this case S1 S4
0 1
• Reuse states as much as possible [0] ...0 ...1 [0]
– look for same meaning 1 1 0
– state minimization leads to
S2 1 S5
smaller number of bits to [0] [0]...10
represent states ...01
• 0 1 0
Once all states have a complete
set of transitions we have a S3 S6 0 or 1
final state diagram ...010 [1] ...100 [0]

14
 Finite string pattern recognizer

• Description including state assignment (or state

encoding)
module string (clk, X, rst, Q0, Q1, Q2, Z); always @(posedge clk) begin
input clk, X, rst; if (rst) state = S0;
output Q0, Q1, Q2, Z; else
case (state)
parameter S0 = [0,0,0]; //reset state S0: if (X) state = S4 else state = S1;
parameter S1 = [0,0,1]; //strings ending in ...0 S1: if (X) state = S2 else state = S1;
parameter S2 = [0,1,0]; //strings ending in ...01 S2: if (X) state = S4 else state = S3;
parameter S3 = [0,1,1]; //strings ending in ...010 S3: if (X) state = S2 else state = S6;
parameter S4 = [1,0,0]; //strings ending in ...1 S4: if (X) state = S4 else state = S5;
parameter S5 = [1,0,1]; //strings ending in ...10 S5: if (X) state = S2 else state = S6;
parameter S6 = [1,1,0]; //strings ending in ...100 S6: state = S6;
default: begin
reg state[0:2]; $display (“invalid state reached”);
state = 3’bxxx;
assign Q0 = state[0]; end
assign Q1 = state[1]; endcase
assign Q2 = state[2]; end
assign Z = (state == S3);
endmodule

15
 Finite string pattern recognizer
• Review of process
– understanding problem
• write down sample inputs and outputs to understand
specification
– derive a state diagram
• write down sequences of states and transitions for sequences
to be recognized
– minimize number of states
• add missing transitions; reuse states as much as possible
– state assignment or encoding
• encode states with unique patterns
– simulate realization
• verify I/O behavior of your state diagram to ensure it
matches specification

16
 Implementation
•Implementation
– NS0 = CS0Q2’ + CS2’X + CS1CS2X’ + CS0X’
– NS1 = CS1X’ + CS0CS2 + CS0CS1 + CS2X
– NS2 = CS0’CS2’X’ + CS1’CS2’X’ + CS0’CS1’X’
– Z = CS0’CS1CS2
CS0 CS1 CS2 X NS0 NS1 NS2
0 0 0 0 0 0 1
0 0 0 1 1 0 0 P010
0 0 1 0 0 0 1
0 0 1 1 0 1 0
0 1 0 0 0 1 1 P100
0 1 0 1 1 0 0 Reset
0 1 1 0 1 1 0 R R

0 1 1 1 0 1 0
X D Q D Q
1 0 0 0 1 0 1
1 0 0 1 1 0 0
1 0 1 0 1 1 0 Clk
1 0 1 1 0 1 0
1 1 0 0 1 1 0
1 1 0 1 1 1 0
17
1 1 1 0 X X X
 Complex counter

• A synchronous 3-bit counter has a mode control M

– when M = 0, the counter counts up in the binary sequence
– when M = 1, the counter advances through the Gray code sequence

binary: 000, 001, 010, 011, 100, 101, 110, 111

Gray: 000, 001, 011, 010, 110, 111, 101, 100

Valid I/O behavior (partial)

Mode Input M Current State Next State

0 000 001
0 001 010
1 010 110
1 110 111
1 111 101
0 101 110
0 110 111

18
 Complex counter (state diagram)

• Deriving state diagram

– one state for each output combination
– add appropriate arcs for the mode control

reset S0 0 S1 0 S2 0 S3 0 S4 0 S5 0 S6 0 S7
[000] [001] [010] [011] [100] [101] [110] [111]
1
1 1 1
1
1 1 1

19
 Complex counter (state encoding)

• Description including state encoding

module string (clk, M, rst, Z0, Z1, Z2); always @(posedge clk) begin
input clk, X, rst; if rst state = S0;
output Z0, Z1, Z2; else
case (state)
parameter S0 = [0,0,0]; S0: state = S1;
parameter S1 = [0,0,1]; S1: if (M) state = S3 else state = S2;
parameter S2 = [0,1,0]; S2: if (M) state = S6 else state = S3;
parameter S3 = [0,1,1]; S3: if (M) state = S2 else state = S4;
parameter S4 = [1,0,0]; S4: if (M) state = S0 else state = S5;
parameter S5 = [1,0,1]; S5: if (M) state = S4 else state = S6;
parameter S6 = [1,1,0]; S6: if (M) state = S7 else state = S7;
parameter S7 = [1,1,1]; S7: if (M) state = S5 else state = S0;
endcase
reg state[0:2];
end
assign Z0 = state[0];
assign Z1 = state[1]; endmodule
assign Z2 = state[2];

20
 State Encoding Problem
• State Encoding Can Have a Big Influence on Optimality of the
FSM Implementation
– No methods other than checking all possible encodings are known to
produce optimal circuit
– Feasible for small circuits only
• Binary (Sequential) – States Encoded as Consecutive Binary
Numbers
– Small number of used flip-flops
– Potentially complex transition functions leading to slow implementations
• One-Hot – Only One Bit Is Active
– Number of used flip-flops as big as number of states
– Simple and fast transition functions
– Preferable coding technique in FPGAs

21
 State Encoding Example

State Binary Code One-Hot Code

S0 000 10000000
S1 001 01000000
S2 010 00100000
S3 011 00010000
S4 100 00001000
S5 101 00000100
S6 110 00000010
S7 111 00000001

22
 RTL Design Components
Data Inputs Control Inputs

Datapath Control
Circuit Circuit

Data Outputs
• Datapath circuits : Provides all necessary resources and interconnects
among them to perform specified task
• Examples of Resources - Adders, Multipliers, Registers, Memories,
etc.
• Control Circuit : Controls data movements in operational circuit by
switching multiplexers and enabling or disabling resources
• Follows Some ‘Program’ or Schedule
• Usually Implemented as FSM
23
 Moore Machine — 111 Detector

Q2
D1 Q1
z
reset
x

Q1
D2 Q2
Q2’
reset
Clock
Reset

Note how the reset is connected

– Reset will make both of the FFs zero, thus putting them into state A.
– Most FFs have both reset and “preset’’ inputs (preset sets the FF to one).
– The reset connections (to FF reset and preset) are determined by the state
assignment of the reset state.

24
 Verilog Organization for FSM

Q2
D1 Q1
z
reset
x

Q1
D2 Q2
Q2’
reset
Clock
Reset

Two always blocks

– One for the combinational logic — next state and output logic
– One for the state register

25
 Verilog Behavioral Specification

module FSM (x, z, clk, reset);

input clk, reset, x; Things to note
output z; – reg [1:2] — matches
reg [1:2] q, d; numbering in state
reg z; assignment (Q2 is least
always significant bit in counting)
@(posedge clk or negedge reset) – <= vs. =
if (~reset)
q <= 0;
else q <= d;
The sequential part
always @(x or q)
(the D flip flop)
begin
d[1] = q[1] & x | q[2] & x;
d[2] = q[1] & x | ~q[2] & x;
z = q[1] & q[2]; The combinational logic part
end next state
output

endmodule

26
 Verilog code for 11 seq FSM

module simple (Clock, Resetn, w, z); y: present state

input Clock, Resetn, w;
output z;
Y: next state
reg [2:1] y, Y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10; State assignment
// Define the next state combinational circuit
always @(w or y)
case (y)
A: if (w) Y = B;
else Y = A;
B: if (w) Y = C;
else Y = A;
C: if (w) Y = C;
else Y = A;
default: Y = 2'bxx;
endcase

// Define the sequential block

always @(negedge Resetn or posedge Clock)
if (Resetn == 0) y <= A;
else y <= Y; Y y Output z
Next state
// Define output
w circuit
Flip-flops
circuit
assign z = (y == C);
clock resetn
endmodule

27
 Generic FSM Diagram

Mealy

Inputs
Next State Outputs
Output
Logic Logic

State Register

Next State
Current State
FF

28
 State Diagram
Inputs a and b are 0,
unless specified otherwise
a=0 b=0 Outputs Y and Z are 0,
unless specified otherwise.

S0 a = 1/ S1 • Is this Mealy or Moore?

Z=1 Y=1

reset = 1 b = 1/ Z = 1

S2

29
 State Diagram: Mealy!

b=0 / Y=1 Inputs a and b are 0,

a=0 / Y=1 unless specified otherwise
a=0 a=1 / Y=1 Outputs Y and Z are 0,
unless specified otherwise.

S0 a = 1/ S1 • Is this Mealy or Moore?

Z=1 MEALY

reset = 1 b = 1/ Z = 1, Y=1

S2

30
 Mealy – Verilog

module fsm_mealy1 (output reg Y, Z, input clk, reset, a, b);

parameter S0 = 2’b00, S1 = 2’b01, S2 = 2’b10; //state values

reg [1:0] state, next_state;

always@(posedge clk) begin

if (reset)
state <= S0; // using non-blocking since sequential
else
state <= next_state; //continued on next slide
end

31
 Mealy – Verilog ….
//next state logic
always@(state, a , b)
case (state)
S0: if (a) next_state = S1;
else next_state = S0;
S1: if (b) next_state = S2;
else next_state = S1;
S2: next_state = S0;
default: next_state = 2’bx;
endcase

32
 Mealy – Verilog ….
//output logic
always@(state, a, b) begin
Z = 0, Y = 0; // avoids latches
case (state)
S0: if (a) Z = 1;
S1: begin
Y = 1;
if (b) Z = 1;
end
S2: ;
default :
begin
Y = 1’bx;
Z = 1’bx;
end
endcase
endmodule

33
 Mealy FSM

Inputs Outputs
Next State and
Output Logic

State Register

Current State
FF

What are the advantages and disadvantages of this approach?

34
 Mealy – Example 2
module fsm_mealy2 (output reg Y, Z, input clk, reset, a, b);

parameter S0 = 2’b00, S1 = 2’b01, S2 = 2’b10; //state values

reg [1:0] state, next_state;

always@(posedge clk) begin

if (reset)
state <= S0; // using non-blocking since sequential
else
state <= next_state; //continued on next slide
end

35
 Mealy – Example 2
// next state & output logic S1: begin
always@(state, a, b) Y = 1;
begin if (b)
begin
Y = 0; Z = 0;
next_state = S2;
case (state)
Z = 1;
S0: if (a)
end
begin else
next_state = next_state = S1;
S1; end
Z = 1; S2: next_state = S0;
end default: next_state = 2’bx;
else endcase
next_state = S0; endmodule

36
 Registered Mealy FSM
Output
Register
Inputs Outputs
FF
Next State and
Output Logic

State Register

Current State
FF

This delays the change in outputs by one cycle

37
 Registered Mealy FSM…
For higher level modeling, easier to debug
Output Registers
Registered
Inputs Outputs
FF
Next State, Datapath
& Output Logic
Combinational
Outputs
State & Datapath Registers

Current State
FF

38
 State Diagram: Moore

a=0 b=0
Inputs a and b are 0,
S0 S1 unless specified otherwise
a=1
Y=1
Outputs Y and Z are 0,
unless specified otherwise.

reset = 1 b=1

S2
Z=1

39
 Moore FSM

Inputs
Next State Output Outputs
Logic Logic

State Register

Next State
Current State
FF

40
 Verilog for Moore
module fsm_moore (output reg Y, Z, input clk, reset, a, b);

parameter S0 = 2’b00, S1 = 2’b01, S2 = 2’b10; //state values

reg[1:0] state, next_state;

always@(posedge clk)
begin
if (reset)
state <= S0; // using non-blocking since sequential
else
state <= next_state; //continued on next slide
end

41
 Verilog for Moore …………..
//next state logic //output logic
always@(state , a, b) always@(state)
case (state) begin
Z = 0, Y = 0; // avoids latches
S0: if (a) next_state = S1;
case (state)
else next_state = S0; S0: ;
S1: if (b) next_state = S2; S1: Y = 1;
else next_state = S1; S2: Z = 1;
S2: next_state = S0; default:
begin
default: next_state = 2’bxx;
Y = 1’bx;
endcase Z = 1’bx;
end
endcase
end
endmodule

42
 Functions & Tasks

• In verilog, tasks and functions allow the designer to

abstract verilog code that is used in many places in the
design
• Verilog supports encapsulation of a piece of code into a
task or a function. Use task or function when
– a section of the code that is used more than once, with
possibility different input
– break long procedural blocks into smaller parts in order to
improve readability and maintenance of the code

43
 Functions
• A procedure used in any expression
• Declared and referenced within a module
• Can be written on RHS on any equation
• Must have at least one input
• Has no outputs but returns a single value
• Can not call a task
• Can not contain timing controls
• Models combinational logic
• Can call other functions and itself
• Function name is implicitly declared return variable
• Type and range of return value can be specified
– default is 1 -bit

44
 Function Example
module and_func
(output [3:0] regx; functions can be called
input [3:0] in1, in2); from within procedural
blocks or continuous
assign regx = myandfunc(in1,in2); assignment statements
function [3:0] myandfunc(input [3:0] in1,in2);
myandfunc=(in1 & in2);
endfunction
more than one statement in
endmodule function block can be grouped with
begin and end

Note : The subsequent statements of a function call will not be executed unless

function returns to calling statement

 M.S Ramaiah School of Advanced Studies - Bangalore 45

 Function Example
module arithmetic_unit (
output [4: 0] result_1,
output [3: 0] result_2,
input [3: 0] operand_1, operand_2);
function call
assign result_1 = sum_of_operands (operand_1, operand_2);
assign result_2 = larger_operand (operand_1, operand_2);

function [4: 0] sum_of_operands(input [3: 0] operand_1, operand_2);

sum_of_operands = operand_1 + operand_2;
endfunction function output function inputs

function [3: 0] larger_operand(input [3: 0] operand_1, operand_2);

larger_operand = (operand_1 >= operand_2) ? operand_1 : operand_2;
endfunction
endmodule

 M.S Ramaiah School of Advanced Studies - Bangalore 46

 Task

• Declared and referenced within a module

• Forms a single line statement in itself
– looks like component instantiation but not
• Can be called from only from procedural blocks
• Need not have any input or output
• Can have any number of inputs and more than one output
• Can call another task as well as function
• Can contain timing controls
• Can be used to model both sequential and combinational logic
• Local variables can be declared and used

 M.S Ramaiah School of Advanced Studies - Bangalore 47

 Example Task
module operation
(input [3:0] a,b);

parameter delay = 10;

reg [3:0] aand, aor, axor;

always@(a ,b)
bitoper(aand, aor, axor, a,b);

task bitoper(output [3:0] a_and, a_or, a_xor, input [3:0] a,b);

begin
#delay a_or =a| b ;
a_xor = a ^ b ;
a_and = a & b ;
end
endtask

endmodule
 M.S Ramaiah School of Advanced Studies - Bangalore 48
 Task – Count # of 1’s
module bitcnt ( task countones(input [7:0] rega,
output reg [3:0] count);
input [7:0] data;
reg [7:0] temp_reg;
output reg [3:0] bitcount;
begin
count=0;
always @ (data)
temp_reg=rega;
countones(data,bitcount);
while (temp_reg)
begin
count=count +temp_reg[0];
temp_reg=temp_reg >> 1;
end
end
endtask
endmodule
 M.S Ramaiah School of Advanced Studies - Bangalore 49
 Re-entrant Functions and Tasks
• Function and task variables are static in nature
• Recursive functions/task calls will overwrite value of previous
variable
• To avoid the overwriting functions/ tasks should be declared
automatic
• Example

function automatic [63:0] factorial;

input [31:0] n;
if (n == 1)
factorial = 1;
else
factorial = n * factorial(n-1);
endfunction

 M.S Ramaiah School of Advanced Studies - Bangalore 50

 Verilog for Libraries

• Verilog is also used for library development

• ASIC designers use standard cell library for designs
• Obtained netlist may need to be simulated
• Technology library can not be used for simulation
• Verilog is used to model functional and timing information of
cells
• Called verilog model library
• Equivalent to VITAL libraries of VHDL language
• Consists of UDPs and Specify blocks

 M.S Ramaiah School of Advanced Studies - Bangalore 51

 UDP

• Other than the built in primitives, Verilog has user defined

primitives(UDP)
• UDPs extend existing primitives by allowing logic to be defined in
tabular format
• UDPs are useful for ASIC library cell design
• UDPs can be used to augment the set of predefined primitive
elements
• UDPs are self contained they do not instantiate other modules
• UDPs can represent both sequential as well as combinational logic
• Behaviour of UDP is described in a truth table
• UDPs are instantiated like built in primitives

 M.S Ramaiah School of Advanced Studies - Bangalore 52

 Characteristics

• UDPs can have only one output

• UDPs can have 1 to 10 inputs
• All ports have to be scalar and no bi-directional ports are allowed
• The logic value ‘z’ is not allowed
• The output port must be listed first in the port list
• The UDP output terminal can be initialized to a known value at
start of simulation
• UDPs can not be synthesized
• They are typically used in ASIC standard cell library development

 M.S Ramaiah School of Advanced Studies - Bangalore 53

 Example – Combinational UDP
• UDP definitions occur outside of a module
• For any input combination that is not specified in the truth table the
output results in a ‘x’

primitive multiplexer (o, a, b, s);

output o;
input a, b, s; The output port must
This is the table be the first port
name of the // a b s : o
primitive 0 ? 1 : 0;
1 ? 1 : 1;
? 0 0 : 0;
? 1 0 : 1;
0 0 x : 0;
1 1 x : 1;
endtable These entries
endprimitive reduce pessimism

 M.S Ramaiah School of Advanced Studies - Bangalore 54

 Example – Sequential UDP
• The output of a sequential UDP is of data type register
• The ? is used to represent a don’t care condition in input and
current state
• An additional field is used to specify the next state
primitive latch ( q, clock, data);
output reg q;
input clock, data;
initial q = 1’ b1;
table
// clock data current state next state
0 1 : ? : 1 ;
0 0 : ? : 0 ;
1 ? : ? : - ;
endtable
endprimitive

 M.S Ramaiah School of Advanced Studies - Bangalore 55

 Example level sensitive UDP
primitive d_edge_ff ( q, clk, data );
output reg q;
input clk, data;
table
// clk data state next :
(01) 0 : ? : 0 ;
(01) 1 : ? : 1 ;
•Rising edge is represented by r, (01)
(0x) 1 : 1 : 1 ;
(0x) 0 : 0 : 0 ; •Positive edge by p, 01, 0x, x1
(x1) 0 : 0 : 0 ; •Falling edge is represented by f, (10)
(x1) 1 : 1 : 1 ; •Negative edge by n, 10, x0, 1x
// ignore negative edge of clock •(??) can be replaced by * denoting
(?0 ) ? : ? : - ;
(1x) ? : ? : - ; any value change in signal
// ignore data changes on steady clock
? (??) : ? : - ;
endtable
endprimitive

 M.S Ramaiah School of Advanced Studies - Bangalore 56

 To summarize

• Behavior is defined using a table

• UDPs are instantiated like built - in primitive
• They are a compact, efficient method of describing logic functions
• Both combinational and sequential behavior can be described
• UDPs are self - contained
• Many built - in primitives can be replaced by a single UDP
• There must be a separate UDP for every output
• The Z value is not supported hence UDP ports can not be bi -
directional
• UDPs are not synthesizable

 M.S Ramaiah School of Advanced Studies - Bangalore 57

 The Specify Block
module noror (out, a, b, c); • Specify block defines module
output out; timing data
input a, b, c; • Separates timing information
nor n1 (net1, a, b); from functionality
or o1 (out, c, net1); • Define module timing paths
• Assign delays to those paths
specify • Perform timing checks
• Module parameters can not be
(a => out) = 2;
used in a specify block
(b => out) = 3;
• Specify blocks use a special
(c => out) = 1; “specify parameter“ (specparam)
endspecify

endmodule

 M.S Ramaiah School of Advanced Studies - Bangalore 58

 Specify Block Parameters
module noror (op. a, b, c); • Specparam declares
output op; parameters for specify block
input a, b, c; • Must be declared inside
nor n1 (net1, a, b); specify block
or o1 (op, c, net1); • Only visible inside block
• Cannot be over-ridden like
parameters
specify
• Parameters cannot be used
specparam aop = 2,
inside a specify block
bop = 3, • Must use specparam
cop = 1;
(a => op) = aop;
(b => op) = bop;
(c => op) = cop;
endspecify
endmodule
 M.S Ramaiah School of Advanced Studies - Bangalore 59
 Accurate Delay Control
• Rise, fall and turn-off delays can be specified for gates and
module paths
– Rise is transition to 1
– Fall is transition to 0
– Turn-off is transition to z

and # (2, 3) (out, in1, in2, in3); // rise, fall

bufif0 #(3, 3, 7) (out, in, ctrl); // rise, fall. turn-off
specify
(in => out) = (1, 2); // rise, fall
(a = > b) = (5, 4, 7); // rise, fall, turn-offs
endspecify

 M.S Ramaiah School of Advanced Studies - Bangalore 60

 Accurate Delay Control
• Minimum, typical, Maximum values can be specified for each
delay
– Syntax – (minimum : typical ; maximum)

// min : typ : max

or # (3 . 2 : 4 . 0 : 6 . 3) o1 (out, in1, in2);
// rise , fall
not # (1 : 2 : 3, 2 : 3 : 5) (o, in);

specify // rise , fall , turn-off (each having min:typ:max values)

(b => y) = (2 : 3 : 4, 3 : 4 : 6, 4 : 5 : 8);
endspecify

 M.S Ramaiah School of Advanced Studies - Bangalore 61

 Parallel and Full Connection
=> represents parallel connection
- Must be between ports must be of the same size
* > represents full connection
- All listed inputs connect to all listed outputs
Parallel module path Full module path
q
input a q output input a output
bits b qb bits bits b bits
qb
2 paths
4 paths
Bit - to - bit connections Bit - to - vector connections
Use => to define path Use *> to define path

(a, b => q, qb) =15; (a, b *> q, qb) = 15;

is equivalent to is equivalent to
(a => q ) = 15; (a => q ) = 15; (b => q ) = 15;
(a => qb ) = 15; (b => qb ) =
(b => qb ) =15;
15;
 M.S Ramaiah School of Advanced Studies - Bangalore 62
 State Dependent Path Delays
* State dependent path delay are assigned to module path only
if a specific condition is true
- Note : not an if statement - no else is allowed....

module jexor (op, a, b);

input a, b;
output op;
a
xor (op, a, b); op
b
specify
if (a) (b => op) = (5 : 6 : 7);
if (!a) (b => op) = (5 : 7 : 8);
if (b) (a => op) = (4 : 5 : 7);
if (!b) (a => op) = (5 : 7 : 9);
endspecify
endmodule

 M.S Ramaiah School of Advanced Studies - Bangalore 63

 Summary

• FSMs have been learnt

• Moore and Mealy machines have been discussed
• Verilog coding styles for FSMs have been discussed
• Functions and Tasks have been discussed
• Relevance, difference of functions and tasks has been
comprehended
• Insight to verilog modeling of libraries has been given

 M.S Ramaiah School of Advanced Studies - Bangalore 64