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Raising a new Generation of Leaders

Module 7:Memory interfacing

and Address Decoding
By Omoruyi O. and Olatimehin O.P.
 Topic
• Memory, Types and Notes
• Memory Interfacing
• Address Decoding.
• I/O Interfacing: Memory mapped I/O,
Isolated I/O, bus timing, I/O instructions.

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 Memory
• With regards to Semi-conductor memories,
they are devices and circuits that can store
data or program.
• Memories for data are stored in Volatile units
called Random Access memory (RAM).
• Memories for program are stored in
persistent units called Read-only Memory
(ROM).
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Memory notes
• A memory device can be viewed as a single-
column table: Memory Address Memory
Binary Hex Contents
• Table index (row number) refers to the address 00-0000-0000 000 10011001
of the memory. 00-0000-0001 001 00111000
• Table entries refer to the memory contents or 00-0000-0010 002 11001001
data. 00-0000-0011 003 00111011
• Each table entry is referred to as a memory
location or as a word.

• Both the memory address and the memory

contents are binary numbers, expressed in most 11-1111-1100 3FC 01101000
cases in Hex format. 11-1111-1101 3FD 10111001
11-1111-1110 3FE 00110100
• The size of a memory device is specified as the 11-1111-1111 3FF 00011000
number of memory locations times the width or
word size (in bits). 1024 X 8 (or 1KX8) Memory
For example A memory with 16 locations and a
word size of 8 bits can store 16 x 8 = 128 bits of
data.
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Memory notes
Pertaining microprocessors, memory devices or
memory chips are often connected with three Y00 Location 000
types of lines : Address, Data, and Control. Y01 Location 001
Y02 Location 002
Address Lines: The input lines that select a A00 Y03 Location 003
A01
memory location within the memory device.
Decoders are used inside the memory chip to
An-2
select a specific location. The number of address An-1 YFC Location 0FC
YFD Location 0FD
pins on a memory chip specifies the number of YFE Location 0FE
memory locations. YFF Location 0FF

• If a memory chip has 13 address pins (A0 to

A12), then it has: 213 = 23 X 210 = 8K locations.

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Data Lines
• Data Connections: All memory devices have a set of data output pins
(for ROM devices), or input/output pins (for RAM devices).
 Most RAM chips have common bi-directional I/O connections.
 Most memory devices have 1, 8 or 16 data lines.
Data Input Lines
(DI0..DIn-1)

k- address lines
k- address lines 2m words k- address lines
m
2 words (A0..A m-1 ) 2m words
(A0..A m-1 ) (A0..A m-1 )
Read (RD) Read/Write (R/W) n-bits per
n-bits per Output Enable (OE) n-bits per
Write (WR) Chip Select (CS) word
word Chip Select (CS) word
Chip Select (CS)

Data Input/Output Data Output Lines

Data Output Lines (D0..Dn-1 )
(DO0..DOn-1 ) Lines (D0..Dn-1 )

(2m X n) RAM with separate I/P (2m X n) RAM with common I/P (2m X n) ROM with only O/P Data
and O/P Data lines and O/P Data lines lines

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 Control Connection
• Enable Connections:
 All memory devices have at least one Chip Select (CS) or Chip Enable (CE) input, used to select or enable the memory device.
‒ If a device is not selected or enabled then no data can be read from or written into it.
‒ The CS or CE input is usually controlled by the microprocessor through the higher address lines via an address decoding
circuit.

• Control Connections:
 RAM chips have two control input signals that specify the type of memory operation: the Read (RD) and the Write (WR)
signals.
‒ Some RAM chips have a common Read/ Write (R/W) signal.
 ROM chips can perform only memory read operations, thus there is no need for a Write (WR) signal.
‒ In most real ROM devices the Read signal is called the Output Enable (OE) signal.

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 Memory Interfacing
8086 has a 20-bit address bus, and hence, it can address 2 20 or
1,048,576 addresses. In each location, a byte is stored. When a
word is stored in the memory, it is stored in two consecutive
locations. Strictly speaking, both memory read and memory write
operations require more than one memory cycle. The basic operation
of reading/writing a byte from/to a memory location/port is called a
machine cycle. A machine cycle is made up of many states.
If we want the 8086 to complete a memory read and memory write
operations to be completed with one machine cycle, the memory is
to be organized in the form of two banks. Each bank will have
524,288 bytes each.
8
Diagram of Data bus model

9
 Memory interfacing
(continued)
One memory bank contains all the even addressed locations like 00000,
00002 and 00004. The data lines of this bank are connected to the
lower eight data lines, D0 through D7 of the 8086. The other memory
bank has all the odd addressed locations like 00001, 00003 and 00005.
The data lines of this bank are connected to the upper eight data lines,
D8 through D15 of the 8086. Address line A0 is used as part of the
enabling for memory in the lower bank.
Address lines A1 through A19 are used to select the desired memory
device in the bank to address the desired byte in the service. These address
lines from A1 through A19 are also used to access a particular location in
the upper bank. An additional signal called Bus High Enable (BHE –Active
Low) is used to enable the upper memory bank. An external latch,
strobed by ALE, grabs the BHE (Active Low) signal that holds it stable
for the rest of the machine cycle.
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Table showing bus cycles and memory access

11
Bus cycle explained
• A bus cycle defines the basic operation that
a microprocessor performs to communicate
with external devices. Examples of bus
cycles are memory read, memory write,
input/output read and input/output write.

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Data transfer

13
Data Transfer

14
Data transfer (16 bit or word
transfer)

15
16 bit Data bus odd word
transfer

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 Memory read
• A memory read operation is carried out in the
following steps:
Clock T1 T2 T3
 The processor loads on the Address bus the
address of the memory location to be read Address Bus Valid Address
(Step 1).
‒ Some of the address lines select the Chip Enable

memory devices that owns the memory Read (RD)

location to be read (Step 1a), while the
Data Bus Invalid Data Valid Data
rest point to the required memory location
Step 1a
within the memory device. Step 2 Step 3 Step 4
Step 1
 The processor activates the Read (RD) signal
(Step 2).
‒ The selected memory device loads on the
data bus the content of the memory
location specified by the address bus (Step
3).
 The processor reads the data from the data
bus, and resets the RD signal (Step 4).

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 Memory write
• A memory write operation is carried out in Clock T1 T2 T3
the following steps:
Address Bus Valid Address
 The processor loads on the Address bus
the address of the memory location Data Bus Valid Data
(Step 1).
‒ Some of the address lines select the Chip Enable
memory devices that owns the Write (WR)
memory location to be written (Step Step 2
1a), while the rest point to the Step 1
Step 4
Step 1a Step 3
required memory location within the
memory device.
 The processor loads on the data bus the
data to be written (Step 2).
 The processor activates the Write (WR)
signal (Step 3).
‒ The data at the data bus is stored in
the memory location specified by the
address bus (Step 4). 18
 The process of accessing memory
involves these steps:
1. Address Generation: The CPU generates the address of
the memory location it wants to access.
2. Address Transmission: The address is sent over the
address bus to the memory.
3. Memory Selection: The memory chip with the matching
address is selected.
4. Data Transfer: The selected memory chip either reads data
from its location or writes data to it.
5. Data Transmission: The data is transferred over the data
bus to or from the CPU.

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 Address Decoding
Address Decoding: This is the process of selecting a specific memory location. The
computer uses address decoding to locate specific memory locations.
The physical address space, or memory map, of a microprocessor refers to the range of
addresses of memory location that can accessed by the microprocessor. The size of the
address space depends on the number of address lines of the microprocessor.
At least two memory devices are required in a microprocessor system: one for the ROM
and one for the RAM. In an 8086 the high addresses in the memory map should always be
occupied by a ROM, while the low addresses in the memory map should always be
occupied by a RAM. Address decoding is required in order to enable the connection of
more than one memory devices on the microprocessor. Each device will occupy a unique
area in the memory map.
A memory system is not fully decoded if some of the address lines are not used by the
address decoding circuit or memory. In this case a memory device will occupy more than
one sections in the memory map. This is referred as memory mirroring or memory
imaging. 20
Simplified memory map of 8086-DATS

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 I/O Interfacing
Some microprocessors use the same address space for both
memory and input/output devices. In this arrangement all
instructions that are capable of accessing the memory locations
can also access the input/output devices. This can be called
Memory-mapped I/O. I.e. Memory-Mapped I/O is a way to
treat I/O devices (like keyboards, mice, and printers) as if they
were part of the computer's memory.
However, 8086 microprocessor permits the establishment of two
separate address spaces for memory and input/output devices.
Having separate address space for the input/output devices is
called direct I/O or Isolated I/O.
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 Bus timing
• The three buses of the 8086 and 8088—address, data, and
control—function exactly the same way as any other
microprocessor. If data are written to the memory, the
microprocessor outputs the memory address on the address
bus, outputs the data to be written into memory on the data
bus, and issues a write (WR) to memory and IO/M= 0 for the
8088 and M/IO= 1 for the 8086. If data are read from the
memory, the microprocessor outputs the memory address on
the address bus, issues a read memory signal (RD), and
accepts the data via the data bus.
• Bus Timing: This refers to the timing signals that control the
flow of data on the bus. 23
 Bus Timing Continues
• The 8086/8088 microprocessors use the memory and I/O in periods
called bus cycles. Each bus cycle equals four system-clocking
periods (T states). Newer microprocessors divide the bus cycle into
as few as two clocking periods. If the clock is operated at 5 MHz (the
basic operating frequency for these two microprocessors), one
8086/8088 bus cycle is complete in 800 ns. This means that the
microprocessor reads or writes data between itself and memory or
I/O at a maximum rate of 1.25 million times a second. (Because of
the internal queue, the 8086/8088 can execute 2.5 million
instructions per second [MIPS] in bursts.)
• Newer versions of microprocessors operate at much higher transfer
rates due to higher clock frequencies.
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 I/O instructions
• The instruction set contains one type of instruction that transfers information to an I/O
device (OUT) and another to read information from an I/O device (IN). Instructions (INS
and OUTS, found on all versions except the (8086/8088) are also provided to transfer
strings of data between the memory and an I/O device.
• Instructions that transfer data between an I/O device and the microprocessor’s
accumulator
• (AL, AX, or EAX) are called IN and OUT. The I/O address is stored in register DX as a 16-
bit I/O address or in the byte (p8) immediately following the opcode as an 8-bit I/O
address. Intel calls the 8-bit form (p8) a fixed address because it is stored with the
instruction, usually in a ROM.
• The 16-bit I/O address in DX is called a variable address because it is stored in a DX,
and then used to address the I/O device. Other instructions that use DX to address I/O
are the INS and OUTS instructions. I/O ports are 8 bits in width, so whenever a 16-bit
port is accessed, two consecutive 8-bit ports are addressed. A 32-bit I/O port is four 8-
bit ports.
• I/O Instructions: These are special instructions that the computer uses to 25
 Address size expansion
• More than one memory devices can be used to expand the number of
memory locations on the system.
• To expand the word size do the following:
 Determine the number of memory chips required, by dividing the required memory size with the size of the
memory devices to be used.
 Connect the data lines of each memory chip in parallel on the data lines of the processor.
 Connect the address lines of each memory chip in parallel with the low address lines of the processor.
 Connect the CS lines of each memory device with the high address lines of the processor through an address
decoding circuit..
 Connect together all WR and all RD lines of each memory device.

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Address Size Expansion: (32X4 RAM module using
8X4 RAM chips)
D0
D1
D2
D3
RAM1 D3 D0 RAM2 D3 D0 RAM3 D3 D0 RAM4 D3 D0
0 0 0 0
1 1 1 1
2 2 2 2
A0 3 A0 3 A0 3 A0 3
A1 4 A1 4 A1 4 A1 4
A2 5 A2 5 A2 5 A2 5
6 6 6 6
7 7 7 7
RD WR CS RD WR CS RD WR CS RD WR CS
RD
WR
A0
A1
A2
A3 A Y0
A4 B Y1
A5 Y2
CS
A6 Y3
Address 2X4 DEC.
Selection

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 Design an 8KX8 RAM module using 2KX8 RAM chips. The module should be connected on an
8-bit processor with a 16-bit address bus, and occupy the address range starting from the
address A000. Show the circuit and the memory map.

Starting Address = A000 = 1010-0000-0000-0000

• Number of memory devices needed ==> A15 = 1, A14 = 0 and A13 = 1
= 8K/2K = 4 A13
A14
Address Selection Circuit
A15
• Decoder needed = 2X4
A15 A14 A13 A12 A11 A10 A0 Mem. Map
• Number of address lines on each 0 0 0 0 0 0 0 0000 Not
2KX8 memory chip = 11 1 0 0 1 1 1 1 9FFF Used
1 0 1 0 0 0 0 A000
2m = 2K = 21 x 210 = 211  (A0..A10) RAM1
1 0 1 0 0 1 1 A7FF
• Decoder needed = 2X4 1 0 1 0 1 0 0 A800
RAM2
1 0 1 0 1 1 1 AFFF
 2 address lines are needed for the 1 0 1 1 0 0 0 B000
decoder.  (A11..A12) 1 0 1 1 0 1 1 B7FF
RAM3

• Number of address lines needed for 1 0 1 1 1 0 0 B800

RAM4
1 0 1 1 1 1 1 BFFF
the address selection circuit
1 1 0 0 0 0 0 C000 Not
= 16 - 11 - 2 = 3  (A13, A14 A15) 1 1 1 1 1 1 1 FFFF Used

28 28
D7
D0 D7 D0 D7 D0 D7 D0 D7

2Kx8 RAM 2Kx8 RAM 2Kx8 RAM 2Kx8 RAM

D0 A0 A0 A0 A0

A10 A10 A10 A10

RD WR CS RD WR CS RD WR CS RD WR CS

RD
WR

A0
2X4 DEC.
A11
A Y0
A12
B Y1
A13
Y2
A14
CS Y3
A15 A15

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