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Lecture-25 (KEC-072) Raman Kapoor ABES

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26 views16 pages

Lecture-25 (KEC-072) Raman Kapoor ABES

Uploaded by

Deepanshi Tripathi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DR.

APJ ABDUL KALAM TECHNICAL UNIVERSITY

Branch - ECE
VLSI Design
(KEC-072)
Lecture – 25

Design for Testability Techniques


By

Dr. Raman Kapoor


Associate Professor
Department of Electronics & Communication Engineering
ABES Engineering College, Ghaziabad
Scan-based DFT Techniques
• It is already known that the controllability and observability can be enhanced by
providing more accessible logic nodes via additional I/O lines and multiplexers.
• However, the use of additional I/O pins can be costly not only for chip fabrication
but also for packaging.
Scan-based DFT Techniques
• A popular alternative is to use scan registers with both shift and parallel load
capabilities. The scan design technique is a structured approach to design
sequential circuits for testability.
• The storage cells in registers are used as observation points, control points, or both.
• By using the scan design techniques, the testing of a sequential circuit is reduced to
the problem of testing a combinational circuit, since a sequential circuit consists of
a combinational circuit and some storage elements
Scan-based DFT Techniques
• In the scan-based design, the storage elements are connected to form a long serial
shift register, the so-called scan path, by using multiplexers and a control (test/
normal) signal.
• In the test mode, the scan-in signal is clocked into the scan path, and the output of
the last stage latch is scanned out.
• In the normal mode, the scan-in path is disabled and the circuit functions as a
sequential circuit. the scan-in path is disabled and the circuit functions as a
sequential circuit.
Scan-based DFT Techniques
• The general structure of scan-based approach is as follows:
Scan-based DFT Techniques
• The testing sequence is as follows:
Scan-based DFT Techniques
• Example: Scan-based design of an edge-triggered D-type flip-flop.
• Practically, two clocks can be used: one for normal operation and one for shift
operation.
Level Sensitive Scan Design
• The LSSD incorporates both the level sensitivity and the scan path approach using
shift registers. The level sensitivity is to ensure that the sequential circuit response
is independent of the transient characteristics of the circuit, such as the component
and wire delays.
• Thus, LSSD removes hazards and races. Its ATPG is also simplified since tests
have to be generated only for the combinational part of the circuit.
Built-in Self Test (BIST) Techniques
• Built-in self-test, or BIST, is a DFT methodology involving the insertion of
additional hardware and software features into integrated circuits to allow them to
perform self-testing.
• BIST avoids the use of costly ATE (Automated Test Equipment).
• Only two external pins (CONTROL and OUTPUT) are sufficient.
• BIST requires lower system effort and provides better fault diagnosis.
• System maintenance and repair costs are reduced.
Built-in Self Test (BIST) Techniques
• The BIST concept is also applicable to circuits that have no direct connections to
external pins, such as embedded memories.
• The essential circuit modules required for BIST include:
– Pseudo random pattern generator (PRPG)
– Output response analyzer (ORA)
Built-in Self Test (BIST) Techniques
• The two most common categories of BIST are the Logic BIST (LBIST) and the
Memory BIST (MBIST).
• LBIST, which is designed for testing random logic, typically employs a
pseudorandom pattern generator to generate input patterns that are applied to the
device's internal scan chain, and a multiple input signature register (MISR) for
obtaining the response of the device to these input test patterns.
• MBIST is used specifically for testing memories. It has a circuit that apply, read,
and compare test patterns.
Built-in Self Test (BIST) Techniques
• The basic architecture of BIST is as follows:
Built-in Self Test (BIST) Techniques
• PRPG using LFSR: Pseudo Random Number Generators (PRNG) are widely used
in VLSI Design as Test Pattern Generators for testing of digital circuits in a BIST
system. These can be designed using the LFSR.
Built-in Self Test (BIST) Techniques
• ORA using LFSR: The signature generator consists of a single-input LFSR in
which all the latches are edge-triggered. The signature is the content of this register
after the last input bit has been sampled. The input sequence (G) can be
represented as: , where Q represents the output sequence, P is the characteristic
polynomial of LFSR and R is the remainder which is the signature to be compared.
Built-in Self Test (BIST) Techniques

Advantages of BIST Disadvantages of BIST


Reduced costs of testing Additional Silicon area and pins required
Independent of technology Power overhead increases
Enhanced fault coverage On-chip testing hardware can fail
Reduced Testing Times
Concurrent testing is possible
THANK YOU

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