Metal Oxide Semiconductor Field

Effect Transistors
MOS Capacitor
MOS Capacitor
• An MOS capacitor is made of a semiconductor
body or substrate, an insulator film, such as
SiO2, and a metal electrode called a gate.
• The MOS capacitor is not a widely used device in
itself. However, it is part of the MOS transistor

The MOS capacitor.

 FLAT-BAND CONDITION AND
FLAT-BAND VOLTAGE
• It is common to draw the energy band
diagram with the oxide in the middle
and the gate and the body on the left-
and right-hand sides
• Flat band is the condition where the
energy band (Ec and Ev) of the
substrate is flat at the Si–SiO2 interface.
• Applying a negative voltage to the gate
thus raising the band diagram on the
left-hand side.

(a) Polysilicon-gate/oxide/semiconductor
capacitor and
(b)(b) its energy band diagram with no
applied voltage.
• When the band is flat in the body the
surface electric field in the substrate is
zero. Therefore the electric field in the
oxide is also zero, i.e., Ec and Ev of SiO2
are flat, too.
• Vacuum level E0, is the energy state of
electrons outside the material.
• Electron affinity, the difference
between E0 and Ec.
• The applied voltage at the flat-band
condition, called Vfb, the flat-band
voltage, is the difference between the
Fermi levels at the two terminals.

Energy band diagram of the MOS system at the

flat-band condition. A voltage equal to Vfb is applied
between the N+-poly-Si gate and the P-silicon body
to achieve this condition. g is the gate-material
work function, and s is the semiconductor work
function. E0 is the vacuum level.
 SURFACE ACCUMULATION
• When Vg ≠ Vfb, φs (surface voltage) and Vox
(oxide voltage) will be non-zero in general. q
φs is the band bending in the substrate.
• Because the substrate is the voltage
reference, φs is negative if Ec bends upward
toward the surface adnd positive if EC bends
downward.
• ps >> Na. there are a large number of holes
at or near the surface. They form an
accumulation layer and these holes are
called the accumulation-layer holes, and
their charge the accumulation charge, This MOS capacitor is biased into surface accumulation
Qacc. This condition is known as surface (ps > p0 = Na).
(a) Types of charge present. . represents holes and –
accumulation. represents negative charge. (b) Energy
At flat band, Vg = Vfb, φs = Vox = 0
band diagram.
 SURFACE DEPLETION
• More positive Vg than Vfb is applied
• There is now a depletion region at the surface
because EF is far from both Ec and Ev and
electron and hole densities are both small. This
condition is called surface depletion.

This MOS capacitor is biased into surface

depletion.
(a) Types of charge present; (b) energy
band diagram.
THRESHOLD CONDITION AND THRESHOLD
VOLTAGE

• If Vg more positive, the energy band bends

down further.
• At some Vg, EF will be close enough to Ec at
the Si–SiO2 interface that the surface is no
longer in depletion but at the threshold of
inversion.
• The term inversion means that the surface is
inverted from P type to N type, or electron
rich.

The threshold condition is reached

when ns = Na, or equivalently, A = B,
or φs= φst = 2 φB. Note that positive φst
corresponds to downward band
 STRONG INVERSION BEYOND
THRESHOLD
• The inversion charge density is
represented with Qinv. (C/cm2). φs does not
increase much further beyond 2 φB

An MOS capacitor biased into inversion. (a)

Types of charge present; (b) energy band
diagram with arrow indicating the sense of
positive Vg.
 MOS C–V CHARACTERISTICS
• The capacitance–voltage (C–V) measurement is
a powerful and commonly used method of
determining the gate oxide thickness, substrate
doping concentration, threshold voltage, and
flat-band voltage.
• The capacitance in the MOS theory is always the
small-signal capacitance

• In the accumulation region, the MOS

capacitor is just a simple capacitor with
capacitance Cox. Setup for the C–V
measurement.
• In the depletion region, the MOS
capacitor consists of two capacitors in
series: the oxide capacitor, Cox, and the
depletion-layer capacitor, Cdep.
 The quasi-static MOS C–V
characteristics. The C–V curve is
called the quasi-static C–V
because Qinv can respond to the
AC signal as if the frequency were
infinitely low (static case).

Illustration of the MOS capacitor in all bias regions with the depletion layers shaded. (a)
Accumulation region; (b) depletion region; (c) inversion region with efficient supply of
inversion electrons from the N region corresponding to the transistor C–V or the quasi-
static C–V; and (d) inversion region with no supply of inversion electrons (or weak supply
by thermal generation) corresponding to the high-frequency capacitor C–V case.
OXIDE CHARGE—A
MODIFICATION TO Vfb AND Vt
• The basic MOS theory ignores the possible presence of electric charge in the gate
dielectric.
• Assuming surface charge, Qox (C/cm2), exists at the SiO2–Si interface, the band diagram
at the flat-band condition would be modified.

Flat-band condition (no band bending at body

surface) (a) without any oxide charge; (b) with Qox
at the oxide–substrate interface.
MOS Capacitor summary
Energy band diagrams of the two dominant types of
MOS capacitors. An N-type device is so named
because it has N-type inversion charge that increases
with a more positive Vg, and a P-type device has P-
type inversion charge increasing with a more negative
Vg.
MOSFET
Types of Transistors
 MOSFET
•Most important device in digital design

•Very good as a switch

•Relatively few parasitics

•Rather low power consumption

•High integration density

•Simple manufacturing

•Economical for large complex circuits

 INTRODUCTION TO THE MOSFET
• The two PN junctions are the source and the
drain that supplies the electrons or holes to
the transistor and drains them away
respectively.
• The name field-effect transistor or FET
refers to the fact that the gate turns the
transistor (inversion layer) on and off with an
electric field through the oxide.
• A transistor is a device that presents a high
input resistance to the signal source, drawing (a) Basic MOSFET structure and (b) IV
little input power, and a low resistance to the characteristics
• output
Depending on the
circuit, gate voltage,
capable the MOSFET
of supplying can be off conducting only a very small off-
a large
state leakage
current to drive current,
the circuitIoff ) or on (conducting a large on-state current, Ion).
load.
 MOSFET Structures

Cross section and circuit symbol for a p-

Cross section and circuit symbol channel enhancement mode MOSFET
for an
n-channel enhancement mode
MOSFET.

Cross section and circuit Cross section and circuit symbol for a p-
symbol for an channel depletion mode MOSFET
The enhancement-type MOSFET is the most widely used field-effect transistor

Operation with Zero Gate Voltage

The gate and the channel region of the MOSFET form a parallel-plate capacitor, with the
oxide layer acting as the capacitor dielectric.

The positive gate voltage causes positive charge to accumulate on the top plate of the
capacitor (the gate electrode).

The corresponding negative charge on the bottom plate is formed by the electrons in the
induced channel.

An electric field thus develops in the vertical direction.

It is this field that controls the amount of charge in the channel, and thus it determines the
channel conductivity and, in turn, the current that will flow through the channel when a
voltage vDS is applied.

This is the origin of the name “field-effect transistor” (FET).

For the MOSFET to conduct, a channel has to be induced.

Increasing vGS above the threshold voltage Vt enhances the channel, hence the names
enhancement-mode operation and enhancement-type MOSFET.

The current that leaves the source terminal (iS) is equal to the current that enters the drain
terminal (iD), and the gate current iG = 0.
Operation as VDS Is Increased
Consider the situation as vDS is increased.
Let vGS be held constant at a value greater than Vt ; that is, let the MOSFET be operated at a
constant overdrive voltage VOV .
vDS appears as a voltage drop across the length of the channel.

That is, as we travel along the channel from source to drain, the voltage (measured relative to
the source) increases from zero to vDS.

Thus the voltage between the gate and points along the channel decreases from vGs =Vt+VOV at
the source end to vGD =vGS −vDS =Vt +VOV −vDS at the drain end.

Since the channel depth depends on this voltage, and specifically on the amount by which this
voltage exceeds Vt , we find that the channel is no longer of uniform depth;

rather, the channel will take the tapered shape shown in Fig. 5.5, being deepest at the source
end (where the depth is proportional to VOV ) and shallowest at the drain end6 (where the depth
is proportional to VOV −vDS).
Cross section and ID versus VDS curve when VGS VT for (a) a small VDS
value, (b) a larger VDS value, (c) a value of VDS VDS(sat), and (d) a value of VDS
VDS(sat).
Small Signal Model of MOSFET
1. The small-signal equivalent circuit of a MOSFET is derived from its basic geometry, involving capacitances (Cgs and Cgd)
and resistances (rs and rd).

2. A simplifying assumption is made by grounding the source and substrate, streamlining the equivalent circuit.

3. Inherent capacitances (Cgs and Cgd) model gate-channel interaction, while parasitic capacitances (Cgsp and Cgdp)
account for gate overlap with source and drain contacts.

4. The drain overlap capacitance (Cgdp) impacts the device's frequency response, particularly affecting drain current
behavior.

5. Drain-to-substrate capacitance (Cds) is included in the small-signal equivalent circuit.

6. Series resistances (rs and rd) associated with source and drain terminals are considered in the circuit.

7. The small-signal channel current is controlled by the internal gate-to-source voltage through the transconductance.
8. The equivalent circuit for an n-channel common-source MOSFET includes total gate-to-source (CgsT) and total
gate-to-drain (CgdT) capacitances.

9. Channel length modulation introduces a finite rds, deviating from the ideal saturation region behavior.

10. A simplified, low-frequency equivalent circuit neglects series resistances (rs and rd), emphasizing the
dependence of drain current on the gate-to-source voltage.

11. Source resistance (rs) is considered in a simplified, low-frequency equivalent circuit, impacting transistor
characteristics.

12. The simplified model assumes an infinite input gate impedance at low frequencies.

13. Relevant figures, such as Figure 10.52, 10.53, and 10.54, visually represent the components and configurations
of the small-signal equivalent circuit.
Short Channel Effects:

As the channel length decreases, the fraction of charge in the channel region controlled by the gate decreases.
As the drain voltage increases, the reverse-biased space charge region at the drain extends further into the
channel area and the gate controls even less bulk charge. The amount of charge in the channel region, Q SD
(max), controlled by the gate, affects the threshold voltage and can be seen from Equation.
As the channel length decreases, the threshold voltage shifts in the negative direction so that an n-channel
MOSFET shifts toward depletion mode.
Channel Length Modulation:
• In the derivation of the ideal current-voltage relationship, channel length (L) was assumed constant.
• In saturation, the depletion region extends into the channel, reducing the effective channel length.
• Depletion width, influenced by bias, modulates the effective channel length with drain-to-source
voltage.
• This modulation effect is depicted in Figure 11.5 for an n-channel MOSFET.
• Depletion width extending into the p-region of a pn junction under zero bias is given by

For a one-sided np junction, essentially all of the applied reverse-biased voltage is across the low-doped
p region. The space charge width of the drain–substrate junction is approximately
Since the drain current is inversely proportional to the channel length, we may write
Subthreshold Conduction:

• Ideal current-voltage relationship predicts zero drain current when VGS ≤ VT.
• Experimentally, ID is not zero when VGS < VT, termed subthreshold current.
• Figure 11.1 compares ideal and experimental results.

• Figure 11.2: Energy-band diagram of MOS structure with p-type substrate.

 Bias: s = 2fp.
 Fermi level closer to conduction band, surface acts like lightly doped n-type material.

• Weak inversion condition: fp < s < 2fp.

• In weak inversion, expect some conduction between n-source and drain through a weakly
inverted channel.
• Crucial for accurate modeling and considers subthreshold leakage currents in electronic devices.
• Figure 11.3 displays surface potential along the channel for accumulation, weak inversion, and threshold with
a small drain voltage.
• P-substrate assumed at zero potential.
• Accumulation and weak inversion (Figure 11.3b, c) exhibit a potential barrier between n-source and channel,
requiring electrons to overcome for channel current.
• Comparison with pn junctions suggests channel current behaves exponentially with VGS.
• In inversion mode (Figure 11.3d), a small barrier makes the junction more ohmic, losing exponential
dependence.
• Actual derivation of subthreshold current is beyond this chapter's scope.
• If VDS is larger than a few (kT/e) volts, then the subthreshold current is independent of VDS