LAB REPORT 05 :
Omar chaib group:08
Introduction about digital system and vhdl :
Digital systems use binary data to power modern electronics,it is
important in all the modern tech , but how to use these data in a
digital system ? To give orders to the machine VHDL is a language
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used to design, simulate, and implement these systems. It enables
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the creation of efficient and reliable hardware. Key concepts
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include digital logic, VHDL syntax, simulation, and synthesis.,
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O THIS LAB :
OBJECTIVES FROM
1-This lab focuses on designing binary and BCD addition
circuits using MSI ICs, VHDL (structural and behavioral styles),
and schematic-based circuit design with buses, bridging
practical hardware and digital modeling techniques.
PART ONE :
ABOUT THE USED MATERIAL :
The( 7483A IC ) is an integrated circuit that performe a 4-bit binarry
addition it can be shown in ( fig01) , it is consist of 14 pin arranged in two
rows : pins from A(0),,,,A(3) ; B(0),,,,B(3) and S(0),,,,S(3) additionly vcc and
GND
EXPLANING HOW IT WORKS :
. Set up the Circuit: (according to fig 02)
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a i b Fig 01
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We connected the A and B inputs (4-bit binary numbers) using switches
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or constants (Vcc for 1 and GND for 0).
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We connected the carry-in (C0) input and set it to 0 (or another value for
testing carry propagation).
The output pins (S0-S3) displayed the 4-bit sum, and C4 showed the
carry-out.
2. Performed Addition:
Using the 7483A IC, we added two 4-bit binary numbers, A and B, and
observed the sum and carry-out results. This demonstrated how the IC
handles binary addition and the carry propagation. FIG 02
What we did in lab :
First of all we plug the circuit that is
shown in (fig03) , then we test our
circuit and the functionality of this
electronic device by :
First example : A = 0101 anb B =
0011 with C0 = 0 the out put is S =
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1000
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Second example : this one shows
the carry out behavior we have A = Fig 03
1100 and B = 1011 with C0 = 0 the
sum is S = 0111 and C4 = 1
We can see these sums by the leds
that display each output of the 4
bit sum
PART TWO :
In this lab we want to learn a technic that
helps us to simplify our circuits by using the
buses , ( the bus is a collection of related
signal lines that can be represented with a
thicker line to reduce complexity for example
A (3,,0) 3 down to zero Fig 04
In our experiment we created the needed
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circuit that is represented in( FiG04) ,
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and the 4 outputs ofm
the 4 inputs are simplified by this one bus A
O our logic circuit are
simplified by the bus F to have all the
combinations inside vectors
We created the truth table as a pre lab and
after simulating this circuit we verified that
our results are correct by using the wave
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function shown in (fig 05)
THE RIPPLE CARRY
THE ADDER (COMPONENT)
(THE GENERAL CODE )
PART THREE : library ieee;
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
In this experiment we are asked to entity full_adder is entity ripple_ca is
illustrates the 4 bit ripple- carry adder using port (x,y,z : in std_logic; port (c0,A0,A1,A2,A3,B0,B1,B2,B3:
4 interconnected full-adder component, s,c:out std_logic); in std_logic;
end entity; S0,S1,S2,S3,C4:out std_logic);
How this programme works !! architecture arch of full_adder is end entity ;
begin architecture arch of ripple_ca is
1. Each Full Adder: component full_adder is
s<= x xor y xor z;
Adds two input bits ( A0 and B0)
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c<=(z and (x xor y))or (x and y); port (x,y,z : in std_logic;
s,c:out std_logic);
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and the carry in bit to produce a sum and carry-out. end architecture;
end component;
a r c signal C1,C2,C3 : std_logic ;
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2. Ripple Carry: begin
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The carry-out from each full adder propagates
stage1: full_adder port map
(c0,A0,B0,S0,C1);
("ripples") to the next full adder as its carry-in. stage2: full_adder port map
(c1,A1,B1,S1,C2);
3. Final Output: stage3: full_adder port map
(c2,A2,B2,S2,C3);
The 4-bit sum (Sum[3..0]) and the final carry-out stage4: full_adder port map
(Cout) represent the result of adding the two 4-bit (c3,A3,B3,S3,C4);
inputs along with the initial carry-in (Cin). end architecture;
PART FOUR :
ADDER
In this experiment we are asked to
implement a full adder using direct
library ieee;
assignment statments , and to obsserve how use ieee.std_logic_1164.all;
ripple carry work use ieee.std_logic_unsigned.all;
How this programme works !! : entity ADDER is
port (A,B :in std_logic_vector (3 downto 0);
The VHDL addition circuit takes two 4-bit s:out std_logic_vector (3 downto 0);
inputs (A and B) and a 1-bit carry-in (Cin) to
G 0 8 c:out std_logic );
end entity ;
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produce a 4-bit sum (Sum) and a carry-out
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(Cout). Inputs are extended to 5 bits to
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architecture arch of ADDER is
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handle overflow, and arithmetic operations
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signal temp_s : std_logic_vector (4 downto 0);
begin
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are performed using the + operator. The
lower 4 bits of the result form the sum, and temp_s<='0'&A+B;
the highest bit becomes the carry-out. This c<=temp_s(4);
method simplifies binary addition by s<= temp_s(3 downto 0);
leveraging VHDL's built-in arithmetic end architecture ;
capabilities, ensuring efficiency and
accuracy.
PART FIVE : BCD ADDER
In this experiment we are asked to creat a vhdl code of
library ieee;
a one digit bcd adder ussing behavioral vhdl, the
use ieee.std_logic_1164.all;
program should check if any of the inputs is not in bcd use ieee.std_logic_unsigned.all;
format (>1001) the circuit must assign a high entity BCD_ADDER is
impedence to the circuit , so for this we created the port (X,Y: in std_logic_vector(3 downto 0);
folowing circuit and here is its explanation how it S: out std_logic_vector(3 downto 0));
works end entity ;
How this programme works : architecture arch of BCD_ADDER is
G 0 8 signal temp :std_logic_vector(4 downto
b
The BCD adder program performs the following:
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Input Validation: It checks if the two 4-bit inputs (A and B) are
0);
begin
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valid BCD numbers (0–9). If any input is invalid (greater than 1001) the
outputs are set to high impedance (ZZZZ), and an error signal is
temp<='0'&X+Y;
activated. O
. BCD Addition: If both inputs are valid, it adds them together. The sum
process (temp)
begin
is calculated, and if there is a carry (sum exceeds 9), the carry bit is set
if (temp >"01001")then S<="ZZZZ";
to '1'. If no carry occurs, the carry bit is set to '0'.
else S<= temp(3 downto 0);
3. Outputs:
end if ;
SUM: The 4-bit BCD result of the addition.
end process ;
CARRY: A signal indicating if there was a carry-out.
end architecture ;
ERROR: A signal indicating if the inputs were invalid.
THE ADDER
PART SIX : (COMPONENT)
In this experiment we aim to create the BCD THE CHEKER
library ieee;
adder that handles the overflow and invalid (COMPONENT )
useieee.std_logic_1164.use
input detection in the context of adding two library ieee;
bcd numbers, by choosing an apropriat use ieee.std_logic_1164.all; ieee.std_logic_unsigned.all;
method and we will explain how this circuit entity BCD_INVALID is entity ADDER is
works and how we mannaged to create it , port ( s1, s2, s3 , cout:in port (A,B :in
std_logic ; std_logic_vector (3 downto
How this programme work!!: co :out std_logic ); 0);
G 0 8 end entity ; c_in:in std_logic;
s:out std_logic_vector
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This programme is consist of two functional programms one architecture arch of
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to add and the other to checkk these two functions or lets
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BCD_INVALID is (3 downto 0);
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use more proffetional words are commponnents in the
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begin
cO<=cout or (s3 and (s2 or
c:out std_logic );
end entity;
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general code and this is how it works :
Two 4-bit binary adders to add the two BCD inputs (A andB).
s1 ));
end architecture ;
architecture arch of ADDER
is
An invalid-BCD detection circuit that checks whether the signal temp_s :
inputs are valid BCD (0-9 in binary). If they are not, the std_logic_vector (4 downto
outputs will be set to high impedance (ZZZZ). 0);
A correction logic that adds the value 6 (0110₂) to the binary begin
sum when the sum exceeds 9 (1001₂) or if a carry is temp_s<= '0'&A + B + c_in;
generated. c<=temp_s(4);
s<= temp_s(3 downto 0);
library ieee; THE GENERAL CODE Stage 3: ADDER port map (‘0’&cout2 & cout2 & ‘0’,
use ieee.std_logic_1164.all; s_out,’0’,s_out2,x);
use ieee.std_logic_unsigned.all; Out_put<=cout2&s_out2;
entity BCD_DETECTOR_WITH_INVALID is End architecture
port (A1,B1:in std_logic_vector(3 downto 0);
OUT_PUT :OUT std_logic_vector(4 downto 0);
cin: in std_logic);
end entity;
architecture arch of BCD_DETECTOR_WITH_INVALID is
component ADDER is
port (A,B :in std_logic_vector (3 downto 0);
c_in:in std_logic;
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s:out std_logic_vector (3 downto 0);
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c:out std_logic );
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end component ;
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component BCD_INVALID is
port ( s1, s2, s3 , cout:in std_logic ;
what are we going to do !!!
co :out std_logic );
end component ;
signal cout2,cout1,x :std_logic ;
signal s_out, s_out2: std_logic_vector(3 downto 0);
begin « ONLY A CONCLUSION »
stage1: ADDER port map (A1,B1,cin,S_out,cout1);
stage2: BCD_INVALID port map (S_out(1),S_out(2),S_out(3),cout1, cout2);
conclusion
In this lab we learned multiple technics that will help us in the future to solve some
dificult problem conserning degital systems cause we learn evry technic possible to solve
the adders and to simplify them in both coding and real life practices , we had agood
experience on how we check our circuits and how we simulate them for better and
accurate results , the lab was abuilding step to our understanding to the electronic
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devices behaviors hoping to go deeper in next labs and gain more understanding
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