Introduction to INTEL X86 Processor

(INTegrated ELectronics)

By

S. KESHAV MURTHY
CS & E, BIT
 Contents to be covered in Day - 1
• X 86 Family
• Features of 8086 – Architecture
• Pipelining in X86
• Addressing modes in 8086
• Instruction sets, Directives
• Interrupts
• Memory Interfacing (16-bit)
 About X-86
X -> 80, 801,802,803,804,805
PENTIUM (PENTA+IUM)
P-SERIES (P3,P6 For Multimedia, Parallel
Processing in a Pipeline)
Itanium(i) – New brand name(64-bit) to
meet needs of Internet driven activities for
Servers & Work Stations. It can executes
many instructions simultaneously(ILP)
 About X86 Processor Applications
8085 (8-bit) – small static Equipment's like for programming toys
signal light, display devices

8086(16-bit) – Processing Equipment's in industry for controlling

speed of motor, Temperature of furnace, washing m/c, ovens. In
RAM for placing the head of motor to read at any position
randomly using stepper motor driven by 8086

80186,80286,80386 – For data processing equipment’s (int i)

80486 – Data processing Real type with built-in co-processor
80487
80586 – Pentium for Desktop, Laptop, Servers etc.,
 Features of 8086
 It is a 16-bit processor. The width of ALU and data bus is 16-
bits.
 It has 20-bit address. Therefore maximum addressable
memory is 2^20 = 1MegaBytes.
 It has 40 pins and is a DIP package.
 The address and data lines are multiplexed to reduce the
number of pins.
 It works on a frequency of 5MHz/10/8Mhz. It depends on
external IC 8284 for frequency generation. 1 Sub division of
time is 0.2 micro seconds
 It is the first processor to support pipelining. The architecture is
divided into Execution unit (EU) and Bus interface unit (BIU) for
this purpose. BIU generates memory address and reads/writes
from memory/IO. EU executes instruction fetched by BIU.
 Logical memory partitioning
 The memory of 1MB is partitioned as 16, segments of 64KB each.
 One 64KB is used for storing program and is called “code seg”.
 One 64KB is used for stack and is called “stack seg”.
 One 64KB is used for storing data and is called “data seg”.
 One 64KB is used for additional data and is called “extra seg”.
 Memory address is represented as Base address:offset address
from programmers view.
 Base address provides the starting address of a segment and the
offset address provides the offset within the segment.
 Once base is initialized only the offset is to be provided in the
instruction that makes the size of instruction small.
Architecture of 8086
 Flag Register
• CF: It is set if there is a carry from the MSB position addition else its
reset
• ZF: It is set if the result of operation in ALU is zero else it is reset.
• PF: It is set if the no. of 1’s in a 8bit result is even else its reset.
• AF: It is set if there is a carry from lower digit to upper digit in a 8-bit
operation.
• SF: It is set if MSB is ‘1’ indicating negative result; it is reset if the MSB
is ‘0’ indicating positive result.
• TF: When set causes processor to operate in trace mode. When reset
causes the processor to execute in normal mode.
• IF: When set the maskable interrupts are enabled; when reset the
maskable interrupts are disabled.
• DF: When set the strings are accessed in decremental order i.e last
character to first; when reset the strings are accessed in incremental
order i.e. first character to last.
Registers
 Registers
 8086 CPU has 8 general purpose registers, each register has its own
name:
• AX - the accumulator register (divided into AH / AL): used as
accumulator (AX-16-bit / AL – 8-bit accumulator)
• BX - the base address register (divided into BH / BL): used as
pointer to data segment and holds offset address for data seg.
• CX - the count register (divided into CH / CL):Iterative code
segments using the LOOP instruction
• DX - the data register (divided into DH / DL):used as data register
for MUL and DIV instruction and for Specifying ports in some IN and
OUT operations
• SI - source index register:Can be used for pointer addressing of
data. Used as source in some string processing instructions
 Registers
• DI - destination index register: Can be used for pointer
addressing of data segment and extra segment. Also Used as
destination in some string processing instructions
• BP - base pointer: Primarily used to access parameters passed
via the stack. Offset address relative to SS
• SP - stack pointer:Always points to top item on the stack. It
holds the offset address relative to SS.
• Segment registers – 8086 has 4 segment register namely CS-reg,
DS-reg, SS-reg, ES-reg which holds the base address for the
respective segments.
• IP – Instruction pointer which holds the offset address for code
segment.
 ADDRESSING MODES
• Every instruction has 2 parts: a OPCODE and a OPERAND.
• OPCODE indicates the job to be done.
• OPERAND is the data on which the job is done.
• Addressing modes are the different ways of specifying the data and its
location in the instruction. The addressing modes can be viewed as
Data related addressing modes, program counter related addressing
modes and stack addressing modes.
• DATA RELATED AM:
The various data related addressing modes are :
1. Register AM 2. Immediate AM 3. Direct AM 4. Register indirect AM
5. Base plus indexed AM 6.Register Relative AM 7. Base plus
relative plus indexed AM 8. Scaled index AM (only in 80386 and
above)
 ADDRESSING MODES
• 1.Register AM: In this AM the data required for the operation is stored
in a register specified in the instruction. Add ax,bx
Syntax: Reg Data = (Reg) [read as content of
register ]
• 2.Immediate AM: In this AM the data required for the operation is
specified as a part of the instruction itself.add ax ,1243h
Syntax: n Data = n, itself
• 3.Direct AM: It is a memory addressing mode. The offset address of the
memory data is given as a part of the instruction.add ax,z
Syntax: [n] offset address : n address : DS:n
• 4.Register indirect AM: It is also a memory addressing mode. The
offset address of the memory data is stored in the register specified in
the instruction.add ax,[bx]
Syntax: [reg] Offset address = (Reg) Data = DS: (reg)
 ADDRESSING MODES
• 5.Register Relative AM: In this AM a displacement is mentioned in the
instruction along with the register. The offset address of the data is the
sum of the displacement and the content of the register.
Syntax: n[Reg] or [reg+n] offset address = n+(reg) Data =
DS:(n+(Reg))
• 6.Base + Indexed AM: In this AM the offset address is the sum of the
content of base register(BP, BX) and content of index register(SI,DI)
Syntax: [REGb][REGi] Offset address = (REGb)+(REGi)
• 7.Base + indexed + relative AM: It is a memory addressing mode. The
offset address of the memory data is the sum of base register, index
register and relative displacement.
Syntax: n [REGb][REGi] Offset address = (REGb)+(REGi)+n
• 8.Scaled Index AM: It is also a memory addressing mode.
Syntax: [reg1+n*reg2] Offset address = (Reg1)+n*(reg2)
 Program memory AM
• It is used with JMP and CALL instructions. There are 3 AM namely: direct,
relative and indirect.
• It is used during branching operation. To realize branching the value of
CS and IP has to be changed. There are 2 types of realization:
1. Intra segment or NEAR branch and 2. Inter segment or FAR branch.
• In case of intra segment branch the branching is between same segment
and hence only IP has to be changed. In case of inter segment branch
the branching is between 2 different segments and hence both IP and CS
have to be changed.
• Direct Program addressing:
In this case the address is stored in the instruction itself.
For eg. JMP [1000h]
 Program memory AM
• Direct AM in inter segment braching: In case of inter segment
branching the instruction is of 5 bytes as shown below:
Opcode Offset low Offset high Segment low Segment high

• Eg. JMP [10000h] will be coded as : Base = 1000h and IP = 0000

Opcode 00 00 00 10

• Relative program memory addressing: Here the branching is relative to

the IP. No inter segment is possible with relative AM. The instruction
will have a 8-bit (short) or 16-bit (near) displacement in the instruction.
The new value of the IP is obtained by adding the IP with the
displacement
i.e. (IP) = (IP) + displacement.
 Program memory AM
• Indirect Program AM: In case of intra segment indirect the register or
memory specified in the instruction gives the offset value for the
branching. i.e. JMP reg/mem
on execution (IP) = (reg/mem).
In case of inter segment indirect a memory is specified which is a 32-bit
memory. The 1st 16-bit number is taken to IP as the offset and the next
16-bit number to CS as the segment address.
i.e. JMP dword ptr mem
Mem+0 Offset low
(IP) = ( mem)
Mem+1 Offset high
(CS) = ( mem + 2)
Mem + 2 Seg low
Mem + 3 Seg high
 Stack memory AM
• Stack holds data temporarily and stores return addresses for procedures.
Stack works on LIFO basis.
• PUSH instruction is used to place data on the stack and POP instruction is
used to remove the data from stack.
• The stack is maintained by SS and SP where SS is the segment register for
the stack and SP is the offset address for the stack.
• While pushing data on the stack the SP is decremented and while poping
the SP will be incremented.
• The push sequence is :
a. The lower 8-bit of data is pushed at an location SS:(SP)-1
b. The upper 8-bit of data is pushed at a location SS : (SP) – 2
c. SP is readjusted as SP-2
 Stack memory AM
• The sequence of the poping is :
a. The content of the stack top pointed by SS : (SP) is brought the lower
8-bit of the destination.
b. The content of the stack top pointed by SS : (SP) + 1 is brought the
upper 8-bit of the destination.
c. The SP is readjusted as SP+2

• Data in stack are pushed or poped as 16-bit value only

• What is wrong with MOV [BX] , [D] ? Both the operands are memory
operands which is not possible.
• Select instruction for:
a. move 12h to AL ------------ MOV AL,12H
b. copy DS into AX ----------- MOV AX , DS
 Directives
• Assembler Directives: These are pseudo codes and helps the assembler
in the processes of conversion. These are transparent to the processor.
The commonly used assembler directives are :
• 1. DB: used to define a variable of byte size. It is equivalent of “char”
declaration in C-language. The usage format is <var> db <initl value>
eg. X db 23; x db 1,2,3,4 ; x db “kumar”
2. DW: used to define a variable of word size. It is equivalent of “int”
declaration in C-language. The usage format is <var> dw <initl value>
3.DD: used to define a variable of double word size. It is equivalent of
“long int” declaration in C-language. The usage format is <var> dd
<initl value>
4.DQ:used to define a variable of quad word size. The usage format is
<var> dq <initl value>
5.DT:used to define a variable of Ten byte size. The usage format is
<var> dt <initl value>
 Assembler directives
• 6.DUP operator: It is used to reserve memory and initialize with
common value. Eg. X db 20 dup(0)
7.proc and endp: These two directives are used to define a procedure
or subroutine. The usage format is :
<name> proc
|
| Body of the procedure.
|
<name> endp
8.EQU: It is used to define a symbolic constant. It does not require any
memory declaration. At the time of assembling the symbol is replaced
by the value. The usage format is : <Symbol> equ <constant>
9.ORG: It is used to change the offset address of the declaration below.
org 3000
 Assembler directives
• Segment and ends: Used to define a segment. The format of usage is
<name> segment
|
|
|
<name> ends
• Assume: used to assign a name of segment with its segment register
assume <segreg>:<name>
• There are 2 instruction formats: 16-bit form and 32-bit form.
16-bit form is used in 8086 systems and the 32-bit format is specific to
80386 and above processors.
 Types of instructions
• 1.Data transfer instructions: mov, xchg, pop, push, xlat, lea, les, lds, lahf,
• Sahf, pushf, popf, in, out.
• 2.Arithmetic instructions:add,adc,inc,sub,sbb,dec,aaa,daa,das,aam,aad.
• 3.Program exe. Transfer inst: call, jmp,ret(u/c), jz, jnz, jc,jnc(cond) etc.
• 4.Processor control inst: stc,std,clc,cld,sti,cli etc.
• 5.String instructions: movsb/w, cmpsb/w, stosb/w, lodsb/w, scasb/w.
• 6.Bit manipulation inst:and,or,xor,sal,shl,sar,shr,rol,ror,rcl,rcr.
• REG: The 3-bit field defines the register used as the first operand in the

REG 000 001 010 011 100 101 110 111

W=0 AL CL DL BL AH CH DH BH
W=1 AX CX DX BX SP BP SI DI

R/M Mod = 00 Mod = 01 Mod = 10 Mod = 11

000 (BX) + (SI) (BX) + (SI)+D8 (BX) + (SI) Same as
001 (BX) + (DI) (BX) + (DI)+D8 (BX) + (DI) REG field
defined
010 (BP) + (SI) (BP) + (SI)+D8 (BP) + (SI) above
011 (BP) + (DI) (BP) + (DI)+D8 (BP) + (DI)
100 (SI) (SI)+D8 (SI) +D16
101 (DI) (DI)+D8 (DI)+D16
110 DIRECT AM (BP) + D8 (BP) + D16
111 (BX) (BX) + D8 (BX) + D16
 Data Coding
• Obtain machine code for instruction : MOV DL , [DI]
Byte 1: 6 bits opcode – 100010
W-bit = 0 as it is a 8-bit operation
D-bit = 1 as the register operand is destination
Therefore Byte 1 is 100010 1 0 = 8A
Byte 2: MOD = 00 as the 2nd operand is memory without
displacement.
REG = 001 corresponding to DL register.
R/M = 101 corresponding to OA=(DI)
Therefore byte 2 is 00 010 101 = 15
Therefore the opcode of the instruction is
8A 15
 Data transfer using MOV
• The format for immediate addressing with MOV instruction is:

• Eg. MOV AX,1234h;move 1234h to AX register

• MOV instructions:
1. MOV segreg, reg 2. MOV reg , segreg
(segreg) (reg) (reg) (segreg)
3. MOV reg1/mem1 , reg2/mem2 4. MOV reg/mem, immdata
(reg1/mem1) (reg2/mem2) (reg/mem) data

Note: when memory is used in instruction 4 the size of the memory has
to be specified by using assembler directives byte ptr / word ptr /
dword ptr
 Data transfer instructions
• PUSH instruction: Possible push instructions are :
1. PUSH reg 2. PUSH mem 3.PUSHF 4. PUSHA 5. PUSH sreg
Note: With PUSHF the flag register is pushed on the stack and with
PUSHA instruction AX, CX, DX, BX, SP, BP, SI and DI in the same order
will be pushed.
The sequence of operation on push instruction are :
(SS: ( SP)-1) (Src upper byte)
(SS: (SP)-2) (Src lower byte)
(SP) (SP) - 2
• POP instruction : Possible pop instructions are :
1. POP reg 2. POP mem 3. POPF 4. POPA 5. POP sreg
The sequence is : (dst lower byte) (SS : (SP) )
(dst upper byte) (SS : (SP) + 1)
( SP ) ( SP ) + 2
 DATA transfer instructions
• What is the effect of following sequence: PUSH AX
PUSH BX
POP AX
POP BX
(same xchg ax,bx)
• Initialization of the stack:
sseg segment .model small
dw 100h dup (?) (OR) .stack 200h
sseg ends
• LEA instruction: It loads the effective address of the memory specified
into the register specified. LEA reg,mem
(reg) offset address of mem
It is used as a pointer initialization instruction.
 example
• Consider swapping of 2 data :
.model small
.data
data1 dw 2000h
data2 dw 3000h
.code
lea si,data1 ; si is the pointer to data1
lea di,data2 ; di is the pointer to data2
mov bx,[si] ; move data1 into bx
mov cx,[di] ; move data2 into cx
mov [si],cx ; move data2 to memory pointed by si
mov [di],bx ; move data1 to memory pointed by di
.exit
end
 Data tfr instructions contd….
• LDS and LES instruction:
instruction These load any 16-bit register with an offset
address and the DS, ES segment register with a segment address.
i.e. LDS reg, mem
(reg) = (mem)
( DS ) = (mem+2) LDS AX,DATA or LDS AX,X
• Exchange instructions:
a) XCHG ax, reg16 b) XCHG reg, reg/mem
(AX) (reg16) (reg) (reg/mem)
• LAHF SAHF
(AH) = ( flags lower byte) ( flags lower byte) = (AH)

• IN acc,portaddr8 IN acc,dx
(acc) (portaddr8) ex: IN DX,AL (acc) ((dx))
This is a fixed IO addressing (8-bit addr) This is a variable port addressing (16-bit
OUT DX,AX
addr)
 Instructions contd….
• XLAT: This is an instruction most suited for lookup table technique.
The offset address of memory is (BX) + (AL). On execution the data
from DS:OA is brought to AL register
i.e. (AL) ( DS : (BX) + (AL))
When to be used for the lookup table the following steps are to be
followed: 1. Prepare the table as per the requirement.
2. Make BX as pointer to the Table.
3. The number for which conversion is required is loaded in AL

4. Execute XLAT instruction and the result will be in AL.

Eg. BCD to ASCII conversion.
BCD 0-9 corresponds to 30h – 39h in ASCII. Lea bx,table address
30h
Mov al,number;al=01h 31h
Xlat ;al=31h ¦
Step1: look up table: 39h
 Instruction contd…
• Step 2: LEA BX,table Step 3: MOV AL,num Step 4: XLAT
Program:
.model small
.data
table db 30h,31h,32h,33h,34h,35h,36h,37h,38h,39h
num db 04
res db 00
.code
lea bx, table ;start addr. of table to BX
mov al, num ;al=04
xlat ;al=34h
mov res , al
.exit
end
 String instructions
• During the string operations the source string is always addressed by
DS as segment base and SI as offset, the destination string is always
addressed by ES as segment base and DI as offset.
• If during string operation the Direction-Flag (DF) = 0 the pointers Si and
DI are incremented after the operation. If DF = 1 the pointers SI and
DI are decremented after the operation.
• LODS instruction: It loads a string/character from source to
accumulator. LODSB causes a byte to be loaded to AL-register and
LODSW causes a word to be loaded to AX-register.
i.e. LODSB ----- (al) (DS:SI)
after if DF=0 SI=SI+1; DF=1 SI=SI-1
LODSW >>>>> (ax) (DS:SI)
after if DF=0 SI=SI+2; DF=1 SI=SI-2
LODSD is possible in 80386 and above processor
 String instruction
• STOS instruction: It stores the accumulator content to the destination.
STOSB causes a byte to be loaded from AL-register to memory pointed
by ES:DI and STOSW causes a word to be loaded from AX-register to
memory pointed by ES:DI.
i.e. STOSB ----- (al) (ES:DI)
after if DF=0 DI=DI+1; DF=1 DI=DI-1
STOSB >>>>> (ax) (ES:DI)
after if DF=0 DI=DI+2; DF=1 DI=DI-2
STOSD is possible in 80386 and above processor.
REP prefix can be used with STOS instruction which causes the
instruction to be repeated until the count in CX ! = 0 i.e. The value of
CX will be decremented by 1 and if not equal to zero the instruction
STOS is repeated.
 String instructions
• A video text memory begins from B800:0000, There are 25 X 80
character per line and each character has 2 bytes. The first byte is the
ascii of character. The 2nd byte is the attribute. Write a program to
clear the screen.
SOLN: The attribute is 07 (white text on a black background)
The ascii of space is 20h
.model tiny
.code
mov ax,0b800h
mov es,ax
mov di,00
mov cx,25*80
mov ax,0720h
REP stosw
.exit
 String instructions
• MOVS instruction: It moves a character from source string to
destination string.
i.e MOVSB (ES:DI) (DS:SI)
After if DF=0 SI++ , DI++ ; DF=1 SI-- , DI—
MOVSW (ES:DI) (DS:SI)
After if DF=0 SI=SI+2, DI=DI+2
=1 SI=SI-2, DI=DI-2
REP prefix can be used with MOVS instruction.

PBLM: write program to move value of location B800:00A0 to

B800:0000 , a total of 24*80 characters.
SOLN: The above program in continuation with the previous program
can be used to scroll the page in the new location.
 String instruction
• .model tiny
.code
cld
mov ax, 0b800h
mov ds, ax
mov es, ax
mov si, 00A0h
mov di, 0000
mov cx, 24*80
REP movsw
.exit
end
 Questions on DATA move instructions
• Q1: Develop a near procedure that stores AL in four consecutive
memory location within data segment addressed by DI-reg.
movemem proc near
mov cx,04
ag: mov [di],al
inc di
dec cx
jnz ag
ret
movemem endp
 Questions on DATA move instructions
• Q2: Develop a far procedure that copies contents of the word-sized
memory location CS:DATA1 into AX,BX,CX,DX,SI
movemem proc far ;start procedure
mov ax,seg
mov cs,ax
lea di,data1
mov ax,[di]
mov bx,[di]
mov cx,[di]
mov dx,[di]
mov si,[di]
ret
movemem endp ;end of procedure
 Logical instructions
• AND operation: It is used for performing logical AND operation on the
two operands.
The possible formats and instructions are:
1. AND reg2 ,reg1 2. AND reg/mem, immdata
3. AND mem,reg 4. AND reg ,mem.
• AND operation can be used for clearing a bit or masking a bit of a given
register or memory. For eg. If A7 , A5 , A2 of CL-reg to be cleared:
A7 A6 A5 A4 A3 A2 A1 A0
& 0 1 0 1 1 0 1 1 = 5b

Therefore instruction is :

AND CL , 5bh
 Logical instructions
OR instruction: The possible instructions in OR gate operations are:
1. OR reg2 ,reg1 2. OR reg/mem, immdata
3. OR mem,reg 4. OR reg ,mem.
OR instruction can be used for setting a bit of a register or memory.
XOR instructions: The possible instructions in XOR gate operations are:
1. XOR reg2 ,reg1 2. XOR reg/mem, immdata
3. XOR mem,reg 4. XOR reg ,mem.
XOR instructions can be used for complimenting a bit of a register or
memory.
NOT and NEG: NOT instruction is used to get 1’s compliment of the
operand. Instruction is NOT reg/mem.
NEG instruction is used to get 2’s compliment of the operand.
Instruction is NEG reg/mem
 Logical instructions
• TEST and BIT test Instruction: TEST instruction performs AND operation
between the 2 operands and then flags are affected based on the result,
but the result is discarded. TEST instruction is followed by JZ ( Jump if
Zero) or JNZ(Jump if not Zero) instruction.
eg. Test whether bit 0 of al-reg. If the bit = 1 branch to RIGHT
TEST AL,1
JNZ RIGHT
• Write a program to clear D0,D1 ; set D2,D3; compliment D6,D7 of a 8-
bit memory data.
i/p: D7 D6 D5 D4 D3 D2 D1 D0
O/P: D7 D6 D5 D4 1 1 0 0
Setting is achieved by OR operation; Clearing by AND operation ;
Complimention by XOR operation.
 Logical instructions
• .model small
.data
num db 24h
res db 0
.code
mov ax,@data
mov ds,ax
mov al,num
and al,0FCh; To clear D0,D1;FCh= (1111 1100)
or al,0Ch ; To set D2,D3
xor al,0C0h ; To compliment D6,D7
mov res,al
.exit
end
 Shift and Rotate
• Shift instructions move bits in a register or memory left/right. A Left
shift performs a multiplication in power of 2n and a right shift gives
quotient of division by power of 2n . The instructions of shift are:
Cy Register or memory
SHL/ 0
SAL

SHR 0 Cy

SAR Cy
 Shift and rotate instruction
• All rotate and shift instructions can be performed once or ‘n’ times. If to be
performed once the syntax is : SHL AX,1
If the operation is to be performed ‘n’ times then the value of ‘n’ is to be
loaded into CL-register. Eg. SHL AX,CL
• Rotate instrutions:
ROL

RCL ROR

RCR
 Logical instructions
• Write a program segment to multiply ax by 10.
SHL AX,1 ; Multiplication by 2
MOV BX,AX ;
SHL AX,2 ; Multiplication by 8
ADD AX,BX

• Write a program segment to multiply AX by 5.

MOV BX,AX ; (BX) = NUM
SHL AX,2 ; (AX) = NUM*4
ADD AX,BX ; (AX) = NUM*4 + NUM = NUM*5
 String comparisions
• SCAS: It scans the character in accumulator with the string pointed by
ES:DI. SCASB instruction compares AL with memory string while
SCASW compares AX with the memory string. DI is incremented or
decremented as per the DF. REPE/REPNE prefix can be used.
• REPE repeats the operation until the contents of CX =0 without
affecting the flags or until an unequal condition exists.
• REPNE repeats the operation until the contents of CX =0 without
affecting the flags or until an equal condition exists.
• Eg. To find the character ‘A’ in a string
MOV CX,LEN
CLD
MOV AL,’A’
REPNE SCASB
 String comparisions
• CMPS: It is used to compare 2 strings pointed by DS:SI and ES:DI. The
pointers are appropriately incremented or decremented based on DF.
• REPE and REPNE prefix can be used with CMPS. CMPSB is used to
compare 2 strings of byte size while CMPSW is used to compare 2
strings of word size.
• e.g. To check for 2 string of 10 character for equal/notequal
LEA SI,SRC
LEA DI,DST
MOV CX,CNT
CLD
REPE CMPSB
 Arithmetic instructions(1)
1. ADD reg2 , reg1 2. ADD reg/mem,data
(reg2) = (reg1) + (reg2) (reg/mem)=(reg/mem)+data

3. ADD reg, mem 4. INC reg/mem

(reg) = (reg) + (mem) (reg/mem)= (reg/mem) + 1
Write a near procedure to add AX,BX,CX,DX
ADDS PROC NEAR
ADD AX,BX
ADD AX,CX
ADD AX,DX
RET
ADDS ENDP
NOTE: All ADD instructions affects all flags, but INC instruction affects all
flags except CY-FLAG
 Arithmetic instructions(example)
• Write a procedure to add numbers in location X and X+1(x,x+1 are words -DW)
SUMS PROC NEAR
LEA DI,X

MOV AX,00
ADD AX,[DI]

ADD AX,[DI+2]
RET
SUMS ENDP
• Write a procedure to add 2 numbers at X and X+1(x,x+1 are bytes db)
SUMS PROC NEAR
LEA DI,X
MOV AL,00
ADD AL,[DI]
INC DI
ADD AL,[DI]
RET
SUMS ENDP
 Arithmetic Instructions(2)
Addition with carry: It is used to add numbers wider than 16-bits.
ADC reg2,reg1;adc ax,bx ADC reg/mem,data
(reg2) = (reg2) + (reg1) + Cy (reg/mem) = (reg/mem)+ data+ Cy
ADC reg,mem;adc ax,z;(ax)+z+(cy)ax
(reg) = (reg) + (mem) + Cy
Write a procedure to add 2, 32-bit numbers
SUMS PROC
LEA DI,X MOV CX,AX
LEA SI,Y RET
MOV AX,[DI] SUMS ENDP
ADD AX,[SI]
MOV BX,AX
MOV AX,[DI+2]
ADC AX,[SI+2]
 Subtraction instructions
• 1. SUB reg2 , reg1 2. SUB reg/mem,data
(reg2) = (reg1) - (reg2) (reg/mem)=(reg/mem)-data
(d) <-- (s) –(d)
3. SUB reg, mem 4. DEC reg/mem
(reg) = (mem) - (reg) (reg/mem)= (reg/mem) - 1

5. SBB reg2,reg1 6. SBB reg/mem,data

(reg2) = (reg1) - (reg2) - Cy (reg/mem) = (reg/mem)- data- Cy

7. SBB reg,mem
(reg) = (reg) - (mem) - Cy
ex1. sub ax,bx ex2.sub ax,1234 ex3.sub ax,z ex4.dec ax
 Comparision instruction
• CMP instruction is used to compare 2 operands and is used to determine
the relation between the 2 operands. It basically subtracts 2 numbers and
flags are affected and the result is not saved.
CMP op1,op2; cmp ax,bx
After CMP instruction
if CF=1 then op1 < op2 ; if ZF=1 then op1 = op2
CF=0 then op1 ≥ op2
The various instructions are CMP REG2,REG1
CMP REG,MEM
CMP REG/MEM,DATA
The conditional jumps after CMP are JA , JB, JAE, JBE
e.g. to check al<=10
cmp al,10
jbe lesseq
 Multiplication and Division
• MUL src ;dest is accumulator by default
If src is 8-bits then (Ax) = (al) * (src)
If the upper part of the product = 00 then CF=OF=0
If the upper part of the product ≠ 00 then CF=OF=1
If src is 16-bits then (DX_AX) = (ax) * (src)
If the upper part of the product = 0000 then CF=OF=0
If the upper part of the product ≠ 0000 then CF=OF=1
• IMUL src
It is similar to MUL but is used for signed multiplication. In case of
signed multiplication the result ,if negative, will be stored in its
equivalent 2’s compliment form.
To perform 5*10 mov bl,5;move 05 to BL
mov al,10
mul bl; AL*BL->AL
 Division
• In case of Division instruction (DIV or IDIV) the numerator should be
double the size of the denominator. i.e. it is a 16-bit by 8-bit division or
32-bit by 16-bit division.
• DIV src and IDIV src
If the src is 8-bits then (AH_AL) = (AX) / (src) with AH = rem & AL=quo
If the src is 16-bits then (DX_AX) =(DX_AX)/(src) with DX =rem & AX=quo
• There are 2 possible types of errors from a division operation: Divide by
zero and Divide overflow.
• Divide overflow occurs when the result exceeds the storage size of the
destination register . E.g. if 1500 is to be divided by 2 then the quotient
is 750 and can’t be stored I al-register as it is only a 8-bit register.
• Eg. If AX=0010h (+16) and BL=FDh(-3) then after IDIV AL=FBh (-5) and
AH = 1.
 Division
• To make the numerator double size for unsigned numbers make (ah) =
00 and (DX) = 0000.
• To reliaze the same in signed number it is necessary to have a sign
extention. Instructions CBW and CDW are used.
CBW(Convert byte to word) sign extends AL to AH
CWD(Convert word to double word) sign extends AX to DX.
• write a program segment to divide a number at X by no. at X+1
A) UNSIGNED NUMBER B)SIGNED NUMBER
MOV AL,X MOV AL,X
MOV AH,0 CBW
DIV X+1 IDIV X+1
MOV ANSQ,AL MOV ANSQ,AL
MOV ANSR,AH MOV ANSR,AH
 BCD & ASCII Arithmetic
DAA : After the addition of 2 bcd numbers the result will be in
hexadecimal. To get a packed decimal result DAA is used. It works on
AL-register only and can be used only after 8-bit addition.
e.g. addition of 2, 16-bit BCD numbers(sum in ch+cL)
mov dx,3099h
mov cx,1234h
mov al,cl
add al,dl ;al=cd h=33d and cy=1
daa ;al=33 ,cy=1
mov cl,al
mov al,ch
adc al,dh
daa
mov ch,al
 BCD & ASCII instructions
• DAS : After the subtraction of 2 bcd numbers the result will be in
hexadecimal. To get a packed decimal result DAS is used. It works on
AL-register only and can be used only after 8-bit subtraction.
e.g. sub of 2, 16-bit BCD numbers
mov dx,3099h
mov cx,1234h
mov al,cl
sub al,dl
das
mov cl,al
mov al,ch
sbb al,dh
das
mov ch,al
 ASCII arithmetic
There are 4 ascii instructions namely:AAA, AAS, AAM, AAD. These
instructions sets the result to the unpacked bcd which can be converted
to ascii easily by adding 30h which is ascii of 0.
AAA: It adds 2 decimal digit and gives unpacked result in AH and AL
registers. E.g. 7+8 = 0fh on using AAA ; AH = 01 and AL = 05 Now
by adding 30h to AL and AH the number can be converted to ASCII.
MOV AL,07
ADD AL,08
AAA
ADD AX,3030H
AAS: It acts similar to AAA but is used after subtraction of 2 BCD digits.
AAM: After multiplication the result in AL will be hexadecimal. AAM
instruction converts the hexadecimal result into unpaked BCD in AH and
AL.
e.g. 07*08 = 56d = 38h on executing AAM AH=05 and AL=06
 ASCII instructions
AAD: This instruction converts the unpacked BCD digits in AH and AL into
a packed hexadecimal number in AL.
e.g. If (AH)=08 (AL)=05 using AAD (AL) =85h
Write a program to display the number in AL in decimal form.
DOS interrupt 21h function code 02 is used for display of a character.
I/p: (AH) = 02 and (DL) = ascii of the character to be displayed.
.model tiny |
.code |
mov al,48h | int 21h
aad | pop ax
div ax,3030h | mov ah,02
mov dl,ah | mov dl,al
push ax | int 21h
mov ah,02 | .exit
 Review questions
• If (AX)=1001h and (DX)=20FFh what is the result and the flag values
0001 0000 0000 0001
+ 0010 0000 1111 1111
----------------------------------
0011 0001 0000 0000 = 3100h
Flags: CF=0, ZF=0, OF=0, AC=1, PF=0, SF=0
• Select an instruction that tests bit position 2(d3) of register ch flag z is
modified based on bit3.if d3 is 0,zf=0,else zf=1.
TEST CH,04 (same as AND, dest.is not altered)
• Select an instruction to move DH register right one place, making sure
the sign of the result is the same as the sign of the original number.
SAR DH,1
 Processor control instructions
Flag control instructions:
CLD --- clear direction flag STD --- set direction flag,DF=1
CLI ---- Clear interrupt flag STI --- set interrupt flag
CLC ---- Clear Carry flag STC --- set carry flag
CMC --- Compliment carry flag.
Miscellaneous instructions:
WAIT: causes the processor to go to wait state and comes out of wait
state when TEST pin = 0
HLT : causes the processor to terminate all the tasks and go to halt
state. The processor can be restarted by interrupt or reset.
NOP: It is a no operation instruction which causes the processor to
pause for a short time only.
LOCK prefix: when used with an instruction causes LOCK pin to go low
until the instruction is completed. E.g. LOCK MOV AX,DX
ESC: When executed the opcode is given to co-processor for execution.
 Program control instruction
• Branching instruction: The value of program pointers (CS and IP) have to
be changes to realise branching. There are 2 types of branching
operations namely : Conditional and unconditional branching.

• Conditional branching: Has a condition based on flags. If the condition

is true it branches to the label specified by changing the values of IP and
if the condition is false then branching does not occur i.e. IP is not
changed. All conditional branching instructions are intra segment or
near branching.

• Unconditional branching: These instructions have no condition. On

execution the value of IP and CS are changed. These can be intra
segment /near branching or inter segment / far branching.
 Program control instructions
• Unconditional jump (JMP): This instruction causes a branching to the
label without any conditions. There are 3 types possible namely:

Short jump: In this case a 8bit signed number is specified in the

instruction. The new value of IP is calculated as current IP + 8-bit no.
i.e. (IP) = (IP) + 8-BIT SIGNED NUMBER
eg. JMP SHORT NEXT
(offset is -128 to +127 one byte)
NEAR Jump: It is similar to short jump but the size of the signed
number/displacement is 16 bits.

indirect JMP: JMP reg/mem

(IP) = (reg/mem)
 Program control instructions
 FAR Jump: In this case the branch is between 2 different code segments. Hence
both CS and IP has to be changed.
FAR JMP Direct: JMP far ptr next
This instruction is coded into a 5 byte instruction

Opcode Offset low Offset high Segment low Segment high

FAR jump indirect: Indirect Program AM: In case of intra segment indirect the
register or memory specified in the instruction gives the offset value for the
branching. i.e. JMP reg/mem
on execution (IP) = (reg/mem).
In case of inter segment indirect a memory is specified which is a 32-bit
memory. The 1st 16-bit number is taken to IP as the offset and the next 16-bit
number to CS as the segment address.
i.e. JMP dword ptr mem
(IP) = ( mem)
(CS) = ( mem + 2)
 Program control instructions
• Conditional jumps: These are always inter segment branching only.
Jcondition label
If the condition is true
(IP) = (IP) + DISPLACEMENT
else
(IP) = unchanged.
• The conditions are based on flags. The flags involved in the conditions are
ZF, CF, PF, OF and SF.
• The various instructions with the condition satisfied and condition unsatisfied
values are given in the table in the next slide:
• E.g. JNC label
If Cy=0
(IP) = (IP) + DISPLACEMENT
else
(IP) = unchanged.
Program control instructions
Instruction Condition safisfied Condition fails
JZ / JE LABEL ZF = 1 ZF = 0
JNZ / JNE LABEL ZF = 0 ZF = 1
JNC LABEL CF=0 CF=1
JC LABEL CF=1 CF=0
JS LABEL SF=1 SF=0
JNS LABEL SF=0 SF=1
JO LABEL OF=1 OF=0
JNO LABEL OF=0 OF=1
JP LABEL PF=1 PF=0
JNP LABEL PF=0 PF=1
JCXZ LABEL CX=0 CX ≠ 0
 Program control instructions
Instruction Condition satisfied Condition fails
INSTRUCTIONS USED AFTER UNSIGNED OPERATION
JBE LABEL CF=1 OR ZF=1 CF = 0 AND ZF=0
JB LABEL CF = 1 CF = 0 OR ZF = 1
JA LABEL CF = 0 AND ZF = 0 CF = 1 OR ZF = 1
JAE LABEL CF = 0 CF = 1
INSTRUCTION USED AFTER SIGNED OPERATION
SF ⊕ OF = 1 AND ZF SF ⊕ OF = 0 OR ZF
=0 =1
JL LABEL

JLE LABEL SF ⊕ OF = 1 SF ⊕ OF = 0
SF ⊕ OF = 0 AND SF ⊕ OF = 1 OR
ZF=0 ZF=1
JG LABEL

JGE LABEL SF ⊕ OF = 0 SF ⊕ OF = 1
 Program control instructions
• Write a procedure to search a character 0Ah in a string of 100
characters. If found return with CF = 0, if not found return CF=1
SCAN PROC NEAR
MOV CX,100;counter
MOV AL,0AH;char to search
LEA DI,STRING; destination string
CLD
REPNE SCASB
JCXZ NF
CLC;return with CF=0,found
RET
NF: STC;return with cf=1;not found.
RET
SCAN ENDP
 Program control instructions
• LOOP instruction: It is a combination of DEC CX followed by JNZ.
It decrements the value in CX-register by 1 and if the value of CX ≠ 0
then it causes a branching to the label specified.

• PROCEDURES: The procedures or subroutines are a group of

instructions that perform a task and which is to be reused . It gives
modularity in the programming. CALL instruction is used to call
procedure and RET instruction to return from the procedure to the
main program.
• CALL instruction: It saves the contents of the program pointers (CS and
IP) before modifying the value . The value saved is called RETURN
ADDRESS. The various NEAR CALL instructions possible are:
CALL NEAR LABEL; CALL REG/MEM
The various FAR CAL instructions possible are:
CALL FAR LABEL CALL DWORD PTR MEM
 Program control instructions
• RET instruction: In case of NEAR RET it pops the stack top value on to
IP and returns to the main program after completion of the procedure.
In case of FAR RET it pops the stack top values to IP and the next stack
top values to CS-register.
• Write a procedure that cubes the contents of CX register. This
procedure may not affect any other register except CX.
• Since none of the registers are to be affected in the procedure 1 st all
possible registers to be used and after the logic is performed move the
result into CX and retrieve the values into the respective registers.

The cubing is realized by (cx) * (cx) * (cx)

 Program control instructions
• cube proc near
push ax
mov ax , cx ; (ax) = cx
mul cx ; (ax)*cx = cx2
mul cx ;(ax)*cx = cx3
mov cx , ax
pop ax
ret
cube endp
 Interrupts
• Interrupts are either a hardware-generated CALL or a software
generated CALL. An internal interrupt due to some internal event is
called EXCEPTION. The software interrupt instructions are INT, INTO,
INT3.
• During interrupt on occurrence of interrupt the processor saves the
return address from CS and IP on to the stack, the flag register is also
saved on to the stack and branches to the subroutine corresponding to
the interrupt type.
• All interrupts are coded by a 8-bit vector or type code. In memory a
table called IVT (Interrupt Vector Table) is maintained in which the
address of the subroutine for a particular vector or type code is pre-
stored.
• The table has four location per vector code and max of 2 8 = 256 vector
codes numbered as 00 – FF h. Therefore the size of the IVT is = 256*4 =
1024 bytes i.e. 1 K Bytes from location 00000 - 003FFh.
•
Interrupts
The organization of the IVT is given below:
00000 offset address of the
Interrupt subroutine

CODE 00001

00 00002 segment address of the

Interrupt subroutine
00003
: :
: :
type 003FC offset address of the
code 003FD Interrupt subroutine

FF 003FE seg address of the

003FF Interrupt subroutine

• In protected mode the 4 byte IVT is replaced by a 8-byte Interrupt Descriptor

table discussed in chapter 1.
 Interrupts
• The vector codes and its usage with the address in IVT is given below:
Vector code address in IVT μP Function
0 00-03 ALL Divide zero error
1 04-07 ALL Single step
2 08-0b ALL NMI
3 0C-0F ALL Breakpoint
4 10h-13h ALL Intrpt on overflow
5 14h-17h 80186 Bound instruction
- P4
: : : :
: : : :
20 - FF 80h – 3FF ------- User intrpts
 Interrupts
The interrupt sequence is given below:
1. On occurance of interrupt the processor accepts it and gets the
8-bit vector code. Let the vector code be nn.
2. The flag register value is pushed on the stack.
3. TF = IF = 0
4. Push CS-reg on to the stack.
5. Push IP onto the stack.
6. From IVT address 4*nn get the new offset address to IP-reg.
7. From IVT address 4*nn + 2 get the new base offset address to CS-reg.
8. Branch to the new location as pointed by CS and IP.
 Interrupts
The various software interrupt instructions are :
1. INT nn: The instruction allows the user to specify the vector code 00-FF
in the instruction. On execution an interrupt of type code nn is
activated as per the sequence explained before.

2. INTO : Interrupt on overflow. It is a conditional interrupt instruction. If

OF=0 then interrupt is not activated. If OF=1 then it causes a interrupt
of type code 04

3. INT3: Its used as a breakpoint. It causes an interrupt of type code 03

when the instruction is executed.

4. IRET: It’s the last instruction of a interrupt subroutine. It pops from the
stack into IP, CS, and flag register in the same order.
BIOS Int 10h(Interrupt for Monitor)

Syntax:Mov ah,function number

Int 10h
Function number: 02h to move cursor(go)
06h to clear screen(clrscr)
Provide start address in CX(row in ch,col in cL)
Destination address in DX(row in dh,col in dL)
BIOS Int 21H for (SWInterrupt for DOS Operating System)

Syntax:
Mov ah,function number in AH
Int 21h
Function number in AH is
01h read a char AL
02h to print a char <-DL
09h to print name DX
0Ah to accept name->DX
 Memory interface
• The most common types of memory are: ROM, Flash ROM, SRAM and
DRAM
• Memory pin connection:
Address Connections: The number of pins required for addressing is
obtained by expressing the memory capacity as power of 2. The power
value is the number of lines required.
eg. Memory capacity = 16KBytes
Expressing as a power of 2 we get 16KBytes = 2 14 .Therefore 14 lines
are required for addressing, typically marked as A0 – A13
(Range of address is 00000h to 03FFFFh)

Data connections: These are the pins through the data is read or written
into the memory. It is labelled as D0 to D7.
Memory are expressed as M X N where M represents the no. of
locations and N represents the bits per location.
 Memory interface
• Memory connections contd…….
Selection connections: Each memory device will have a enable signal
called chip select / chip enable / select. It has to be selected to enable
the memory IC. Generally the address lines are used for selection.

Control connections: For ROM there will be only one control signal
called Output enable(OE) where as the RAM will need 2 control signals,
one to read and other to write. These signals are controlled by the
processor through the memory interface.

• ROM memory:
It is a read only memory and permanently stores programs and data
that are resident to the system. It is a non-volatile memory The types of
ROM memory available are : PROM, EPROM, EEPROM, Flast ROM etc.
 Memory interface
• The EPROM IC has a number a 27XXX where XXX represents the
number of Kilo bits storable in the IC
E.g, If the IC is 2732 It indicates that 32Kbits or 4KBytes of data can be
stored.
If the IC is 271024 the capacity is 1024kbits or 128KBytes.

• Similarly Static RAM has starting with 6XXX and DRAM with 4xxx
• In case of dynamic RAM a signal for refreshing the memory value is
required apart from the regular pins for address, data, selection and
control.
• ADDRESS DECODING: To interface memory to microprocessor, it is
necessary to decode the address sent from the microprocessor. It
makes the memory function at a unique section of memory. Without
decoding only one memory device can be connected to the processor.
 Memory interface
• Simple NAND gate Decoder:
A NAND gate can be used as a decoder to enable the Chip selection of a
memory IC. Generally CE is a low output. Hence NAND is preferred.
NAND provides a low output when all its input are high.
Method of decoding using NAND:
1. Identify the lines of address required based on the memory size.
2. From A0 separate that many lines as identified in step 1.
3. The remaining address lines through NAND gate is used for Chip
selection.

Eg. Interface a 2K * 8 EPROM for a address range of FF800 to FFFFF

For 2K locations 11 address lines are required. i.e A0 to A10.
The remaining bits A11 to A19 is used for chip select.
 Memory interface
• Expanding the address
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
FF800 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
FFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
The blue bits are used for chip enable and the red are used for
addressing 2K locations
A11
Memory Map

0
1

0
1
Diagram interfacing 64K RAM &
64K ROM
 Thank you

Any Question…….. ?