 A hardware description language (HDL) is a

computer-based language that describes

the hardware of digital systems in a textual
form.
 2 common HDLs

◦ Verilog
◦ VHDL (Very high-speed integrated circuit
hardware description language)
• HDL is a Documentation language.
• It resembles an ordinary computer
programming language, such as C, but is
specifically oriented to describing hardware
structures and the behavior of logic circuits.
• It can be used to represent logic diagrams,
truth tables, Boolean expressions, and complex
abstractions of the behavior of a digital system.
• It describes a relationship between signals that
are the inputs to a circuit and the signals that
are the outputs of the circuit.
HDLs are used in several major steps in the
design flow of an integrated circuit:
 Design entry
 Functional simulation or verification,
 Logic Synthesis,
 Timing Verification,
 Fault Simulation
• Design entry creates an HDL-based
description of the functionality that is to be
implemented in hardware.
• Depending on the HDL, the description can
be in a variety of forms: Boolean logic
equations, truth tables, a netlist of
interconnected gates, or an abstract
behavioral model.
• The HDL model may also represent a
partition of a larger circuit into smaller
interconnected and interacting functional
units.
• Logic simulation displays the behavior of a digital system
through the use of a computer.
• A simulator interprets the HDL description and either produces
readable output, such as a time-ordered sequence of input and
output signal values, or displays waveforms of the signals.
• The simulation of a circuit predicts how the hardware will
behave before it is actually fabricated. Simulation detects
functional errors in a design without having to physically
create and operate the circuit.
• Errors that are detected during a simulation can be corrected
by modifying the appropriate HDL statements.
• The stimulus(i.e., the logic values of the inputs to a circuit) that
tests the functionality of the design is called a test bench.
• Thus, to simulate a digital system, the design is first described
in an HDL and then verified by simulating the design and
checking it with a test bench, which is also written in the HDL.
• Logic synthesis is the process of deriving a list of
physical components and their interconnections (called a
netlist ) from the model of a digital system described in
an HDL.
• The netlist can be used to fabricate an integrated circuit
or to lay out a printed circuit board with the hardware
counterparts of the gates in the list.
• Logic synthesis is similar to compiling a program in a
conventional high-level language.
• Logic synthesis produces a database describing the
elements and structure of a circuit.
• The database specifies how to fabricate a physical
integrated circuit that implements in silicon the
functionality described by statements made in an HDL.
• Logic synthesis is based on formal exact procedures that
implement digital circuits and addresses that part of a
digital design which can be automated with computer
software.
• Timing verification confirms that the fabricated,
integrated circuit will operate at a specified speed.
• Because each logic gate in a circuit has a
propagation delay, a signal transition at the input of
a circuit cannot immediately cause a change in the
logic value of the output of a circuit.
• Propagation delays ultimately limit the speed at
which a circuit can operate.
• Timing verification checks each signal path to verify
that it is not compromised by propagation delay.
• This step is done after logic synthesis specifies the
actual devices that will compose a circuit and
before the circuit is released forproduction.
• Fault simulation compares the behavior of an ideal circuit with
the behavior of a circuit that contains a process-induced flaw.
• Dust and other particulates in the atmosphere of the clean
room can cause a circuit to be fabricated with a fault.
• A circuit with a fault will not exhibit the same functionality as a
fault-free circuit.
• Fault simulation is used to identify input stimuli that can be
used to reveal the difference between the faulty circuit and the
fault-free circuit.
• These test patterns will be used to test fabricated devices to
ensure that only good devices are shipped to the customer.
• Test generation and fault simulation may occur at different
steps in the design process, but they are always done before
production in order to avoid the disaster of producing a circuit
whose internal logic cannot be tested.
 Hardware Description Language (HDL)

 Developed in 1984

 Standard: IEEE 1364, Dec 1995

 Limited to Digital Circuits only

 Any text between two forward slashes ( // )
and the end of the line is interpreted as a
comment and will have no effect on a
simulation using the model.
 Multiline comments begin with / * and

terminate with * /.
• Blank spaces are ignored, but they may not appear
within the text of a keyword, a user-specified
identifier, an operator, or the representation of a
number.
• Verilog is case sensitive, which means that
uppercase and lowercase letters are distinguishable
(e.g., not is not the same as NOT).
• The term module refers to the text enclosed by
the keyword pair module . . . endmodule.
• A module is the fundamental descriptive unit in
the Verilog language.
• It is declared by the keyword module and must
always be terminated by the keyword endmodule.
 Keywords are predefined lowercase
identifiers that define the language
constructs. Examples of keywords are
module, endmodule, input, output,
wire, and, or, and not.
 For clarity, keywords will be displayed in

boldface in the text in all examples of code

and wherever it is appropriate to call
attention to their use.
 Any Sequence of letter, digits, dollar sign,
underscore.
 First character must be a letter or

underscore.
 It cannot be a dollar sign.
 Cannot use characters such as hyphen,

brackets, or # in verilog names

 Formed from {[A-Z], [a-z], [0-9], _, $},
but ..
 .. can’t begin with $ or [0-9]
◦ myidentifier 
◦ m_y_identifier 
◦ 3my_identifier 
◦ $my_identifier 
◦ _myidentifier$ 
 Case sensitivity
◦ myid  Myid
 The keywords used are:
 1. input
 2. output
 3. inout
 Scalar
 Vector
 The type of port is defined in the port

declaration phase of Verilog programming.

 Eg :
 Input a;
 Input [7:0] b;
 Output y;
 Predefined logic value system or value set
: ‘0’, ‘1’ ,’x’ and ‘z’;

 ‘x’ means uninitialized or unknown logic

value

 ‘z’ means high impedance value.

 <size>’<radix> <value>

Binary
Binary bbor
orBB
Octal
Octal ooor
orOO
No
Noofof Decimal
Decimal ddor
orDD Consecutive
Consecutivechars
chars
bits
bits
Hexadecimalhhor
Hexadecimal orHH 0-f,
0-f,x,x,zz
◦ 8’h ax = 1010xxxx
◦ 1’b0=0
◦ 4’b1010=1010
The datatypes used are:
1.Nets
2.Reg
3.Integer
4.Time
5.Realtime
6.Strings
 Can be thought as hardware wires driven by
logic
 Equal z when unconnected
 Various types of nets
◦ wire
◦ wand (wired-AND)
◦ wor (wired-OR)
◦ tri (tri-state)
 Internal connections are declared as wires.
 The circuit in this example has one internal

connection, at terminal w1 , and is declared

with the keywordwire.
 &&  logical AND
 ||  logical OR
 ! logical NOT
 Operands evaluated to ONE bit value: 0, 1

or x
 Result is ONE bit value: 0, 1 or x

A = 6; A && B  1 && 0  0
B = 0; A || !B  1 || 1  1
C = x; C || B  x || 0  x
but
butC&&B=0
C&&B=0
 &  bitwise AND
 |  bitwise OR
 ~  bitwise NOT
 ^  bitwise XOR
 ~^ or ^~  bitwise XNOR

 Operation on bit by bit basis

Verilog HDL Basics Thanasis Oikonomou 37

 >  greater than
 <  less than
 >=  greater or equal than
 <=  less or equal than

Verilog HDL Basics Thanasis Oikonomou 38

 $finish is a Verilog system task that tells the
simulator to terminate the current
simulation.
 Initial blocks cause particular instructions to
be performed at the beginning of the
simulation before any other instructions
operate.
 Initial blocks only operate once.
 In Verilog, the always block is one of the
procedural blocks. Statements inside an
always block are executed sequentially.
 An always block always executes, unlike
initial blocks that execute only once at the
beginning of the simulation. The always
block should have a sensitive list or a delay
associated with it
 The sensitive list is the one that tells the
always block when to execute the block of
code
 The always block indicates a free-running
process,
 but the initial block indicates a process

executes exactly once.

 Both constructs begin execution at

simulator time 0, and both execute until the

end of the block.
 The initial processes execute once, whereas

always process repeatedly execute forever.

• The port list of a module is the interface
between the module and its environment.
• In this example, the ports are the inputs and
outputs of the circuit.
• The logic values of the inputs to a circuit are
determined by the environment; the logic
values of the outputs are determined within the
circuit and result from the action of the inputs
on the circuit.
• The port list is enclosed in parentheses, and
commas are used to separate elements of the
list.
• The statement is terminated with a semicolon
(;).
• The elements of the list are referred to as
instantiations of a gate, each of which is
referred to as a gate instance .
• Each gate instantiation consists of an
optional name (such as G1, G2 , etc.)
followed by the gate output and inputs
separated by commas and enclosed within
parentheses.
• The output of a primitive gate is always
listed first, followed by the inputs.
• A Verilog module is declared. Its declaration
specifies the input–output behavior of the
hardware that it represents.
• Predefined primitives are not declared, because
their definition is specified by the language and
is not subject to change by the user.
• Primitives are used (i.e., instantiated), just as
gates are used to populate a printed circuit
board
• Once a module has been declared, it may be
used (instantiated) within a design.
• In Verilog, the propagation delay of a gate is specified in terms
of time units and by the symbol #.
• The numbers associated with time delays in Verilog are
dimensionless.
• The association of a time unit with physical time is made with
the timescale compiler directive. (Compiler directives start
with the () back quote, or grave accent, symbol.)
• Such a directive is specified before the declaration of a module
and applies to all numerical values of time in the code that
follows. An example of a timescale directive is timescale
1ns/100ps
• The first number specifies the unit of measurement for time
delays. The second number specifies the precision for which
the delays are rounded off, in this case to 0.1 ns.
• If no timescale is specified, a simulator may display
dimensionless values or default to a certain time unit, usually
1ns (=10-9 s).
 HDL Example 3.2 repeats the description of
the simple circuit of Example 3.1 , but with
propagation delays specified for each gate.
 The and, or , and not gates have a time

delay of 30, 20, and 10 ns, respectively.

 If the circuit is simulated and the inputs

change from A , B , C = 0 to A , B , C = 1,
the outputs change as shown in Table 3.5
 An HDL description that provides the
stimulus to a design is called a test bench.
• A test bench is a module containing a signal generator and an
instantiation of the model that is to be verified.
• Note that the test bench ( t_Simple_ Circuit_prop_delay ) has no input
or output ports, because it does not interact with its environment.
• In general, we prefer to name the test bench with the prefix t_
concatenated with the name of the module that is to be tested by the
test bench, but that choice is left to the designer.
• Within the test bench, the inputs to the circuit are declared with
keyword reg and the outputs are declared with the keyword
wire .
• The module Simple_Circuit_ prop_delay is instantiated with the
instance name M1.
• Every instantiation of a module must include a unique instance name.
• Note that using a test bench is similar to testing actual hardware by
attaching signal generators to the inputs of a circuit and attaching
probes (wires) to the outputs of the circuit.
• The initial keyword is used with a set of statements that begin
executing when the simulation is initialized;
• The signal activity associated with initial terminates execution
when the last statement has finished executing.
• The initial statements are commonly used to describe
waveforms in a test bench.
• The set of statements to be executed is called a block statement and
consists of several statements enclosed by the keywords begin and
end.
• The action specified by the statements begins when the simulation is
launched, and the statements are executed in sequence, left to right,
from top to bottom, by a simulator in order to provide the input to the
circuit.
• Initially, A, B, C = 0. ( A, B, and C are each set to 1b0, which signifies
one binary digit with a value of 0.)
• After 100 ns, the inputs change to A, B, C = 1. After another 100 ns,
the simulation terminates at time 200 ns.
• A second initial statement uses the $finish system task to
specify termination of the simulation.
• Boolean equations describing combinational
logic are specified in Verilog with a
continuous assignment statement
consisting of the keyword assign followed
by a Boolean expression.
• To distinguish arithmetic operators from
logical operators, Verilog uses the symbols
(&), (/), and (~) for AND, OR, and NOT
(complement), respectively.
 Example 3.4, The mechanism acts just like
combinational logic, has a gate-level
equivalent circuit, and is referred to as
implicit combinational logic .
• The logic gates used in Verilog descriptions
with keywords and, or, etc., are defined by
the system and are referred to as system
primitives.
• The user can create additional primitives by
defining them in tabular form.
• These types of circuits are referred to as user-
defined primitives (UDPs).
• One way of specifying a digital circuit in tabular
form is by means of a truth table.
• UDP descriptions do not use the keyword pair
module . . . endmodule.
• Instead, they are declared with the keyword
pair primitive . . . endprimitive.
 single output many input
 consume very less memory
 I/Os must be scalar (i.e. bit)
 ‘z’ value is not supported.
 UDPs can take only scalar input terminals (1 bit).
Multiple input terminals are permitted.
 2) UDPs can have only one scalar output terminal (1
bit). The output terminal must always appear first in the terminal
list. Multiple output terminals are not allowed.
 3) In the declarations section, the output terminal is declared with
the keyword output. Since sequential UDPs store state, the output
terminal must also be declared as a reg.
 4) The inputs are declared with the keyword input.
 5) The state in a sequential UDP can be initialized with an ‘initial’
statement. This statement is optional. A 1-bit value is assigned to the
output, which is declared as reg.
 6) The state table entries can contain values 0,1,or x . UDPs do
not handle z values. Z values passed to
a UDP are treated x values.
 7) UDPs are defined at the same level as modules. UDPs can
not be defined inside modules. They can be instantiated only
inside modules. UDPs are instantiated exactly like gate primitives.
 8) UDPs do not support inout ports.
• It is declared with the keyword primitive ,
followed by a name and port list.
• There can be only one output, and it must be listed
fi rst in the port list and declared with keyword
output .
• There can be any number of inputs.
• The order in which they are listed in the input
declaration must conform to the order in which they
are given values in the table that follows.
• The truth table is enclosed within the keywords
table and endtable.
• The values of the inputs are listed in order, ending
with a colon (:). The output is always the last entry
in a row and is followed by a semicolon (;).
• The declaration of a UDP ends with the keyword
endprimitive.
•The system recognizes the variables by the order in which they are listed
in the input declaration.
•A user-defined primitive can be instantiated in the construction of other modules
(digital circuits), just as the system primitives are used.
•For example, the declaration
Circuit _with _UDP_ 02467 (E, F, A, B, C, D);
will produce a circuit that implements the hardware shown in Figure 3.37