Microprocessor

Programming
and Interfacing
Introduction
Teaching Team

Instructor in Charge
Vipin Kizheppatt ([email protected])
Lecture Instructor
Vipin Joshi ([email protected])
Tutors
Vipin Kizheppatt
Vipin Joshi
Arun Raman ([email protected])
Lab Instructors
Vipin Kizheppatt
Vipin Joshi
2
Arun Raman
If you face any issues

Lab: TA  Concerned Lab Instructor  IC 

Tutorials: Tutor  IC 

Discussion forums in Quanta

Continuous course feedback (Anonymous)

https://forms.gle/kowcUbKzxwfmcAbM7

3
Course Objectives

o Describe the basic architecture of microprocessors

o Able to write simple to moderately complex assembly level programs for x86
and RISC processors
o Able to interface different peripherals (such as DMA controller, ADC, DAC
etc.) with a microprocessor and control them through software
o Interface interrupt controller with a microprocessor and write interrupt service
routine for the peripherals
o Text Book:
o Barry B Brey, The Intel Microprocessors, Pearson, 8th Ed.
o David Patterson and John Hennessy, Computer Architecture: A Quantitative
Approach, 5th Ed.
o Reference Book: 4

o nd
Evaluation Components

Componen Duration Weightage Date & Time OB/

t (%) CB
Midsem Exam 90 Mins 25% 06/03/25 OB
09:30AM-11:00AM

Quizzes 4 quizzes with 15 mins 15% Feb 5 OB

each. Feb 27 07:00-7:15 PM
Best 3 will be considered April 2
for grading April 23
Evaluated Labs 4 evaluated labs, each 15% Feb 10,13 OB
one 1.5 hrs. March 13,17
Best 3 will be considered March 24,27
for grading April 09,April 14
Lab Compre. 1.5 hrs 10% April 21-April 25 OB
(Respective lab slots)

Comprehensive 3 hrs 35% 08/05/25 (FN) OB

Examination

5
Why study an obsolete
processor?

6
Why study an obsolete processor?

o Fundamentals remains same

o Easy to learn the basics due to simpler architecture
o Possible in a semester of course work
o Understand the limitations and need for improvement

7
Processor Architecture Fundamentals

o Let’s start with a simple problem statement.

o You need to find the average of 4 numbers 20H, 30H, 40H and
50H using some sort of circuit
o You will notice that throughout the course we are using
hexadecimal number representation
o It is due to their concise nature and easier conversion from binary
and vice-versa
o Basically, you need to find (20H+30H+40H+50H)/4
o One way to do this is the build a circuit dedicated for this
operation (with 3 adders and 1 divider) 8
Processor Architecture Fundamentals

o How to do that you might already know from digital design

o Main drawback here is your circuit is quite inflexible and performs
only one operation
o Other option is to build a flexible circuit (which can perform
different operations such as add, subtract etc.) and some how
control it to get our operation done
o This flexible circuit is our first step towards a microprocessor and
its control is the first step towards software development

9
Processor Architecture Fundamentals
o Since the circuit needs to perform addition, we need to build a
circuit which can add

Circuit diagram

8
Adder 8
8 10

Abstract model of 8-bit adder 4-bit adder by cascading four 1-bit adders
Processor Architecture Fundamentals
o Follow similar steps to design a bunch of circuits to perform one
operation

8 8
Adder/ Multiplier
Subtractor 8 8
8 8

8
Comparator Complement
8 8 8
8
11
Processor Architecture Fundamentals (ALU)
o Arithmetic and Logic Unit (ALU) is usually referred as the brain of
a processor

8 Add/Sub
8
8

8 Multiplier data_in1 8

4 :1 Mux
8
8
data_out
8 ALU
8
8 Comparator data_in2 8
8
8
Control
2
Compleme Abstract Model
8 nt 8
Control The multiplexer (MUX)
chooses
the output of a particular 12

circuit
Processor Architecture Fundamentals (ALU)

data_in1 8
data_out
ALU
8
data_in2 8

Control
2
Abstract Model

o ALU requires some data to operate on

o It requires control signals to specify the type of operation to
perform
o It gives output data and usually some status signals 13
Processor Architecture Fundamentals

o Let’s come back to our problem

o You need to find the average of 4 numbers 20H, 30H, 40H and
50H using some sort of circuit
o Here we need to perform addition 3 times
o First, we can add 20H and 30H
o We need to store that result some where and feed back to the
adder along with 40H for the next addition
o Then that result needs to be stored some where and fed along
with 50H
o That means there should be some way to store data (registers) 14
Processor Architecture Fundamentals
(Registers)

o A register is a bunch of flip-flops storing different bits of same

data

DataIn 8
En

DataOut 8
15
8-bit Register abstract model
Processor Architecture Fundamentals
(Register Set)
Write Register Data
Read Register

MUX
Reg 0 Data 1

Reg 1
Write Register
Decoder
Address

Address
Read Register Address 1
Reg 2
RegWriteEn
.
.
. Read Register

MUX
Data 2

Reg 15
16

Read Register Address 2

Processor Architecture Fundamentals
(Register Set)
RegWriteEn

Read Read
address 1 data 1 RegSet
Read
address 2 Read
data 2
Write
address
Write Register File
data
ALU
Register set abstract model

ALU register set interface

o Registers store data temporarily

o Register set require control signals to specify in which
register data should be stored, which register value
should be propagated to ALU etc. 17
Processor Architecture Fundamentals

o To find the average of 4 numbers 20H, 30H, 40H and 50H, we

may store them in 4 registers (Reg0, Reg1, Reg2 and Reg3)
o Now make Reg0 and Reg1 as input to the ALU and choose adder
circuit
o Store the output from ALU to Reg4
o Make Reg2 and Reg4 as input to ALU and store output in Reg4
o Make Reg3 and Reg4 as input to ALU and store output in Reg4
o Now you have the sum of 20H, 30H, 40H and 50H in Reg4
o Similar steps can be followed now to find the average
18
Processor Architecture Fundamentals
(Control logic)

o There should be some logic which controls the address lines of

register set and Mux of ALU
o This circuit is referred as control logic (control unit)

19
Software

o But who tells the control logic when and which control/data signals
to be made active
o That is where software comes into picture
o Here we will define some predefine binary patterns
o Eg: Pattern 0020H corresponds to storing 20H in register 0
0020H

Indicates Indicates register Indicates data to be

operation number stored
20
Software

o Let’s define a few operations

o 0 Store constant to a register
o 1 Make a register as in input to ALU
o 2 Add 2 inputs of ALU
o 3 Multiply 2 inputs of ALU
o 4 Compare 2 inputs of ALU
o 5 Complement first input of ALU

21
Software

o So, our problem to add 4 numbers 20H, 30H, 40H and 50H might look
like
0020H #Store 20H in register 0
0130H #Store 30H in register 1
0240H #Store 40H in register 2
0350H #Store 50H in register 3
1000H #Make reg 0 as first ALU input
1101H #Make reg 1 as second ALU input
24XXH #Add ALU inputs and store result in
reg 4
………… 22
Software

o You can see software is a bunch of binary patterns corresponding

to the instructions (code) and data
o Ultimately, they will get translated to bit patterns stored in registers
(data) and control signals to internal circuits
o But where do we store this software?
o For modern computers, it will be stored in the main memory
(generally a RAM)
o Control logic reads the instructions one by one, decodes and
performs the operation
23
Software

0020H 0
XX XX XX XX 0130H
Reg0 Reg1 Reg2 Reg3 2
Reset#
MUX 0240H 4
0350H 6
ALU XX
F 1000H 8
Latch
1101H 10
Address Bus
24XXH 12
Control logic
Data Bus XXXX 14
XXXX 16
PC 0
XXXX 18
CPU XXXX
20
Memory 24
Software

0020H 0
XX XX XX XX 0130H
Reg0 Reg1 Reg2 Reg3 2
Reset#
MUX 0240H 4
0350H 6
ALU XX
F 1000H 8
Latch
1101H 10
0 Address Bus
24XXH 12
Control logic
Data Bus XXXX 14
XXXX 16
PC 0
XXXX 18
CPU XXXX
20
Memory 25
Software

0020H 0
XX XX XX XX 0130H
Reg0 Reg1 Reg2 Reg3 2
Reset#
MUX 0240H 4
0350H 6
ALU XX
F 1000H 8
Latch
1101H 10
0 Address Bus
24XXH 12
Control logic
Data Bus XXXX 14
0020H
XXXX 16
PC 0
XXXX 18
CPU XXXX
20
Memory 26
Software

0020H 0
XX XX XX XX 0130H
Reg0 Reg1 Reg2 Reg3 2
Reset#
MUX 0240H 4
0350H 6
ALU XX
F 1000H 8
Latch
1101H 10
0 Address Bus
0020H 24XXH 12
Control logic
Data Bus XXXX 14
0020H
XXXX 16
PC 0
XXXX 18
CPU XXXX
20
Memory 27
Software

0020H 0
20H XX XX XX 0130H
Reg0 Reg1 Reg2 Reg3 2
Reset#
MUX 0240H 4
0350H 6
ALU XX
F 1000H 8
Latch
1101H 10
0 Address Bus
24XXH 12
Control logic
Data Bus XXXX 14
0020H
XXXX 16
PC 0
XXXX 18
CPU XXXX
20
Memory 28
Software

0020H 0
20H 30H XX XX 0130H
Reg0 Reg1 Reg2 Reg3 2
Reset#
MUX 0240H 4
0350H 6
ALU XX
F 1000H 8
Latch
1101H 10
2 Address Bus
24XXH 12
Control logic
Data Bus XXXX 14
0130H 0130H
XXXX 16
PC 2
XXXX 18
CPU XXXX
20
Memory 29
Computer Architecture

o In the previous example notice that memory address increments

by 2
o It is because each instruction is 2 bytes and for all modern
processor-based systems, atomic unit of memory is a byte
o Processor architecture discussed in slides is an over simplified
model but the concepts remain the same
o Low-level design of control logic, ALU etc. are beyond the scope
of this course (called processor micro-architecture)
o Those interested in it should take a course on computer
architecture and VLSI architecture
30
Main takeaways

o A processor is a digital circuit mainly composed of ALU, control

logic and register set
o What a processor does is decided by software, which is nothing
but binary patterns representing instructions and data
o Software generally resides in main memory and executed in a
sequential manner by the processor

31
Try your self

o Write the complete software for the average problem for our
fictitious processor assuming it is capable of division
o Define additional binary patterns to represent the instructions as
you need
o If the processor does not support division (such circuit is not
present in ALU) but supports subtraction, how will you tackle the
problem?
o What is the effect on your program size and execution time?

32
Thank you,
any
questions?

33