Outline

1. Design Procedure
2. Examples
• Adder
• Subtractor
• Carry-look ahead
adder
• Code converter
• Magnitude
comparator
• 7-segment display
3. Timing Hazard
1
1. Design Procedure
1. State the problem / specification for
the design.
2. Determine the number of input
variables and output variables.
3. Formulate truth tables / Boolean
functions
between inputs and outputs.
4. Simplification / minimization for the
logic functions.
5. Design and draw the logic circuit
diagram.
2
1. Adder
1-bit Half-Adder
• As known as half adder
(HA)

S(X,Y) =
x s m(1,2)
y c =
0 0 XY C(X,Y)
0 0
0 1 = XY
1 0
1 1
0 0
1 0
1 1 3
1-bit Full-Adder Carry out

(FA)
x y c s i
co Sum

0 0 0 0 0
0 0 1 1 0
co  yci  xci  xy
0 1 0 1 0 s  x yci  xyci  xy ci  xyci
0 1 1 0 1  xy  x( y  y)ci  y(x 
 x( yci  yci )  x( yci  y
1 0 0 1 0  x( y  ci )  x( y  x)ci
1 0 1 0 1 c i )
 xy(1  ci )  (xy 
1 1 0 0 1 ci )  xy  xyci  xyci  xyci
xy)ci
1 1 1 1 1 x x  y  c
i
 xy  (x  y)ci
y s

ci
co
4
1-bit Full-Adder
(FA)

x. x x s s
s
y co co
y. y
ci co

Arrangement of 2 half-adders to form a full-

adder

5
Ripple Carry Adder (Parallel
• A single full-adder is capable of adding two
adder)
one-bit
numbers and an input carry.
• To add binary numbers with more than
one bit, additional full-adders must be
employed.
• The carry out from previous stage will be
fed into the carry input of the next stage.
• A ripple carry adder is formed.

xx3 yy3 ci xx2 yy2 ci xx1 yy1 ci xx0 yy0 ci

(LSB)
(MSB) 0
co s co s co s co s

co
s3 s2 s1 s0 6
3.2.2 -
Subtractor
1-bit
X
Half-Subtractor
D B The outputs are
Y
D (difference bit)
0 0
and
0 0
0 1 B (borrow out bit)
1 1
1 1
0 0
D(X,Y) =
1 0
m(1,2)
1 0
= XY
B(X,Y) = X’Y

7
Full
Subtractor
XYZ D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1 B = X’Y + YZ +
0 1 1 0 1 X’Z,
1 0 0 1 0 = X’Y + Z(X’Y’ +
XY)
1 0 1 0 0
= X’Y + Z(XY)’
1 1 0 0 0
1 1 1 1 1

D=
8
XYZ
Full Subtractor
D = XYZ, B = X’Y +
Z(XY)’

Like FA, FS is built by two

HSs 9
4-bit parallel adder with 1-bit 4 FA
modules

10
4-bit parallel subtractor with 1-bit 4 FA
modules

A – B = A + (2’s of B) = A
+ B’ + 1
11
4-bit
Adder/Subtractor

F3 F2 F1 F0

M B F
0 0 0
M = 0→ Adder
M = 1→ 0 1 1 F=B
Subtractor 1 0 1 M
1 1 0
12
3.2.3 Carry Look Ahead
Adder
The carry output of each full-adder stage is
connected
to the carry input of the next higher stage
A time delay thus occurs because the sum and
the carry output of each stage cannot be
produced until the input carry appears
Assuming that the delay for generating the carry
output is m nsec
For a N-bit adder, the total delay will be up to Nm
nsec
Serious delay problem if N is a large number
Solution: Calculate the carry bits beforehand,
then construct carry-look-ahead adder
13
Carry generate (g) and carry
propagate (p)
x y ci co Conditions for generating g and p
0 0 0 0
From the table, we obtain
0 0 1 0
0 1 0 0 g = xy and p = xy
0 1 1  1 p
1 0 0 0 More importantly, the carry output
1 0 1  1 p can be obtained by:
1 1 0 1 g co = g + i
1 1 1 1 g pc

14
Derivation of a 4-bit carry look-ahead
adder:0: c
Full-adder =g +p c 0 0 i0
o0
Full-adder 1: = co0 Final co3, is only depend
ci1 = g1 + p1 ci1 on ci0 , not co2 and co1 ; and x, y
= g1 + p1 co0
co1
= g1 + p1(g0 + p0 ci0)
= g1 + p1 g0 + p1 p0 ci0
Full-adder 2: = co1
ci2
= g2 + p2 co1
co2
= g2 + p2(g1 + p1 g0 + p1 p0 ci0)
= g2 + p2 g1 + p2 p1 g0 + p2 p1 p0 ci0
Full-adder 3:
ci3 = co2
co3 = g3 + p3 co2
= g3 + p3(g2 + p2 g1 + p2 p1 g0 + p2 p1 p0 ci0)
= g3 + p3 g2 + p3 p2 g1 + p3 p2 p1 g0 + p3 p2 p1 p0 ci0 15
4-bit Carry Look Ahead
Adder

16
3.2.4 Code
Converter
State the case
Design a circuit to convert the BCD to the
Excess- 3 code
- A, B, C, D are the input of BCD.
- W, X, Y, Z are the output of Excess-3 code.
- The output functions are:
W (A, B, C, D)
X (A, B, C, D)
Y (A, B, C, D)
Z (A, B, C, D)

17
Decim Input (8421 code) Output (Excess-3
al code)
digit A B C D W X Y Z

0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
Unused X X X X X X X X
Unused X X X X X X X X
Unused X X X X X X X X
Unused X X X X X X X X
X
Unused Unused X
outputs X consider
can X X DON’T
as X X X
Unused CARE.
X X X X X X X X
 There are four variables (A,B,C,D) in
the functions
 Each output variable depends on 4
variables
 So we need 4 four-variable K-maps

W(A,B,C,D) = m(5,6,7,8,9) +
d(10,11,12,13,14,15)
X(A,B,C,D) = m(1,2,3,4,9) +
d(10,11,12,13,14,15)
Y(A,B,C,D) = m(0,3,4,7,8) +
d(10,11,12,13,14,15)
Z(A,B,C,D) = m(0,2,4,6,8) +
d(10,11,12,13,14,15)
Logic functions and
circuit
From previous K-maps,
W = A + BC + BD
X = B’C + B’D +
BC’D’ Y = CD +
C’D’
Z = D’

We further optimize
them (optional)
W = A + BC + BD
= A
+ B(C + D)
X = B’C + B’D +
BC’D’ = B’(C +D) +
3.2.5 Magnitude
Comparator
A comparator is used to compare the magnitude of
two
numbers.
The output will be one of the three possibilities,
small (s), equal (e) and greater (g)
For two 2-digit numbers, A and B, we have the
following description:

g, if A  B 
z A
  if  
e, B
 s, if A 
Finally, we construct the following truth
table:
input output input output
a1 a0 b1 b0 z2 z1 z0 a1 a0 b1 b0 z2 z1 z0
0 0 0 0 0 1 0 1 0 0 0 1 0 0
0 0 0 1 0 0 1 1 0 0 1 1 0 0
0 0 1 0 0 0 1 1 0 1 0 0 1 0
0 0 1 1 0 0 1 1 0 1 1 0 0 1
0 1 0 0 1 0 0 1 1 0 0 1 0 0
0 1 0 1 0 1 0 1 1 0 1 1 0 0
0 1 1 0 0 0 1 1 1 1 0 1 0 0
0 1 1 1 0 0 1 1 1 1 1 0 1 0
The output (z2 z1 z0)can be obtained by using k-
map:

z2  a1b1  a0 b1 b0  a1a0 b0

z1  (a1b1  a1 b1)(a0b0  a0
b0 )

z0  a1b1  a0b1b0  a1
a0b0
3.2.6 7-segment
display
Note: the
corresponding outputs
of those unused BCD
code should either be
0 or don’t care
Number of variables (input)?
Number of functions (output)?
Number of K-map?
Example of functions:
a ( w, x, y, z) =  m
(0,2,3,5,6,7,8,9)
OR
a ( w, x, y, z) =  m
(0,2,3,5,6,7,8,9) +
 d (10,11,12,13,14,15)
The second design will generate
K-maps of
segment-a

a(w,x,y,z) = w + y + xz +
x’z’

Exercise: find the simplified expression of b, c, d, e, f and g

BCD TO 7-SEGMENT
DECODER/DRIVER
74LS47
3.3 Timing
Hazard
Logic devices (gates or other more
complex
circuits) are essentially made from
semi- conductor
IC input impedance and PCB copper
track inductance cause charging and
discharging effect (similar to RC
circuit response)
The “real” input and output voltages are
not a perfect step function
Practical logic input and output
waveforms exhibit “delay” nature
I/P and O/P
waveform
Timing Diagram of NOT
Gate
Timing Diagram of AND
Gate
Gate
delay
 Output waveform is shifted tG time units
 The length of time for an input change, to result
in the
corresponding output change.

 The propagation delay could cause undesirable

events: timing hazard: timing hazards
Timing
Hazards
The circuit output may
produce a
short pulse (which should not
be happened) at the
transient time caused by
delay in propagation of
signals
Short pulse also known as
glitch
Static and Dynamic
Hazards
Examp
le
 x 2 xz’ 2 
2
z’
z  f

y 2 yz z

Assuming that the delay of the z’

gates are different as shown
above.
With the initial input condition: yz
xyz =111
Now, change z from “1” to “0”.
Then the associated gate outputs
xz’
will be change after their
corresponding delays.
f
An unwanted glitch will appear at
the
output – static-1 hazard !!!
x 2 xz’ 2 
2
z’
z  f

y 2 yz
z

Consider a different case z’

With the initial input
condition:
xyz =110
yz
Now, change z from “0” to
“1”.
NO glitch
Hazard !!! occurs when
only
input of xzy change from
xz’
111 to 110, NOT for the
case of from 110 to 111.
f

4
2
Example of static-0
hazard
W
WXZP 

X 
 ZP
Z   F
 
 YZ
 YP 
Y  
 XPYP 
 XP
Z

With the initial ZP

input condition: YZ
wxyz = 0000
W XZP
Now, change z from “0”
to “1”. F
Static-0 hazard
4
occurs !!! 3
Timing hazard elimination
The occurrence of the hazard can
be detected by inspecting the K-
map of the particular circuit.
Eliminating a hazard is to enclose the
two minterms in question with
another product term that overlaps
both groupings.
The removal of hazards requires the
addition of redundant gates to the
circuit.
4
4
K-map for eliminating timing
hazard
f(x,y,z) = xz’ + yz
The optimal grouping

Static-1 hazard occurs

when
input change from 111 to
110
Include an redundant product
term

f = xz’ + yz + xy

Now the hazard is removed!

4
5
Use K-map to eliminate
Hazards
 To eliminate the hazard, group the two minterms
that cause the hazards
 An additional redundant product term (gate) is
introduced

4
6
Hazard-free realization
General idea: to include all PIs
Work for both K-map and QM-
method

Please try to develop a hazard-

free circuit for the function
f (a, b, c) =  m (0,2,4,5)

Steps:
a) Minimize the function f
b) Realize f to a hazard-free
circuit 4
7