Session 4

Motivation
CMOS Power Consumption Sources
Low power techniques
UPF
References

Prepared by:
ICpedia PnR Team
C0ntents
 Motivation
 CMOS Power Consumption Sources

 Low power techniques

 Importance of Power Awareness

 Dynamic Power Reduction Techniques

 Static Power Reduction Techniques

 UPF

 References

2
The Transistor Revolution

3
Advances in IC Technologies

Intel 4004 microprocessor Intel Pentium (IV) microprocessor Intel Xeon E7-8893 v2

1971 2001 2014

1000 transistors 42 Million transistors 4.3 Billion transistors
1 MHz operation 2 GHz operation 3.7 GHz operation

4
Electronic Technology Today: CMOS Convergence

CMOS technology dominates in modern ICs

5
Moore’s Law
 1965. Moore’s law was discovered, according to which the number of transistors in ICs doubles every 18 months.

 At present, the number of transistors in ICs has reached dozens of billions.

6
Die Size Growth & Frequency

 Die size grows by 14% every year  Clock frequency doubles every 2 years

7
Power Dissipation & Power Density
 Power increases about ten times every 3 years  Power Density increases twice every year

8
Power Consumption of Integrated Circuits

9
Power Consumption of Integrated Circuits

10
Power Affected Problems

Low Power Power Efficiency Reliability

<90nm
Technology
Application

• Wireless • Microprocessors
• Mobile • Graphics/multimedia • All design<90nm
• Embedded systems
• Networking/telecom
Concern

• Battery life • Thermal management • Leakage power

• Leakage power • Packaging, cooling cost • IR-drop
• Dynamic power • Electromigration

11
Sources of Power Dissipation in CMOS
 – represents the Charging and discharging load capacitances

 – is due to the direct-path short current, which arises when both NMOS
and PMOS transistors are simultaneously active, conducting current
directly from supply to ground

 – is due to leakage current, which arises from reverse bias diode currents, Power
sub-threshold currents, gate tunneling

 Leakage problems cannot be solved by new technology nodes, so design Static

Dynamic
(Leakage)
approaches are needed to minimize leakage
Isw
IInt

Cload
ILeakage

Switching Short Circuit Gate Oxide Sub Threshold

Isw
IInt

Cload Cload Igate oxide

Isubtreshold

12
Dynamic Power
 Dynamic Power: Charging and discharging load capacitances
=
 Minimizing Dynamic Power :
1. Voltage and frequency scaling (lower )
- Run high speed circuits at lower voltage to meet performance constraint
- Reduce clock frequency with parallel functional units
- Relax critical path constraints by pipelining.
- Reducing voltage lead to quadratic reduction in the dynamic switching power but Switching
frequency is reduced
- Note that: voltage and frequency usually fixed by project so the most controllable factors will
be switching activity and load capacitance.
2. Reduce capacitive load (lower )
- Minimum device sizes if performance allows
= +
- Compact and custom layout
- Shorten or eliminate long wires, including clock net
3. Reduce activity factor (lower )
- Clock gating

13
Short Circuit Power
 Occurs when PMOS and NMOS devices on simultaneously, Direct path from
to .

 Proportional to switching activity, So short-circuit power is consumed by each

transition same as dynamic power.

 Peak current determined by MOSFET saturation current, so directly

proportional to device sizes.

 Short circuit power increases with rise and fall times of input.

 Minimizing Short Circuit Power :

1. Can eliminate short circuit dissipation entirely by very aggressive voltage

scaling
- Need < + |
- Both devices can’t be on simultaneously
14
Short Circuit Power
2. For individual gate, minimize short circuit current by making output rise/fall time much
bigger than input rise/fall time

- Slows down circuit.

- Increases drive capability for fanout gates.

Another terminology that minizine short circuit power requires that gate output transition
should not be faster than the input transition.

3. When input and output rise/fall times are equalized, most power is associated with
dynamic power.

15
Technology Scaling Impact on Short Circuit Power
 1-16% short-circuit power at 0.18 micron.

 4-37% at 0.13 micron

 12-60% at 0.09 micron

16
Static Power

 Static or leakage power occurs when the device is at steady state, no activity in the
device [transistor is off].

 Static power consists of:

 Sub-threshold current
When the transistor is in off state, the gate-to-source voltage is less than the
threshold voltage, there is a leakage current from drain to source which is called the
subthreshold current. This current is highest when the gate voltage is just below the
threshold voltage, as voltages have scaled down with technology, this is becoming a
major component of leakage power in semiconductor devices.

 Gate oxide leakage

As transistor geometries reduce, gate oxide thickness have also been reducing
enabling higher performance. However, this thinning of oxide layer causes leakage
current between substrate and gate through the oxide.

 pn-junction leakage
Even when the p-n junctions are reverse-biased, there is a small current flowing
through these junctions due to minority carriers. When the temperature increases, the
minority carrier injection also raises, and causes an increase in leakage current.
17
Static Power

 Leakage current equations:

Subthreshold leakage Gate Leakage

( )
𝐕 gs − 𝐕 th − 𝐕 ds
𝒒 𝒒
𝐈sub =𝐈𝟎 ex p nkT
⋅ 𝟏−ex p kT
Reverse Biased Junction

( )
𝟐
kT 𝟏 .𝟖 𝐖 (Band-To-Band-Tunneling) BTBT Leakage
𝐈𝐎 ≈ 𝜷 𝒆 𝛃=μ Cox
( )
qVapp
𝐪 𝐋
𝐈 reverse = 𝐀 ⋅ 𝐉𝐒 𝐞 kT
−𝟏

Total Transistor Leakage Current = Ioverall = IBTBT + Isub +Igate

18
Static Power
 Gate Oxide leakage increases with :
- Increase in VOX - Reduction in tOX

 Leakage is now a major problem

- Battery life issues for wireless applications.

- Total power budget for wired applications.

 Leakage problems cannot be solved by new processes.

 Design approaches are needed to minimize leakage like

- Power gating method.

- Muti-threshold standard cells used for the block.

19
Technology Scaling Impact on Leakage Power

 Leakage power is dominated while technology is scaling.

20
Exercise 1
 What really matters for IR drop analysis, is overall power consumption.. Or power density?

 For FPGAs, what is the major component of power, static or dynamic power?

 Which design constraints that have an impact on power consumption?

 For the same technology node , when the delays are small, Power consumptions will be ………. [ High – Low
– Cannot be determined – Doesn’t change ]

 Give some example for low power design techniques.

21
Importance of Power Awareness
 Power has an impact on:

• System performance (battery life)

• Chip performance (circuit speed)

• Packaging and cooling (cost)

• Signal integrity: Inductive kick (Ldi/dt), IR drop, noise, etc.

• Physical reliability: Electromigration, hot-carriers, etc.

 The Old Design Philosophy

• Maximum performance is primary goal : Minimum delay at circuit level.

• Performance achieved through optimum sizing, logic mapping, architectural transformations.

 The New Design Philosophy

• Maximum performance is too power-hungry, practically unachievable.

• Excess performance (as offered by technology) to be used for energy/power reduction.

22
Importance of Power Awareness
 Power-Aware Design Flow

System and Software Architecture Choose appropriate power intent, design styles etc

RTL Implementation
Implement power intent in appropriate format
Logic simulation
Power aware simulation and analysis
Logic Synthesis
Automate synthesis of LPD techniques
Timing Analysis

Power-aware verification needed to reveal power

Formal Verification
Related bugs
Physical Synthesis

Signoff Signoff tools must be voltage-aware for silicon

success

 Power Management should be considered at the earliest design stages. Almost every step of design flow need to be modified for
LPD “Low Power Design”.

23
Importance of Power Awareness

 Design approaches used for reducing power

consumption :

- Dynamic power reduction techniques :

• Clock gating

• DVFS: Dynamic Voltage Frequency Scaling

• Multi voltage design technique

- Static power reduction techniques :

• Multi-Threshold Logic

• Power Gating

24
Dynamic Power Reduction Techniques
 Clock Gating :

• Clock Gating technique used for synchronous design to disable clock switching for certain time [when circuit not used].
• A significant fraction of the dynamic power in a chip is in the distribution network of the clock.
• Up to 50% or even more of the dynamic power can be spent in the clock buffers. The reason is:
1. Clock buffers have the highest toggle rate in the system, there are lots of clock buffers in a design
2. Clock buffers often have a high drive strength to minimize clock delay

The most common technique to reduce this power is to turn clocks off when they are not required. This approach is known as clock gating.
• RTL compilation with clock gating insertion :

always@ (posedge CLK)

D Q
if(EN)
EN
Q<=D ;
Low
CLK ICG activity

• Today, most libraries include specific clock gating cells that are recognized by the synthesis tool. The combination of explicit clock
gating cells and automatic insertion makes clock gating a simple and reliable way of reducing power.

25
Dynamic Power Reduction Techniques
 Clock Gating Distribution :
• Can insert clock gating at multiple levels in clock tree
• Can shut off entire subtree

26
Dynamic Power Reduction Techniques
 Integrated Clock Gating (ICG) Cell

• Integrated Clock Gating (ICG) Cell is a specially designed cell that is used for clock gating
techniques.

• ICG cell basically stops the clock propagation through it when we apply a low clock enable
signal on it.
• As shown in the waveform figure it provides a glitch-free clock gated output. passed the clock
single only when the enable signal is high and stop the clock propagation when enable signal
is low.

27
Dynamic Power Reduction Techniques
 Why not only AND gate as a clock gating?

• The issue with the AND gate as clock gating is, it can not provide a glitch-free
output whereas a glitch.

• free clock wave is highly desired.

 Why not using Flip Flop instead of Latches?

• FF made of two latches so it’s double area [Not preferred].

• Doubling area cause increasing in power consumption.

 Note that :
• There are trade of between power and area due to number of ICG cells that will be added.
• Enable signal must operate at much lower frequency than clock itself otherwise it may out of
power saving.
• Best way to insert ICG cells is near to leaf cells of clock tree.

28
Dynamic Power Reduction Techniques
 DVFS is a method through which variable amount of energy is allocated to perform
a task

Dynamic voltage and frequency scaling

• Adjusts performance and energy consumption levels while the device is active

• Key is to meet users' performance needs while saving energy PWR

CTRL
0.7 – 0.9V

• Reduces processor frequency and voltage to obtain quadratic energy savings

OFF

• Frequency scaling 0.7V

0.9V

• For CPU, lower frequency gives lower energy consumption

Pcpu
f1
f3 = f1/3
E1 = CV12f1t f2 = f1/2 Dynamic Voltage/Frequency Scaling
E3 = E1/9
E2 = E1/4 (DVFS)

Time
t 2t 3t

29
Dynamic Power Reduction Techniques
 Voltage Scaling
𝐊 𝑽 𝑫𝑫 Voltage Average Power Delay (ns)
𝐃𝐞𝐥𝐚𝐲 = (uW)
(𝑽 ¿ ¿ 𝑫𝑫 −𝑽 𝑻 )𝜶 ¿
1.8 106.32 1.76
• Reducing VDD supply voltage reduce the power consumption.
1.5 66.43 1.934

• No effect on area 1.2 36.49 2.34

1 21.71 3.99
• Power consumption is a quadratic function of voltage.
Voltage Average Power Delay
• Decrease in supply voltage increases the overall delay (% Decrease) (% Decrease) (% Increase)

• At lower voltages, the delay increase is very significant 16.7% 37.5% 10%
33.3% 65.6% 33%
• Transistor sizing or parallel processing can help reduce the overall delay
44.4% 79.5% 127%

Voltage Avg Power Delay

(% Decrease) (% Decrease) (% Increase)

VDD Reduction of 4x4 Array Multiplier

30
Dynamic Power Reduction Techniques
 DVFS Example:

• Suppose that a task with workload W should be finished by deadline D

P1 α v1
Power Power 𝑣1
2
𝑓1
2

P1
( 𝑉 𝑓
(𝑉 2 , 𝐹2 )= 1 , 1
2 2 ) 𝑃2 α
4
.
2

W P2
W 75% energy saving
Time Time
T1 D D

DVFS is an affective way of reducing the CPU energy

 DVFS Summary:

• DVFS technique has been proven to be a highly effective technique for power minimization subject to a performance constraint.

• DVFS should consider not only the CPU power but also the total system power dissipation.

31
Dynamic Power Reduction Techniques
 Multi-Voltage Design Technique:

• Two VDDs are becoming common. Many chips already have two supplies (one for core and
one for I/O).

• Power reduction effect will be decreased as VDD’S are scaled. VDD1 VDD2

• Optimum V2/V1 is around 0.7 IN OUT

• Mixing blocks at different supplies adds some complexity to the design:

0.7 – 1.08 VSS
◦ Need to add I/O pins to supply the different power rails.
◦ Need a more complex power grid. Level Shifter logic model

LS
LS
LS
LS

LS
LS
LS
LS
◦ Need for level shifters on signals running between blocks. Level Shifters (LS) are special
standard cells used in Multi Voltage designs to covert one voltage level to another. LS
LS
◦ The best solution is to make sure each domain gets the voltage swings ( rise and fall 0.9 0.7
times) that it expects. Level shifters are needed between any domains that use different LS
LS
voltages. This approach limits any voltage swing and timing characterization issues to the
boundary of voltage domains and leaves the internal timing of the domain unaffected.

• When driving signals between power domains with radically different power rails, the need
for level shifters is clear.
 Two types of level shifters are used: High to Low & Low to High

32
Dynamic Power Reduction Techniques
 High-to-Low Level Shifter is basically two cascaded inverts has vddl supply and input is vddh. It’s placed in the lower voltage domain

• If the distance between the 1.2V domain and the 0.9V domain is small enough, and the library has a strong enough buffer, then the
driving buffer can be placed in the 1.2V domain. No additional buffering is required.

• If the distance between the 1.2V domain and the 0.9V domain is Large, adding additional buffers is required. Additional buffers in
the 1.1V domain as shown.

• Additional buffer uses the power rail of the 1.2V domain. But this means that the 1.2V rail must be routed probably in the 1.1V
domain. This kind of complex power routing is one of the key challenges in automating the implementation of multi-voltage designs.

VDDL VDDL
VDDH
OUTL OUTL
D Q D Q
CLK CLK

VSS VSS

1.2V Domain 0.9V Domain 1.2V Domain 0.9V Domain

1.1V Domain 1.1V Domain

Level Shifter in the Destination Domain

33
Dynamic Power Reduction Techniques
 Low-to-High Level Shifter is basically getting the lower voltage signal and uses a cross-coupled amplifier transistor structure
running at the higher voltage .

• Since the output driver requires more current than the input stage, the level shifter is placed in the 1.2V domain.

• However, power routing will be a challenge no matter where the level shifter is placed. Because it requires both rails, at least one of
the rails will have to be routed from another domain.

• If the distance between the 1.2V domain and the 0.9V domain is small enough, and the library has a strong enough buffer, then the
driving buffer can be placed in the 0.9V domain. No additional buffering is required. Otherwise, additional buffers need to be
placed in the 1.1V domain, causing the power routing problems mentioned above.

VDDL VDDH VDDL VDDH

D Q OUTH
INL OUTH
CLK
VSS

VSS 0.9V Domain 1.2V Domain

1.1V Domain

34
Dynamic Power Reduction Techniques
 Recommendation When using Level Shifters:

• Place the level shifters in the receiving domain – in the lower domain for High-to-Low shifters, in the higher domain for Low-to-
High shifters.

• Low-to-High level shifters have significant delays that need to be understood and thoughtfully factored into RTL design
partitioning for timing critical blocks.

• Ensure there is a defined relationship between different voltage domains such that the operating conditions make it clear whether
an up- or down-shifter is required.

• Routing clocks across different power domains means that they have to go through level shifters.

• This clearly complicates automation – the clock tree synthesis tools need to understand level shifters and automatically insert them
in the appropriate places.

• The clock buffers in the multi-level domain will sometimes be powered at 0.9V and sometime at 1.2V. The solution is that
optimization and timing analysis must be done simultaneously for both situations to assure that timing will be met for both
conditions.

35
Static Power Reduction Techniques
 Multi-Threshold Logic:

• As geometries have shrunk to 130nm, 90nm, 65nm, 45nm, 32nm, 22nm, 14nm and below, using libraries
with multiple VT has become a common way to reduce leakage current.

• Many libraries today offer two or three versions of their cells: Low VT, Standard VT, and High VT.

• HVT cells: Standard cells made up of transistors having high Vth. These cells consumes less power but
are slow. These can be used in path where timing is not critical thus, we can afford to introduce delay
while saving static power.

• LVT cells: Standard cells made up of transistors having low Vth. These cells are fast but consumes more
power. These are used in timing critical path.

• SVT cells: Standard cells made up of transistors having medium Vth. It offers a trade-off between HVT
and LVT, thus is consumes less power than LVT cells but are faster than HVT cells. These can be used
when we are not able to meet the timing by a small margin.

• The implementation tools can take advantage of these libraries to optimize timing and power
simultaneously.

36
Static Power Reduction Techniques
 Power Gating:

• Amount of possible saving in leakage power.

Power Gating

• A critical decision in power gating is how to switch power. In general, there are
two approaches: fine grain power gating and coarse grain power gating. OFF

• In fine grain power gating the switch is placed locally inside each standard 0.9V

cell in the library. Since this switch must supply the worst-case current required
by the cell, it must be quite large not to impact performance. The area overhead 0.9V 0.9V
of each cell is significant (often 2x-4x the size of the original cell).

• In coarse grain power gating, a block of gates has its power switched by a
collection of switch cells. The sizing of a coarse grain switch network is more VDD VDD
difficult than a fine grain switch as the exact switching activity of the logic it Sleep
Sleep
supplies is not known and can only be estimated. But coarse grain gating VVDD
designs have significantly less area penalty than fine grain.
VVDD

VSS

Coarse Grain Fine Grain

37
Static Power Reduction Techniques
 Comparison between two methods as the following table:

Parameter Fine Grain Coarse Grain

Reduce leakage 10x 50x
Wakeup time Fast Slow
Wakeup power Small Large
Library requirements New cell library New footer or header cell

Sensitive to PVT variation Large Small

Can be implemented by usual physical synthesis Yes No

IR-drop variations Large Small

Chip Area Large Small

• Today, virtually all power gated designs use coarse grain power gating.

38
Static Power Reduction Techniques
 Power Gating Challenges :
• Minimizing the impact of power gating on timing and area.

• Design of the power gating controller.

• Design of the power switching fabric.

• The functional control of clocks and resets.

• Developing the correct constraints for implementation and analysis.

• Managing the in-rush current when the power is reconnected.

• Interface isolation.

• Selection and use of retention registers and isolation cells.

• Performing state-dependent verification for each supported power state.

• Performing power state transition verification to ensure all legal state entry and exit arcs are simulated and verified.

39
Static Power Reduction Techniques
 Dynamic and Leakage Power Profiles

An example activity profile for a sub-system using clock gating to reduce power

• SLEEP events initiate entry to the low power mode & WAKE events initiate return to active mode.

• Figure shows Realistic Profile with Power Gating. The leakage power savings are not perfect and instantaneous; the full leakage
power savings take some time to reach target levels. This is due partly to the hotter thermal profile of the preceding activity and
partly to the non-ideal nature of the power-gating technology. Therefore, the achievable savings are compromised to some extent.

40
Static Power Reduction Techniques
 A simplified view of an SoC that uses internal power gating is shown.

• Unlike a block that is always powered on, the power-gated block receives its power
through a power-switching network. This network switches either VDD or VSS to the
power gated block. In this example, VDD is switched; VSS is provided directly to the
entire chip. The switching fabric typically consists of large umber of CMOS switches
distributed around or within the power gated block.

• One challenge for power gating designs is that the outputs of the power gated block
may ramp off very slowly. The result could be that these outputs spend a significant
amount of time at threshold voltage, causing large crowbar currents in the always
powered on block. To prevent these crowbar currents, isolation cells (the “Isol” block
in the figure) are placed between the outputs of the power gated block and the inputs
of the always on block. These isolation cells are designed so that they do not
experience crowbar current when one of the inputs is at threshold, as long as the
control input is off. The power gating controller provides this isolation control signal.

 Special Cell Used for power Gating:

• Isolation Cells

• Header Cells

• Retention Registers
41
Static Power Reduction Techniques
 Isolation Cells:

• The outputs of the power gated block are the primary concern, since they can
cause electrical or functional problems in other blocks.
VDD2
VDD
• The inputs to the power gated blocks usually are not an issue they can be driven IN
to valid logic values by powered up blocks without creating electrical (or OUTSimplified logic model
EN
functional) problems in the powered down block.
VSS
• There are three basic types of isolation cell: D D

Those that clamp the signal to “0”, Q

Q

Those that clamp it to “1”, ISO

ISO

Those that latch it to the most recent value

Logic Symbol of Logic Symbol of
• In most cases, it is sufficient to clamp the output to an inactive state. When using Clamp 0 Isolation Cell Clamp 1 Isolation Cell
active high logic, the most common approach is to clamp the value to “0”. An (Logic AND) (Logic OR)
AND-gate function accomplishes this. With active low logic, an OR-gate Hold 0 Isolation Cell Hold 1 Isolation Cell
function parks the output at logic “1”. (Logic AND) Truth Table (Logic OR) Truth Table

• Clamp library cells are designed to avoid crowbar currents and leakage paths D ISO Q D ISO Q
Bypas Bypas
when signal input floats, if the control input is in the appropriate (“isolate”) s 0 0 0 s
0 1 0
state. In addition, their extra attributes to ensure these cells never get optimized mode
1 0 1 mode
1 1 1
away, buffered incorrectly or inverted as part of logic optimization X 1 1
X 0 0
Output
clamped 42
Static Power Reduction Techniques
 Recommendation When using Isolation Cells:

• Make sure the isolation cells are always powered on.

• Isolation clamps on clocks can considerably complicate clock tree synthesis and timing closure. Clock tree balancing can become
difficult. If possible, avoid clocks that are generated in a power gated block and used externally to the block.

• Since the Power Gated Controller manages all the power gating inside a design, it enables the isolation enable signal before power
gating to make sure there is no ‘X’ value propagated to [on-domain] after power is cut off.

• Ensure that stuck-at-0 and stuck-at-1 faults can be detected during test on the isolation control signals. This facilitates verifying
during manufacturing test that isolation works.

• Example on Isolation Cells :

Always on
domain

43
Static Power Reduction Techniques
 Retention Registers : preserve status while the power-gated block is turned off

• Another approach to providing state retention while power gating is to replace a standard register with a retention register.

• A retention register contains a “shadow” register that can preserve the registers state during power down and restore it at power up.

When SAVE is asserted, the state of the main register When RETAIN goes high, the state of the main
is loaded into the shadow register. register is loaded into the shadow register.
When RESTORE is asserted, the state of the shadow When RETAIN goes low, the state of the shadow
register is loaded back into the main register. register is loaded back into the main register.
SAVE and RESTORE are level-sensitive signals. RETAIN is an edge-sensitive signal.

45
UPF
 UPF stands for unified power format. It’s power format specification to implement low
power techniques in a design flow. UPF is designed to reflect the power intent of a design at a
relatively high level
• UPF 1.0 was defined by Accellera
• UPF 2.0 defined by IEEE
• UPF 2.1 – UPF3.1
- Added new capabilities
- New commands

 At each design stage the UPF is used along with the RTL/Verilog.
At RTL level Simulation, Simulators understand power intent and do power aware verification.

 UPF divided to:

Power Architecture Power strategies
- Power domain - Power state tables
- Supply rails - Operating voltages
- Shutdown control - Isolation cell, level shifters, Switches
- Retention registers

48
References
1. Synopsys University Courseware

2. Advanced Digital Circuits Berkeley Course for Borivoje Nikolić

3. https://www.linkedin.com/company/learnvlsi/

4. https://www.cs.utexas.edu/users/hunt/FMCAD/2007/presentations/Tutorial_Najm.pdf

5. https://www.ece.ucdavis.edu/~ramirtha/EEC216/W08/lecture1_updated.pdf

6. https://vlsi.pro/power-dissipation-leakage-power

7. https://teamvlsi.com/2021/08/integrated-clock-gating-icg-cell-in-vlsi.html/

8. https://vlsitutorials.com/isolation-cells-level-shifter-cells-low-power-vlsi/

9. https://media-exp1.licdn.com/dms/document/C561FAQGpoRcAJIQVmg/feedshare-document-pdf-analyzed/0/16491303
65274?e=2147483647&v=beta&t=kBQgCDk86uJPWRcCbC3CJuexMG5WH_vk1AEN8VYImmU

10. https://www.cnblogs.com/guolongnv/articles/6252690.html

11. UPF Commands Syntax Description: https://vlsitutorials.com/upf-command-syntax-low-power-vlsi/

57