Microprocessor Architecture

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 UNIT 1

Microprocessor Architecture:
Introduction to Microprocessors, Architecture of
8085, Pin Configuration and Function; internal register & flag
register, Generation of Control Signals: Bus Timings:
Demultiplexing of address / data bus; Fetch Cycle, Execute
Cycle, Instruction Cycle, Instruction Timings and Operation
Status, Timing Diagram.

MICROPROCESSOR 2
 UNIT 2
Instruction Set and Programming with 8085:
Instruction for Data Transfer. Arithmetic and Logical Operations.
Branching Operation: Machine Cycle Concept; Addressing Modes;
Instructions Format: Stacks. Subroutine and Related Instructions.
Elementary Concepts of Assemblers, Assembler Directives, Looping
and Counting: Software Counters with Time Delays: Simple
Programs using Instruction Set of 8085: Debugging: Programs
Involving Subroutines. Programs for Code Conversion e.g. BCD to
Binary, Binary to BCD. Binary to Seven-Segment LED Display. Binary
to ASCII. ASCII to Binary: Program for Addition Subtraction:
Programs for Multiplication and Division of Unsigned Binary
Numbers.

MICROPROCESSOR 3
 UNIT 3

Data Transfer and Device Selection:

Format of Data Transfer: Modes of Data Transfer: Type of I/O
Addressing: Condition of Data Transfer: Microprocessor Controlled
Data Transfer: Peripheral Controlled Data Transfer: Absolute and
Linear Select Decoding: Memory and I/O Interfacing: Use of
Decoders Selection: Memory organization and Mapping.

MICROPROCESSOR 4
 UNIT 4

Interrupts:
Restart Instruction; Hardware Implementation: Interrupt
Processing; Multiple Interrupts and Priority Concepts: Interrupt
Structure of 8085: Instructions related to interrupts: Pending
Interrupts: Use of Interrupt and Handshaking Signals in Interfacing:
Application of Interrupts and Illustrative Programs.

MICROPROCESSOR 5
 UNIT 5

Architecture of Peripheral Interfacing Devices:

Architecture, Pin Diagram and functioning of 8155/8156 (RAM),
8355/8755 (ROM), 8255 (PPI). Simple programs like Initialization and
I/O operations of the ports, Timer operation of 8155.
Programmable Internal Timer 8253/8254: Block Diagram, Pin
Configuration, Modes, Initialization Instruction, Interfacing and
Simple Programmes to generate various types of signals.
Architecture, Pin diagram, description and initialization of Keyboard
and display interface (8279), USART (8251)

MICROPROCESSOR 6
 Microprocessor Architecture
• The microprocessor can be programmed to
perform functions on given data by writing
specific instructions into its memory.
– The microprocessor reads one instruction at a
time, matches it with its instruction set, and
performs the data manipulation specified.
– The result is either stored back into memory or
displayed on an output device.

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 The 8085 Architecture
• The 8085 uses three separate busses to
perform its operations
– The address bus.
– The data bus.
– The control bus.

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 The Address Bus
– 16 bits wide (A0 A1…A15)
• Therefore, the 8085 can access locations with numbers from 0
to 65,536. Or, the 8085 can access a total of 64K addresses.

– “Unidirectional”.
• Information flows out of the microprocessor and into the
memory or peripherals.

– When the 8085 wants to access a peripheral or a memory

location, it places the 16-bit address on the address bus
and then sends the appropriate control signals.

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 The Data Bus
– 8 bits wide (D0 D1…D7)
– “Bi-directional”.
• Information flows both ways between the
microprocessor and memory or I/O.

– The 8085 uses the data bus to transfer the binary

information.

– Since the data bus has 8-bits only, then the 8085
can manipulate data 8 bits at-a-time only.
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 The Control Bus
– There is no real control bus. Instead, the control
bus is made up of a number of single bit control
signals.

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Example: Instruction Fetch Operation
 The 8085 Bus Structure
The 8-bit 8085 CPU (or MPU – Micro Processing Unit) communicates with the other units using a
16-bit address bus, an 8-bit data bus and a control bus.

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8085 Functional Block Diagram

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 The 8085 Microprocessor

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 8085 Notes
• The 8085 microprocessor has 2
differentiators
The low order address bus of 8085
is multiplexed with the data bus.
The bus need to be Demultiplexed

Appropriate control signals need to

be generated to interface memory
and I/O with the 8085

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 8085 Notes
• All signals can be classified in to 6 groups:
Address bus
Data bus
Control and Status signals
Power supply & Frequency signals
Externally initiated signals
Serial I/O ports

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 8085 Notes
• Multiplexed Address/Data bus

The signal lines AD7 – AD0 are bidirectional, they are used as low
order address bus as well as the data bus

During the execution an instruction

- In Early Cycle, it will be Address bus
- Later Cycle(s), it will be Data bus

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 8085 Notes
• Control & Status signals

2 control signals - RD & WR

3 status signals - IO/M, S1 & S0 to identify the nature of
the operation
1 special signal - ALE to indicate the operation

ALE - This positive pulse is generated every time the 8085 begins an operation. It
indicates that the bits on AD7 – AD0 are address bits. This signal latches the low order
address from the multiplexed bus and generates a separate set of eight address lines
A7 – A0.

RD - This is active low control signal, this signal indicates a “read” data from I/O or
memory

WR - This is active low control signal, this signal indicate that the data on the data bus
will be written onto the I/O or memory

IO/M - This status signal is used to differentiate between the IO and memory. When it
is high IO will be selected. If low, then memory is selected. This signal is combined
with RD & WR for read or write operation

S1 & S0 - status signals, used for identifying various operations

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 8085 Notes
• Power supply and Clock frequency:-
Vcc = + 5v
Vss = Ground/Gnd/0 Volts
• X1, X2: with RC/LC network to operate
system - 3MHz to 6MHz
• CLK - Clock output, used as system clock for
other devices

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 8085 Notes - Externally initiated Signals
including Interrupts
• INTR (input) - INTerrupt Request, used as a general purpose
interrupt.

• INTA (output) - INTerrupt Acknowledge - used to acknowledge an

interrupt

• RST 7.5, RST 6.5, RST 5.5 (inputs) - ReSTart interrupts - have higher
priorities than the INTR interrupt

• TRAP (input) – Non Maskable interrupt & has highest priority

• HOLD (input) - indicates that a peripherals like DMA controller is

requesting for the use of address bus and data bus

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 8085 Notes – other signals
• HLDA (output) - HoLD Acknowledge - signal to acknowledge the
assertion of HOLD signal

• READY (input) - this signal is used to delay the mP read or write

cycles. When this signal goes low , the mP waits for an integral
number of clock cycles until it goes high

• RESET IN - When this signal goes low, the PC is set to zero, the buses
are tri-stated & mP is reset

• RESET OUT - signal indicates that the mP is being reset, more

importantly used to reset all other devices

Serial I/O ports

SID (serial input data ) & SOD( serial output data) - data bits are sent
over a single line (one bit at a time)

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8085 Bus Architecture

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8085 programmable Registers

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Another View of the 8085 System Bus

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Memory Read Operation

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Demultiplexing the Bus AD7 – AD0

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Timing :Transfer of byte from memory to MPU

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Data Flow from Memory to the mP

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 Cycles and States

– T- State: One subdivision of an operation. A T-state lasts for one

clock period.
• An instruction’s execution length is usually measured in a
number of T-states. (clock cycles).
– Machine Cycle: The time required to complete one operation of
accessing memory, I/O, or acknowledging an external request.
• This cycle may consist of 3 to 6 T-states.
– Instruction Cycle: The time required to complete the execution
of an instruction.
• In the 8085, an instruction cycle may consist of 1 to 6
machine cycles.
Example: Instruction Fetch Operation

Instruction
(opcode)
reaches the
instruction
decoder now !

It takes four
clock cycles
to get one
instruction
into the CPU.

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 Execution of an Instruction
Now consider the execution of a simple instruction:

 Instruction 3E (hex) means: Load a data byte into

the accumulator

 The instruction is followed by the data byte 32 (hex)

 Two-byte instruction !

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Execution of an Instruction

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Execution of an Instruction

Put the first

memory
location on
the address
bus (2000 h)

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Execution of an Instruction

Get the
instruction
(opcode)
byte from
memory

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Execution of an Instruction

Interpret the
instruction:

Wait for the

data byte !

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Execution of an Instruction

Put the next

memory
location on
the address
bus (2001 h)

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Execution of an Instruction

Get the data

byte from the
memory

Put into
accumulator

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 Basic DMA Operation

02/25/2025 39
 DMA

device device

CPU CPU

memory memory

Conventional data transfer DMA data transfer

02/25/2025 EIE311-CSF-int-dma 40
 DMA (cont.)
• The direct memory access (DMA) I/O technique
provides direct access to the memory while the
microprocessor is temporarily disabled.
• A DMA controller temporarily
– borrows the address bus, data bus, and control bus from the
microprocessor and
– transfers the data bytes directly between an I/O port and a
series of memory locations.
• The DMA transfer is also used to do high-speed
memory-to-memory transfers.

02/25/2025 EIE311-CSF-int-dma 41
 DMA (cont.)
• Two control signals are used to request and
acknowledge a DMA transfer in the microprocessor-
based system.
• The HOLD signal is a bus request signal which asks the
microprocessor to release control of the buses after
the current bus cycle.
• The HLDA signal is a bus grant signal which indicates
that the microprocessor has indeed released control of
its buses by placing the buses at their high-impedance
states.
• The HOLD input has a higher priority than the INTR or
NMI interrupt inputs.

02/25/2025 EIE311-CSF-int-dma 42
 When DMA does not operate

02/25/2025 EIE311-CSF-int-dma 43
 When DMA does not operate

02/25/2025 EIE311-CSF-int-dma 44
 When DMA operates

02/25/2025 EIE311-CSF-int-dma 45
 Example: memory-to-device transfer

02/25/2025 EIE311-CSF-int-dma 46
8237A DMA Block Diagram
 1

Stack and Subroutines

 The Stack 2

• The stack is an area of memory identified by

the programmer for temporary storage of
information. • The stack is a LIFO structure.
- Last In First Out.
• The stack normally grows backwards
into memory.
Memory
- In other words, the
programmer defines the
bottom of the stack and the
stack grows up into The Stack
reducing address range. grows
backwards
into memory Bottom
of the
Stack
 Subroutines 13

• A subroutine is a group of instructions that

will be used repeatedly in different
locations of the program.
- Rather than repeat the same instructions
several times, they can be grouped into a
subroutine that is called from the different
locations.
• In Assembly language, a subroutine can
exist anywhere in the code.
- However, it is customary to place
subroutines separately from the main
program.
 Subroutines 14

• The 8085 has two instructions for dealing

with subroutines.
- The CALL instruction is used to redirect
program execution to the subroutine.
- The RET insutruction is used to
return the execution to the calling
routine.
 The CALL Instruction 15

• CALL 4000H (3 byte instruction)

- When CALL instruction is fetched, the
MP knows that the next two Memory
location contains 16bit subroutine
address in the memory.
2000 CALL 4000
2003
4 0 00 [W] [Z]Register

PC 2003
FFFB
FFFC
FFFD 03
FFFE 20
FFFF SP
 The CALL Instruction 16

- MP Reads the subroutine address from the

next two memory location and stores the
higher order 8bit of the address in the W
register and stores the lower order 8bit of the
address in the Z register - Pushe the address
of the instruction immediately following the
CALL onto the stack [Return address]
- Loads the program counter with the 16-bit
address supplied with the CALL instruction
from WZ register.
 The RET Instruction 17

• RET (1 byte instruction)

- Retrieve the return address from the top
of the stack
- Load the program counter with the
return address.

PC 2003
FFFB
4014 FFFC
4015 RET FFFD 03 SP
FFFE 20
FFFF
 The Stack 3

• Given that the stack grows backwards into

memory, it is customary to place the bottom
of the stack at the end of memory to keep it
as far away from user programs as possible.
• In the 8085, the stack is defined by
setting the SP (Stack Pointer) register.
• LXI SP, FFFFH
• This sets the Stack Pointer to location
FFFFH (end of memory for the 8085).
• The Size of the stack is limited only
by the available memory
 Saving Information on the Stack 4

• Information is saved on the stack by

PUSHing it on.
- It is retrieved from the stack by POPing it off.

• The 8085 provides two instructions: PUSH

and POP for storing information on the
stack and retrieving it back.
- Both PUSH and POP work with register
pairs ONLY.
 The PUSH Instruction 5

• PUSH B (1 Byte Instruction)

- Decrement SP
- Copy the contents of register B to the
memory location pointed to by SP
- Decrement SP
- Copy the contents of register C to the
memory location pointed to by SP
B C
12 F3
FFFB
FFFC
FFFD F3
FFFE 12
FFFF SP
 The POP Instruction 6

• POP D (1 Byte Instruction)

- Copy the contents of the memory location
pointed to by the SP to register E
- Increment SP
- Copy the contents of the memory location
pointed to by the SP to register D
- Increment SP
D E
12 F3
FFFB
FFFC
FFFD F3 SP
FFFE 12
FFFF
 Operation of the Stack 7

• During pushing, the stack operates

in a “decrement then store” style.
- The stack pointer is decremented first,
then the information is placed on the
stack.
• During poping, the stack operates in a “use
then increment” style.
- The information is retrieved from the top of the
the stack and then the pointer is incremented. •
The SP pointer always points to “the top of
the stack”.
 LIFO 8

• The order of PUSHs and POPs must be opposite of

each other in order to retrieve information back
into its original location.

PUSH B
PUSH D

POP D
POP B

• Reversing the order of the POP instructions will

result in the exchange of the contents of BC and
DE.
 The PSW Register Pair 9

• The 8085 recognizes one additional register

pair called the PSW (Program Status Word).
- This register pair is made up of the
Accumulator and the Flags registers.

• It is possible to push the PSW onto the

stack, do whatever operations are needed,
then POP it off of the stack.
- The result is that the contents of the
Accumulator and the status of the Flags
are returned to what they were before the
operations were executed.
 PUSH PSW Register Pair 10

• PUSH PSW (1 Byte Instruction)

- Decrement SP
- Copy the contents of register A to the
memory location pointed to by SP
- Decrement SP
- Copy the contents of Flag register to the
memory location pointed to by SP
A Flag
12 80
FFFB
FFFC
FFFD 80
FFFE 12
FFFF SP
 Pop PSW Register Pair 11

• POP PSW (1 Byte Instruction)

- Copy the contents of the memory location
pointed to by the SP to Flag register
- Increment SP
- Copy the contents of the memory location
pointed to by the SP to register A
- Increment SP

A Flag
12 80
FFFB
FFFC
FFFD 80 SP
FFFE 12
FFFF
 Interrupts
• Interrupt is a process where an external device can get
the attention of the microprocessor.
– The process starts from the I/O device
– The process is asynchronous.
• Classification of Interrupts
– Interrupts can be classified into two types:
• Maskable Interrupts (Can be delayed or Rejected)
• Non-Maskable Interrupts (Can not be delayed or Rejected)

• Interrupts can also be classified into:

• Vectored (the address of the service routine is hard-wired)
• Non-vectored (the address of the service routine needs to be supplied externally
by the device)

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 Interrupts
• An interrupt is considered to be an emergency signal
that may be serviced.
– The Microprocessor may respond to it as soon as possible.

• What happens when MP is interrupted ?

– When the Microprocessor receives an interrupt signal, it
suspends the currently executing program and jumps to
an Interrupt Service Routine (ISR) to respond to the
incoming interrupt.
– Each interrupt will most probably have its own ISR.

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 Responding to Interrupts
• Responding to an interrupt may be immediate or
delayed depending on whether the interrupt is
maskable or non-maskable and whether interrupts are
being masked or not.
• There are two ways of redirecting the execution to the
ISR depending on whether the interrupt is vectored or
non-vectored.
– Vectored: The address of the subroutine is already known
to the Microprocessor
– Non Vectored: The device will have to supply the address of
the subroutine to the Microprocessor
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 The 8085 Interrupts
• When a device interrupts, it actually wants the
MP to give a service which is equivalent to asking
the MP to call a subroutine. This subroutine is
called ISR (Interrupt Service Routine)
• The ‘EI’ instruction is a one byte instruction and is
used to Enable the non-maskable interrupts.
• The ‘DI’ instruction is a one byte instruction and
is used to Disable the non-maskable interrupts.
• The 8085 has a single Non-Maskable interrupt.
– The non-maskable interrupt is not affected by the
value of the Interrupt Enable flip flop.

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 The 8085 Interrupts
• The 8085 has 5 interrupt inputs.
– The INTR input.
• The INTR input is the only non-vectored interrupt.
• INTR is maskable using the EI/DI instruction pair.

– RST 5.5, RST 6.5, RST 7.5 are all automatically vectored.
• RST 5.5, RST 6.5, and RST 7.5 are all maskable.

– TRAP is the only non-maskable interrupt in the 8085

• TRAP is also automatically vectored

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 The 8085 Interrupts

Interrupt name Maskable Vectored

INTR Yes No
RST 5.5 Yes Yes
RST 6.5 Yes Yes
RST 7.5 Yes Yes
TRAP No Yes

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 8085 Interrupts

TRAP
RST7.5
RST6.5
RST 5.5
8085
INTR
INTA

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 The 8085 Non-Vectored Interrupt Process

• The 8085 recognizes 8 RESTART instructions:

RST0 - RST7.
– each of these would send the execution to a
predetermined hard-wired memory location:
Restart Equivalent
Instruction to
RST0 CALL 0000H
RST1 CALL 0008H
RST2 CALL 0010H
RST3 CALL 0018H
RST4 CALL 0020H
RST5 CALL 0028H
RST6 CALL 0030H
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RST7 CALL 0038H
The 8085 Maskable/Vectored Interrupts
• The 8085 has 4 Masked/Vectored interrupt inputs.
– RST 5.5, RST 6.5, RST 7.5
• They are all maskable.
• They are automatically vectored according to the following
table: Interrupt Vector
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH

– The vectors for these interrupt fall in between the vectors for the RST
instructions. That’s why they have names like RST 5.5 (RST 5 and a
half).
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