SYNCHRONOUS SEQUENTIAL CIRCUITS

• The sequential circuits described before perform simple functions such as

shifting and counting. Registers shift data inputs in response to a clock
signal. Similarly, counters generate a predetermined sequence of states and
have no inputs other than the initial conditions and the clock signal.
• The counters discussed so far were constructed by cascading flip-flops to
count in an orderly fashion. Changing the count order requires a sequence of
data input.
• Thus, the design methods designed so far are not adequate to design a
complex sequential circuit.
• A sequential circuit which has additional inputs that may change its present
state is referred to as a finite-state machine (FSM).
• There are two classes of sequential circuits: synchronous and asynchronous.
• If a clock signal is used to control the operation of a sequential circuit, the
circuit is known as a synchronous sequential circuit.
• Asynchronous sequential circuits do not require a clock signal but rely on the
time delays of its components. Propagation delays of logic gates are used as
timing delays to accomplish the required feedback.
• In general, synchronous circuits are easier to design and are used in the vast
majority of practical applications.
 FINITE-STATE MACHINE DESIGN CONCEPTS
• The general structure of a sequential circuit consists of two parts: flip-flops
and combinational circuits. The flip-flops hold the state memory of the
sequential circuit.
• Two structure models can be constructed depending on how the output of
the finite-state machine is related to the state of the flip-flops:

1. The Moore model - In the Moore model the output of the finite-state
machine depends only on the present state of the flip-flops. In other words,
the output does not depend on the present inputs but, rather, on the previous
inputs. The output is not valid until the flip-flops are updated during the
current clock cycle.
 The Moore model

• In the structure of the Moore model above, there is no direct connection

between the inputs and the outputs of a finite-state machine. The output of
a finite-state machine is a function of its present state.
 The Mealy model
• The Mealy model is a variation of the Moore model in which the output of
the finite state machine depends on the present states of the flip-flops and
the present inputs of the finite-state machine.
• The logic expression of the output depends explicitly on the inputs of the
finite-state machine. The output is valid before the flip-flops are updated
during the current clock cycle.
 State Diagram
• A state diagram is a graphical representation that consists of circles (nodes)
and directional arcs. The nodes represent the states and the arcs represent
the transitions between the states.
 State and State Assigned Tables
• A state table is a direct enumeration of a state diagram into a useful table.
The state table, also referred to as a state transition table, is one step closer
to FSM circuit implementation.
 State assigned table
• This is called a state assigned table because binary numbers are assigned
selectively to the states.
 Next-State and Output Logic Functions
• The inputs and the present states are the input columns, and the next states
and the output are the output columns.

• The next states and the outputs of the finite-state machine can be expressed
and simplified using algebraic or graphical manipulations (Karnaugh maps). It
can then be implemented using logic gates and flip-flops.
• Since the present states are delayed versions of the next states, D flip-flops
are better choice for implementation.
 Finite-State Machine Design Procedures
• the following procedure summarizes the steps in the design of a
synchronous sequential circuit (FSM):
1. Obtain the behavior specifications of the finite-state machine.
2. Design a state diagram and state table from a word description using state
labels.
3. Select a starting state for reset conditions.
4. Minimize the number of states, if necessary.
5. Choose state variables and assign binary values to the states.
6. Design a state assigned table from state table or state diagram.
7. Choose a flip-flop type to implement FSM memory.
8. Derive the simplified next-states and output logic expressions.
9. Draw the logic circuit for the finite-state machine.
 FINITE-STATE MACHINE SYNTHESIS
• Synthesis is the process of designing a finite-state machine from a problem
statement which describes its specifications and behavior.
• The finite-state machine is designed using D flip-flops. Other flip-flops such
as JK and T flip-flops can also be used.

Example:
• Below we work with a finite-state machine with one input, x, and one
output, z. Output z is equal to 1 when the sequence 111 has been detected
at the input; otherwise, output z is equal to 0. This finite-state machine is
referred to as a sequence detector.

Figure A:
 Moore Model Design
• Recall that in the Moore model, the output of a finite-state machine depends
only on the present states of the machine. Therefore, input sequence 111
would have occurred in the preceding three clock cycles for output z to change
to 1 (Figure A).
• From the state diagram above, the state table is constructed. Notice that the
output column does not depend on input x as the next state does. Since
there are four states, it takes 2-bit binary numbers to represent the states of
the FSM.
• Assigning the binary values 00, 01, 10, and 11 to states S0, S1, S2, and S3,
respectively, the corresponding state assigned table is illustrated.
 Next-State and Output Logic Expressions of
the FSM
• Once the state assigned table has been constructed, the next-to-last task is
to determine the logic expressions of the next states and the output of the
FSM. Using the Karnaugh map method, the optimized logic expressions are
as follows:
 Logic Implementation of the FSM
• The final step of synthesis is to design a finite-state machine using logic gates
and flip-flops. D flip-flops are the favorite choice due to their straightforward
application. Next states Y1 and Y2 become the inputs D of the flip-flops and
present states y1 and y2 are the outputs Q of the flip-flops.
 Mealy Model Design
• Here, the outputs of the finite-state machine depend not only on the
present states of the FSM but also on the inputs. For the sequence detector
example, the desired input sequence 111 is detected during three clock
cycles: two previous clock cycles and the present clock cycle.
 Mealy Model Design
• In the state table, notice that the output column depends on input x and the
present states, as do the next states.

• Two-bit binary numbers are required to represent the three states of the
FSM. Assigning the binary numbers 00, 01, and 10 to states S0, S1, and S2,
respectively, the state assigned table is as illustrated.
• Notice that the number of states is not a power of 2. An additional don’t-
care state is added and assigned the binary number 11.
 Next-State and Output Logic Expressions of the FSM
• The logic expressions for the next states and output are derived and listed as
follows:

• The don’t-care state was helpful in obtaining simpler logic expressions.

 Mealy-type logic Implementation
• Using D flip-flops, the Mealy-type sequence detector finite-state machine is
implemented by the logic circuit below:
 FINITE-STATE MACHINE ANALYSIS
• Analysis of a finite-state machine is the process of finding the function of the
FSM by determining the relationships among the inputs, the outputs, and
the states of the flip-flops.
• Recall that synthesis of a finite-state machine is the process of finding a
circuit implementation that satisfies the behavior of the FSM.
• On the other hand, analysis is breaking the FSM apart to determine its
behavior and eventually its function.

• Steps to analyze a finite-state machine:

1. Identify the inputs and outputs of the finite-state machine.
2. Determine the logic expressions of the next states and the outputs simply
by reading the logic networks that interconnect the inputs and outputs of the
flip-flops.
3. Determine the number of all possible states, including the don’t-care states.
Recall that the number of states is equal to 2N, where N is the number of flip-
flops of the FSM.
4. Determine the necessary bit size of the binary numbers required to
represent the states of the FSM.
5. Decide on a state assignment and construct a state assigned table using the
next-state and output logic expressions.
6. Construct a state table from the state assigned table.
7. Construct a state diagram from the state table if necessary.
8. Draw or list a sample input–output timing sequence that describes the
behavior of the FSM.
9. Determine the function of the FSM.
 PROBLEMS
• What is a finite-state machine?
• List the procedural steps for finite-state machine design.
• What is a Mealy machine?
• What is a Moore machine, and how does it differ from a Mealy machine?
• Using D flip-flops, design a logic circuit for the finite-state machine described
by the state assigned table below.
• Using D flip-flops, design a logic circuit for the finite-state machine described
by the state assigned table below.

• Using D flip-flops, design a logic circuit for the finite-state machine described
by the state assigned table.
• Consider the finite-state machine logic implementation in Figure P9.32.
(a) Determine the next-state and output logic expressions.
(b) Determine the number of possible states.
(c) Construct a state assigned table.
(d) Construct a state table.
(e) Construct a state diagram.
(f) Determine the function of the finite-state machine.
• Consider the finite-state machine logic implementation in Figure below
(a) Determine the next-state and outputs logic expressions.
(b) Determine the number of possible states.
(c) Construct a state assigned table.
(d) Construct a state table.
(e) Construct a state diagram.
(f) Determine the function of the finite-state machine.
• Design a logic circuit to implement a Moore-type sequence detector to
detect each of the following input sequences.
(a) 000 (b) 100
(c) 001 (d) 101
(e) 010 (f) 110
(g) 011 (h) 111

• Design a logic circuit to implement a Moore-type sequence detector to

detect each of the following input sequences.
(a) 00 and 11
(b) 01 and 10
(c) 10 and 11
(d) 00 and 01