Microprocessor 8086-16 bit

Unit 1
Introduction
8086 Microprocessor is an enhanced version of
8085Microprocessor that was designed by Intel in
1976. It is a 16-bit Microprocessor having 20
address lines and16 data lines that provides up to
1MB storage. It consists of powerful instruction set,
which provides operations like multiplication and
division easily.
It supports two modes of operation, i.e. Maximum
mode and Minimum mode. Maximum mode is
suitable for system having multiple processors and
Minimum mode is suitable for system having a
single processor.
Features
• It has an instruction queue, which is capable of storing six instruction bytes from the memory
resulting in faster processing.
• It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus, and 16-bit
external data bus resulting in faster processing.
• It is available in 3 versions based on the frequency of operation −
• 8086 → 5MHz
• 8086-2 → 8MHz
• (c)8086-1 → 10 MHz
• It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves performance.
• Fetch stage can prefetch up to 6 bytes of instructions and stores them in the queue.
• Execute stage executes these instructions.
• It has 256 vectored interrupts.
• It consists of 29,000 transistors.
Architecture of 8086
Pin description of 8086
AD0-AD15: Address/Data bus. These are low order
address bus. They are multiplexed with data. When
AD lines are used to transmit memory address the
symbol A is used instead of AD, for example A0-
A15. When data are transmitted over AD lines the
symbol D is used in place of AD, for example D0-
D7, D8-D15 or D0-D15.
A16-A19: High order address bus. These are
multiplexed with status signals.
S2, S1, S0: Status pins. These pins are active
during T4, T1 and T2 states and is returned to
passive state (1,1,1 during T3 or Tw (when ready is
inactive). These are used by the 8288 bus
controller for generating all the memory and I/O
operation) access control signals. Any change in
S2, S1, S0 during T4 indicates the beginning of a
bus cycle.
 Flag register
The flag register is a 16-bit register in the Intel 8086 microprocessor that contains
information about the state of the processor after executing an instruction. It is sometimes
referred to as the status register because it contains various status flags that reflect the
outcome of the last operation executed by the processor.
The flag register is an important component of the 8086 microprocessor because it is used to
determine the behavior of many conditional jump and branch instructions. The various flags
in the flag register are set or cleared based on the result of arithmetic, logic, and other
instructions executed by the processor.
The flag register is divided into various bit fields, with each bit representing a specific flag.
Some of the important flags in the flag register include the carry flag (CF), the zero flag (ZF),
the sign flag (SF), the overflow flag (OF), the parity flag (PF), and the auxiliary carry flag (AF).
These flags are used by the processor to determine the outcome of conditional jump
instructions and other branching instructions.
Purpose Register. Depending upon the value of result after any arithmetic and logical
operation the flag bits become set (1) or reset (0).

The sixth one is the overflow flag. The 6 status flags are:
1.Sign Flag (S)
2.Zero Flag (Z)
3.Auxiliary Carry Flag (AC)
4.Parity Flag (P)
5.Carry Flag (CY)
6.Overflow Flag (O)
 Bus Interface Unit(BIU)
BIU takes care of all data and addresses transfers on the buses for the EU like sending addresses,
fetching instructions from the memory, reading data from the ports and the memory as well as
writing data to the ports and the memory.
It has the following functional parts −

•Instruction queue − BIU contains the instruction queue. BIU gets upto 6 bytes of next instructions and
stores them in the instruction queue. When EU executes instructions and is ready for its next instruction,
then it simply reads the instruction from this instruction queue resulting in increased execution speed.
•Fetching the next instruction while the current instruction executes is called pipelining.

•Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the addresses of instructions
and data in memory, which are used by the processor to access memory locations. It also contains 1 pointer
register IP, which holds the address of the next instruction to executed by the EU.
• CS − It stands for Code Segment. It is used for addressing a memory location in the code
segment of the memory, where the executable program is stored.
• DS − It stands for Data Segment. It consists of data used by the program andis accessed in the
data segment by an offset address or the content of other register that holds the offset address.
• SS − It stands for Stack Segment. It handles memory to store data and addresses during
execution.
• ES − It stands for Extra Segment. ES is additional data segment, which is used by the string to
hold the extra destination data.
 Memory Segmentation in 8086 Microprocessor
Segmentation is the process in which the main memory of the computer is
logically divided into different segments and each segment has its own base
address. It is basically used to enhance the speed of execution of the computer
system, so that the processor is able to fetch and execute the data from the
memory easily and fast.
Need for Segmentation –
The Bus Interface Unit (BIU) contains four 16 bit special purpose registers
(mentioned below) called as Segment Registers.

The number of address lines in 8086 is 20, 8086 BIU will send 20bit address,
so as to access one of the 1MB memory locations. The four segment
registers actually contain the upper 16 bits of the starting addresses of the
four memory segments of 64 KB each with which the 8086 is working at that
instant of time. A segment is a logical unit of memory that may be up to 64
kilobytes long. Each segment is made up of contiguous memory locations. It
is an independent, separately addressable unit. Starting address will always
be changing. It will not be fixed.

Advantages of the Segmentation The main advantages of segmentation are as

follows:
• It provides a powerful memory management mechanism.
• Data related or stack related operations can be performed in different
segments.
• Code related operation can be done in separate code segments.
• It allows to processes to easily share data.
• It allows to extend the address ability of the processor, i.e. segmentation
allows the use of 16 bit registers to give an addressing capability of 1
Megabytes. Without segmentation, it would require 20 bit registers.
• It is possible to enhance the memory size of code data or stack
segments beyond 64 KB by allotting more than one segment for each
area.
 Physical Memory Address Generation
8086 has 20bit address line. So the maximum value of address that can be addressed by 8086 is 2^20 = 1MB. So
8086 can address the locations ranging between 00000 H to FFFFF H. This 1MB memory is divided into 16 logical
segments, each with a memory of 64KB. In 8086 one megabyte is physically organized as an odd bank and an even bank, each of
512Kbytes, addresses in parallel by a processor. Byte data with even address transferred on D7-D0 , while byte data with odd address is
transferred on D15-D8 bus lines. To select an even or odd bank its has BHE and Ao as selector lines. Instruction stream is fetched from
memory as words and is addressed internally by a processor. If it fetches a word from memory, the different possibilities are
Both bytes may be data operands
Both bytes may contain opcode
One is opcode while other may be data
Following are the examples to calculate
Physical Address:
1. The code segment(CS) is at 1000H and the destination
index(DI) is at 4000H the physical address can be
calculated by
PA = CS * 10 + DI +Displacement(if any)

CS = 1000H
DI = 4000H
Displacement = 0
PA = 1000H* 10 + 4000H + 0
PA = 14000H
2. The data segment is present at 3000H and source index
is at 3000H then the physical address is
PA = DS * 10 + SI + Displacement( if any)

DS = 3000H
SI = 3000H
Displacement = 0
PA = 3000H * 10 + 3000H +0
PA = 33000H
 Concept of pipelining
Pipelining is a technique used in modern processors to improve performance by executing multiple instructions simultaneously. It breaks down the
execution of instructions into several stages, where each stage completes a part of the instruction. These stages can overlap, allowing the processor
to work on different instructions at various stages of completion, similar to an assembly line in manufacturing.

Following are the 5 stages of the RISC pipeline with their respective operations:
•Stage 1 (Instruction Fetch): In this stage the cpu fetches the instructions from the address present in the memory location whose value is stored in the
program counter.
•Stage 2 (Instruction Decode): In this stage, the instruction is decoded and register file is accessed to obtain the values of registers used in the instruction.
•Stage 3 (Instruction Execute): In this stage some of activities are done such as ALU operations.
•Stage 4 (Memory Access): In this stage, memory operands are read and written from/to the memory that is present in the instruction.
•Stage 5 (Write Back): In this stage, computed/fetched value is written back to the register present in the instructions.
Advantages of Pipelining
•Increased Throughput: Pipelining enhance the throughput capacity of a CPU and enables a number of instruction to be processed at the same
time at different stages. This leads to the improvement of the amount of instructions accomplished in a given period of time, thus improving the
efficiency of the processor.
•Improved CPU Utilization: From superimposing of instructions, pipelining helps to ensure that different sections of the CPU are useful. This gives
no time for idling of the various segments of the pipeline and optimally utilizes hardware resources.
•Higher Instruction Throughput: Pipelining occurring because when one particular instruction is in the execution stage it is possible for other
instructions to be at varying stages of fetch, decode, execute, memory access, and write-back. In this manner there is concurrent processing going
on and the CPU is able to process more number of instructions in a given time frame than in non pipelined processors.
Disadvantages of Pipelining
•Pipeline Hazards: Pipelining may result to data hazards whereby instructions depends on other instructions; control hazards, which arise due to
branch instructions; and structural hazards whereby there are inadequate hardware facilities. Some of these hazards may lead to delays hence tough
strategies to manage them to ensure progress is made.
•Increased Complexity: Pipelining enhances the complexity of processor design as well as its application as compared to non-pipelined structures.
Pipelining stages management, dealing with the risks and correct instruction sequence contribute to the design and control considerations.
•Stall Cycles: When risks are present, pipeline stalls or bubbles can be brought about, and this produces idle times in certain stages in the pipeline.
These stalls can actually remove some of the cycles acquired by pipelining, thus reducing the latter’s efficiency.
Difference between minimum mode and maximum mode in 8086 microprocessor

Minimum mode Maximum mode

There can be only one processor. There can be multiple processors.

Performance is slower. Performance is faster.

The circuit is simple. The circuit is complex.

Multiprocessing cannot be performed. Multiprocessing can be performed.

MN/MX is 1 to indicate the minimum mode. MN/MX is 0 to indicate the maximum mode

The 8086 generates INTA for interrupt acknowledgment. The 8288 Bus Controller generates the interrupt acknowledgment signal
(INTA).

The 8086 itself provides an ALE for the latch. Because there are several processors, the 8288 bus controller provides
ALE for the latch.

The system is more affordable. The system costs more money.

It is used for small systems. It is used for large systems.

The multiprocessor setup is not supported. The multiprocessor configuration is accepted.