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DLD Chapter5

Chapter 5 of the document discusses combinational logic circuits, which are defined by outputs determined solely by current inputs, contrasting with sequential circuits that rely on storage elements. It outlines the design procedure for these circuits, including understanding operations, creating truth tables, and drawing logic diagrams, while also introducing basic circuits like adders, comparators, multiplexers, and demultiplexers. The chapter concludes with exercises to reinforce understanding of the concepts presented.

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5 views

DLD Chapter5

Chapter 5 of the document discusses combinational logic circuits, which are defined by outputs determined solely by current inputs, contrasting with sequential circuits that rely on storage elements. It outlines the design procedure for these circuits, including understanding operations, creating truth tables, and drawing logic diagrams, while also introducing basic circuits like adders, comparators, multiplexers, and demultiplexers. The chapter concludes with exercises to reinforce understanding of the concepts presented.

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bekema
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Kibur College

Department of Computer science


Digital Logic Design

Chapter 5:Combinational Logic Circuit


1
Introduction
 Logic circuit for digital systems maybe combinational or sequential.
 A combinational circuit consists of logic gates whose outputs at
any time are determined from only the present combination of inputs.
 A combinational circuit performs an operation that can be specified
logically by a set of Boolean functions.
 In contrast, sequential circuits employ storage elements in
addition to logic gates.
 The outputs of sequential circuits are a function of the input and the
state of the storage elements.

2
DESIGN PROCEDURE
 The design of combinational circuits starts from the specification of the design objectives and
is converted to a set of Boolean functions from which the logic diagram can be obtained.

 The procedure involves the following steps;


1. Understand the full operation
2. Determine the required number of inputs and outputs and assign a symbol to each.
3. Derive the truth table that defines the required relationship between inputs and outputs.
4. Obtain the simplified Boolean functions for each output as a function of the input variables.
5. Draw the logic diagram and verify the correctness of the design.

3
Basic Combinational Logic
Circuits
• AND-OR logic circuit
• Directly implements an SOP expression.
• AND-OR-Inverter logic circuit
• This kind of implementation leads to POS expression.
• Exclusive-OR logic circuit
• A combination of two AND gates, one OR gate and two inverters.
• Exclusive-NOR logic circuit
• Implemented by simply inverting the output of an exclusive-OR
4
AND-OR LOGIC
• Figure shows an AND-OR circuit consisting of
two 2-input AND gates and one 2-input OR gate.
AND-OR-INVERT LOGIC
• When the output of an AND-OR circuit is complemented (inverted), it results in an
ANDOR-Invert circuit.
• Product-of-sum(POS) expressions can be implemented with AND-OR-Invert logic. This is
illustrated as follows, by developing the corresponding AND-OR-Invert (AOI) expression.
EXCLUSIVE-OR LOGIC
• Although, because of the importance of exclusive-OR gate, this circuit is
considered a type of logic gate with its own unique symbol, it is actually a
combination of two AND gates, one OR gate, and two inverters, as shown in
Figure.
Adders
• Adders are important in computers and also in other types of digital systems in which numerical data are
processed, as you have seen. An understanding of the basic adder operation is fundamental to the study of
digital systems. In this section, the half-adder and the full-adder are introduced.

• After completing this section, you should be able to


 Describe the function of a half-adder.

 Draw a half-adder logic diagram.

 Describe the function of the full-adder.

 Draw a full-adder logic diagram using half-adders.

 Implement a full-adder using and-or logic.


The Half-adder
… cont’d
• A half-adder is represented by the logic symbol
… cont’d
The Full-adder
• The second category of adder is the full-adder.*
• The full-adder accepts two input bits and an input carry and
generates a sum
output and an output carry.
• The basic difference between a full-adder and a half-adder is that the full-adder accepts
an
input carry. A logic symbol for a full-adder is shown in Figure , and the truth table.
Full-adder implemented with half-adders.
Example
For each of the three full-adders in Figure, determine the outputs for the inputs shown.
Parallel Adders

• Two or more full-adders are connected to form parallel binary adders.

• Single full-adder is capable of adding two 1-bit numbers and an input carry.

• To add binary numbers with more than one bit, you must use additional full-adders.

• To add two binary numbers, a full-adder is required for each bit in the numbers. So for 2-
bit numbers, two adders are needed; for 4-bit numbers, four adders are used; and so on.
Block Diagram Of A 2-bit Parallel Adder Using Two Full-adders.
Example
Determine the sum generated by the 3-bit parallel adder in Figure and show
the intermediate carries when the binary numbers 101 and 011 are being

added.
Four-bit Parallel adders
• A group of four bits is called a nibble.
• A basic 4-bit parallel adder is implemented with four full-adder
stages as shown in Figure.
Example
Use the 4-bit parallel adder find the sum and output carry for the
addition of the following two 4-bit numbers if the input carry (Cn-1)
is 0:

A4A3A2A1 = 1100 and B4B3B2B1 = 1100


… Cont’d
Comparators

• The basic function of a comparator is to compare the


magnitudes of two binary quantities to determine the
relationship of those quantities.

• In its simplest form, a comparator circuit determines whether

two numbers are equal.


Equality

• The exclusive-nor gate can be used as a basic comparator


because its output is a 0 if the two input bits are not equal and a
1 if the input bits are equal.

• In order to compare binary numbers containing two bits each,


an
additional XOR gate is necessary
Logic diagram for equality comparison of two 2-bit numbers
Example
• Apply each of the following sets of binary numbers to the comparator inputs in
Figure, and determine the output by following the logic levels through the
circuit.
(a) 10 and 10 (b) 11 and 10
• solution
(a) The output is 1 for inputs 10 and 10, as shown in Figure (a).
(b) The output is 0 for inputs 11 and 10, as shown in Figure (b).
The Basic Binary Decoder
Home work
1. Design a decoder for 3 binary input
2. Design a binary(4) to HEX Decoder
3. Design a HEX to BCD Encoder
Multiplexers (Data Selectors)
• A multiplexer (mux) is a device that allows digital information from several
sources to be
routed onto a single line for transmission over that line to a common destination.
• The basic multiplexer has several data-input lines and a single output line.
• It also has data-select inputs, which permit digital data on any one of the inputs
to be switched to the output line.
• Multiplexers are also known as data selectors.
Cont’d
• In a multiplexer, data goes from
several lines to one line.
• A logic symbol for a 4-input
multiplexer (MUX) is shown in
Figure.
• Notice that there are two data-
select lines because with two select
bits, any one of the four data-input
lines can be selected.
Cont’d
• A 2-bit code on the data-select (S) inputs will allow the data on the
selected data input to pass through to the data output.
• If a binary 0 (S1 = 0 and S0 = 0) is applied to the data-select lines, the data on input
D0 appear on the data-output line.
• If a binary 1 (S1 = 0 and S0 = 1) is applied to the data-select lines, the data on input
D1 appear on the data output.
• If a binary 2 (S1 = 1 and S0 = 0) is applied, the data on D2 appear on the output.
• If a binary 3 (S1 = 1 and S0 = 1) is applied, the data on D3 are switched to the output
line.
Cont’d
Cont’d
Cont’d
• Because data can be selected from any one of the input lines,
this circuit is also referred to as a data selector.

logic diagram for a 4-input multiplexer.


An 8-input Data
selector/multiplexer
• The multiplexer shown in Figure
has eight data inputs (D09D7) and,
therefore, three data-select or
address input lines (S09S2).
• Three bits are required to select any
one of the eight data inputs (23 = 8).
• We can implement 8x1 Multiplexer using lower order Multiplexers easily by
considering the above Truth table. The block diagram of 8x1 Multiplexer is
shown in the following figure.
Class Exercise
• Construct a 16X1 multiplexer with two 8 X 1 and one 2 X 1 multiplexers. Use
block diagrams.
Solution
Demultiplexer
• A demultiplexer (DEMUX) basically reverses the multiplexing function.
• It takes digital information from one line and distributes it to a given number of
output lines.
• For this reason, the demultiplexer is also known as a data distributor. as you will
learn, decoders can also be used as demultiplexers.
• Figure shows a 1-line-to-4-line demultiplexer (DEMUX) circuit.
• The data-input line goes to all of the AND gates.
• The two data-select lines enable only one gate at a time, and the data
appearing on the data-input line will pass through the selected gate to the
associated data-output line.
• In a demultiplexer, data goes from one line to several lines
Chapter Review Exercise
1. For the given inputs, determine the intermediate and final outputs of
the full adder.
CONT’D
2.How could you test two 4-bit numbers for equality?
Cont’d
3.Assume the output of the decoder shown is a logic 1. What are the
inputs to the decoder?

A0 = 0
A1 = 1
1
A2 = 0
A3 = 1
CONT’D

• Construct a 16 × 1 multiplexer with as many 4 × 1 multiplexers and any additional


logic that
you might need. Use block diagrams for the components

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