Carnegie Mellon

14-513 18-613

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Machine-Level Programming I: Basics

15-213/15-513: Introduction to Computer Systems
3rd Lecture, Jan 23, 2024

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Announcements
 Lab 0 due today at midnight – no grace days allowed
 If lab is taking you > 10 hours, consider dropping the course or
preparing to study hard on C over next 3 weeks!
 Handin via autolab (if still on waitlist, submit once off waitlist)
 Lab 1 (datalab) went out Jan 18, is due Feb 1
 Lab 2 (bomb lab) goes out via Autolab on Thurs Jan 25
 Due Feb 8

 Written Assignment 1 goes out Jan 31 (via canvas)

 Bootcamp 2 (debugging & gdb) to be held on Sun Jan 28

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Today: Machine Programming I: Basics

 History of Intel processors and architectures CSAPP 3.1
 Assembly Basics: Registers, operands, move CSAPP 3.3-3.4
 Arithmetic & logical operations CSAPP 3.5
 C, assembly, machine code CSAPP 3.2

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Intel x86 Processors

 Dominate laptop/desktop/server market
 Evolutionary design
 Backwards compatible up until 8086, introduced in 1978
 Added more features as time goes on
 Now 3 volumes, about 5,000 pages of documentation
 x86 is a Complex Instruction Set Computer (CISC)
 Many different instructions with many different formats

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Example: Integer addition in x86 (CISC)

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Intel x86 Processors

 Dominate laptop/desktop/server market
 Evolutionary design
 Backwards compatible up until 8086, introduced in 1978
 Added more features as time goes on
 Now 3 volumes, about 5,000 pages of documentation
 x86 is a Complex Instruction Set Computer (CISC)
 Many different instructions with many different formats (next slide)
 But! only small subset encountered with most Linux programs
 Compare: Reduced Instruction Set Computer (RISC)
 RISC: *very few* instructions, with *very few* modes for each
 RISC can be quite fast (but Intel still wins on speed!)
CISC vs RISC has nothing to do with speed, really … take 15-740
 Current RISC renaissance (e.g., ARM, RISCV), especially for low-power

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Intel x86 Evolution: Milestones

Name Date Transistors MHz
 8086 1978 29K 5-10
 First 16-bit Intel processor. Basis for IBM PC & DOS
 1MB address space
 386 1985 275K 16-33
 First 32-bit Intel processor (IA32). “Flat addressing”; runs Unix.
 Pentium 4E 2004 125M 2800-3800
 First 64-bit Intel x86 processor (x86-64).
 Core 2 2006 291M 1060-3333
 First multicore Intel processor
 Core i7 2008 731M 1600-4400
 Four cores (our shark machines)

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Intel x86 Processors, cont.

 Machine Evolution
 386 1985 0.3M
 Pentium 1993 3.1M Core i7 Skylake
 Pentium/MMX 1997 4.5M
 PentiumPro 1995 6.5M
 Pentium III 1999 8.2M
 Pentium 4 2000 42M
 Core 2 Duo 2006 291M
 Core i7 2008 731M
 Core i7 Skylake 2015 1.9B
 Core i9 Raptor Lake 2023 25.9B
 Added Features
 Instructions to support multimedia operations, efficient conditionals
 Transition from 32 bits to 64 bits
 More cores
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Intel x86 Processors

 Past Generations Process tech.
 1st Pentium Pro 1995 600 nm
Process technology dimension
 1st Pentium III 1999 250 nm
= width of narrowest wires
 1st Pentium 4 2000 180 nm (10 nm ≈ 100 atoms wide)
 1st Core 2 Duo 2006 65 nm
 Recent & Upcoming Generations
1. Nehalem 2008 45 nm
2. Sandy Bridge 2011 32 nm
3. Ivy Bridge 2012 22 nm
4. Haswell 2013 22 nm
5. Broadwell 2014 14 nm
6. Skylake 2015 14 nm
7. Kaby Lake 2016 14 nm
8. Coffee Lake 2017 14 nm
9. Cannon Lake 2018 10 nm
10. Ice Lake 2019 10 nm
11. Tiger Lake 2020 10 nm
12. Alder Lake 2022 “intel 7” (10nm+++)
13. Raptor Lake 2023 “intel 7” (10nm+++)
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Intel’s Latest: Raptor Lake (2023)

In recent years, increasing die space devoted to the graphics/AI engine

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x86 Clones: Advanced Micro Devices (AMD)

 Historically
 AMD had followed just behind Intel
 A little bit slower, a lot cheaper
 Then
 Recruited top circuit designers from Digital Equipment Corp. and
other downward trending companies
 Built Opteron: tough competitor to Pentium 4
 Developed x86-64, their own extension to 64 bits
 Recent Years
 Intel got its act together
 1995-2011: Lead semiconductor “fab” in world
 2015: TSMC becomes leading semiconductor fab; Intel falls behind
 2018-2023: back-and-forth with Samsung for #1 by $$
 Back-and-forth with AMD on performance
 Non-x86 GPUs from Nvidia now dominate compute market
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Our Coverage
 IA32
 The traditional x86
 For 15/18-213: RIP, Summer 2015

 x86-64
 The standard
 shark> gcc hello.c
 shark> gcc –m64 hello.c

 Presentation
 Book covers x86-64
 Web aside on IA32
 We will only cover x86-64
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Today: Machine Programming I: Basics

 History of Intel processors and architectures
 Assembly Basics: Registers, operands, move
 Arithmetic & logical operations
 C, assembly, machine code

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Levels of Abstraction
#include <stdio.h>
int main(){
C programmer int i, n = 10, t1 = 0, t2 = 1, nxt;
for (i = 1; i <= n; ++i){
printf("%d, ", t1);
nxt = t1 + t2;
t1 = t2;
t2 = nxt; }
return 0; } Seems like nice
clean layers…
Assembly programmer

Computer Designer
Gates, clocks, circuit layout, …

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Definitions
 Architecture or ISA (instruction set architecture): The
interface between software and hardware. Aka, the
lowest-level programming interface.
 Examples: instruction set specification, registers, memory model
 Not a specification of the hardware itself.
 Microarchitecture: Implementation of the architecture
 Examples: cache sizes and core frequency
 Much more – eg, modern processors execute instr’ns out-of-order!
 Code Forms:
 Machine Code: The byte-level programs that a processor executes
 Assembly Code: A text representation of machine code
 Example ISAs:
 Intel: x86, IA32, Itanium, x86-64
 ARM: Used in almost all mobile phones, and some laptops/servers
 RISC V: New open-source ISA
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Assembly/Machine Code View

CPU Memory
Addresses
Registers
Data Code
PC Data
Condition Instructions Stack
Codes

Programmer-Visible State
 PC: Program counter  Memory
 Byte addressable array
 Address of next instruction
 Code and user data
 Called “RIP” (x86-64)
 Stack to support procedures
 Register file
 Heavily used program data
 Condition codes
 Store status information about most
recent arithmetic or logical operation
 Used for conditional branching
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Assembly: Data Types

 “Integer” data of 1, 2, 4, or 8 bytes
 Data values
 Addresses (untyped pointers)

 Floating point data of 4, 8, or 10 bytes

 SIMD/vector data types of 8, 16, 32 or 64 bytes

 Code: Byte sequences encoding series of instructions

 No aggregate types such as arrays or structures

 Just contiguously allocated bytes in memory

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Assembly: Data Types

 “Integer” data of 1, 2, 4, or 8 bytes
 Data values
 Addresses (untyped pointers)
Register names

addq
add %rbx, %rax

is

rax += rbx

These are 64-bit registers, so we

know this is a 64-bit add

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x86-64 Integer Registers

%rax %eax %r8 %r8d

%rbx %ebx %r9 %r9d

%rcx %ecx %r10 %r10d

%rdx %edx %r11 %r11d

%rsi %esi %r12 %r12d

%rdi %edi %r13 %r13d

%rsp %esp %r14 %r14d

%rbp %ebp %r15 %r15d

 Can reference low-order 4 bytes (also low-order 1 & 2 bytes)

 Not part of main memory (or cache)
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Some History: IA32 Registers Origin

(mostly obsolete)

%eax %ax %ah %al accumulate

%ecx %cx %ch %cl counter

general purpose

%edx %dx %dh %dl data

%ebx %bx %bh %bl base

source
%esi %si index

destination
%edi %di index
stack
%esp %sp
pointer
base
%ebp %bp
pointer

16-bit virtual registers

(backwards compatibility) 21
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Assembly: Operations
 Transfer data between memory and register
 Load data from memory into register
 Store register data into memory

 Perform arithmetic function on register or memory data

 Transfer control
 Unconditional jumps to/from procedures
 Conditional branches
 Indirect branches

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Activity 1
Form pairs
 One person open the activity instructions at

https://www.cs.cmu.edu/~213/activities/gdb-and-assembly.pdf

 The other person open a terminal on a shark machine and enter

wget http://www.cs.cmu.edu/~213/activities/gdb-and-
assembly.tar

tar xf gdb-and-assembly.tar

cd gdb-and-assembly

./act1

 Follow the instructions in the pdf and/or on screen

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Moving Data %rax

 Moving Data %rcx
movq Source, Dest %rdx
 Operand Types %rbx
 Immediate: Constant integer data %rsi
Example: $0x400, $-533 %rdi
 Like C constant, but prefixed with ‘$’
 Encoded with 1, 2, or 4 bytes
%rsp
 Register: One of 16 integer registers %rbp
 Example: %rax, %r13
 But %rsp reserved for special use %rN
 Others have special uses for particular instructions
 Memory: 8 consecutive bytes of memory at address given by register
 Simplest example: (%rax)
 Various other “addressing modes” Warning: Intel docs use
mov Dest, Source
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movq Operand Combinations

Source Dest Src,Dest C Analog

Reg movq $0x4,%rax temp = 0x4;

Imm
Mem movq $-147,(%rax) *p = -147;

Reg movq %rax,%rdx temp2 = temp1;

movq Reg
Mem movq %rax,(%rdx) *p = temp;

Mem Reg movq (%rax),%rdx temp = *p;

Cannot do memory-memory transfer with a single instruction

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Simple Memory Addressing Modes

 Normal (R) Mem[Reg[R]]
 Register R specifies memory address
 Aha! Pointer dereferencing in C

movq (%rcx),%rax

 Displacement D(R) Mem[Reg[R]+D]

 Register R specifies start of memory region
 Constant displacement D specifies offset

movq 8(%rbp),%rdx

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Complete Memory Addressing Modes

 Most General Form
D(Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]+ D]
 D: Constant “displacement” 1, 2, or 4 bytes
 Rb: Base register: Any of 16 integer registers
 Ri: Index register: Any, except for %rsp
 S: Scale: 1, 2, 4, or 8 (why these numbers?)

 Special Cases
(Rb,Ri) Mem[Reg[Rb]+Reg[Ri]]
D(Rb,Ri) Mem[Reg[Rb]+Reg[Ri]+D]
(Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]]

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Activity 2

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Example of Simple Addressing Modes

void
whatAmI(<type> a, <type> b)
{
????
whatAmI:
}
movq (%rdi), %rax
movq (%rsi), %rdx
movq %rdx, (%rdi)
movq %rax, (%rsi)
ret

%rsi
%rdi

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Example of Simple Addressing Modes

void swap
(long *xp, long *yp)
{ swap:
long t0 = *xp; movq (%rdi), %rax
long t1 = *yp; movq (%rsi), %rdx
*xp = t1; movq %rdx, (%rdi)
*yp = t0; movq %rax, (%rsi)
} ret

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Understanding Swap()
Memory
void swap Registers
(long *xp, long *yp)
{ %rdi
long t0 = *xp;
%rsi
long t1 = *yp;
*xp = t1; %rax
*yp = t0;
} %rdx

Register Value
%rdi xp
%rsi yp
swap:
%rax t0
movq (%rdi), %rax # t0 = *xp
%rdx t1 movq (%rsi), %rdx # t1 = *yp
movq %rdx, (%rdi) # *xp = t1
movq %rax, (%rsi) # *yp = t0
ret
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Understanding Swap()
Memory
Registers Address
123 0x120
%rdi 0x120
0x118
%rsi 0x100
0x110
%rax 0x108
%rdx 456 0x100

swap:
movq (%rdi), %rax # t0 = *xp
movq (%rsi), %rdx # t1 = *yp
movq %rdx, (%rdi) # *xp = t1
movq %rax, (%rsi) # *yp = t0
ret

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Understanding Swap()
Memory
Registers Address
123 0x120
%rdi 0x120
0x118
%rsi 0x100
0x110
%rax 123 0x108
%rdx 456 0x100

swap:
movq (%rdi), %rax # t0 = *xp
movq (%rsi), %rdx # t1 = *yp
movq %rdx, (%rdi) # *xp = t1
movq %rax, (%rsi) # *yp = t0
ret

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Understanding Swap()
Memory
Registers Address
123 0x120
%rdi 0x120
0x118
%rsi 0x100
0x110
%rax 123 0x108
%rdx 456 456 0x100

swap:
movq (%rdi), %rax # t0 = *xp
movq (%rsi), %rdx # t1 = *yp
movq %rdx, (%rdi) # *xp = t1
movq %rax, (%rsi) # *yp = t0
ret

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Understanding Swap()
Memory
Registers Address
456 0x120
%rdi 0x120
0x118
%rsi 0x100
0x110
%rax 123 0x108
%rdx 456 456 0x100

swap:
movq (%rdi), %rax # t0 = *xp
movq (%rsi), %rdx # t1 = *yp
movq %rdx, (%rdi) # *xp = t1
movq %rax, (%rsi) # *yp = t0
ret

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Understanding Swap()
Memory
Registers Address
456 0x120
%rdi 0x120
0x118
%rsi 0x100
0x110
%rax 123 0x108
%rdx 456 123 0x100

swap:
movq (%rdi), %rax # t0 = *xp
movq (%rsi), %rdx # t1 = *yp
movq %rdx, (%rdi) # *xp = t1
movq %rax, (%rsi) # *yp = t0
ret

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Simple Memory Addressing Modes

 Normal (R) Mem[Reg[R]]
 Register R specifies memory address
 Aha! Pointer dereferencing in C

movq (%rcx),%rax

 Displacement D(R) Mem[Reg[R]+D]

 Register R specifies start of memory region
 Constant displacement D specifies offset

movq 8(%rbp),%rdx

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Address Computation Examples

%rdx 0xf000
%rcx 0x0100

Address
Expression Address
Computation
0x8(%rdx) 0xf000 + 0x8 0xf008
(%rdx,%rcx) 0xf000 + 0x100 0xf100
(%rdx,%rcx,4) 0xf000 + 4*0x100 0xf400
0x80(,%rdx,2) 2*0xf000 + 0x80 0x1e080
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Address Computation Examples

%rdx 0xf000
%rcx 0x0100

Address
Expression Address
Computation
0x8(%rdx) 0xf000 + 0x8 0xf008
(%rdx,%rcx) 0xf000 + 0x100 0xf100
(%rdx,%rcx,4) 0xf000 + 4*0x100 0xf400
0x80(,%rdx,2) 2*0xf000 + 0x80 0x1e080
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Quiz Time!

Check out:

https://canvas.cmu.edu/courses/39547/quizzes/118132

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Today: Machine Programming I: Basics

 History of Intel processors and architectures
 Assembly Basics: Registers, operands, move
 Arithmetic & logical operations
 C, assembly, machine code

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Address Computation Instruction

 leaq Src, Dst
 Src is address mode expression
 Set Dst to address denoted by expression

 Uses
 Computing addresses without a memory reference
E.g., translation of p = &x[i];
 Computing arithmetic expressions of the form x + k*y
 k = 1, 2, 4, or 8
 Example
long
long m12(long
m12(long x)
x)
{
Converted to ASM by compiler:
{
return
return x*12;
x*12; leaq
leaq (%rdi,%rdi,2),
(%rdi,%rdi,2), %rax
%rax #
# t
t =
= x+2*x
x+2*x
}
} salq
salq $2,
$2, %rax
%rax #
# return
return t<<2
t<<2
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Some Arithmetic Operations

 Two Operand Instructions:
FormatComputation
addq Src,Dest Dest = Dest + Src
subq Src,Dest Dest = Dest  Src
imulq Src,Dest Dest = Dest * Src
salq Src,Dest Dest = Dest << Src Also called
shlq
sarq Src,Dest Dest = Dest >> Src Arithmetic
shrq Src,Dest Dest = Dest >> Src Logical
xorq Src,Dest Dest = Dest ^ Src
andq Src,Dest Dest = Dest & Src
orq Src,Dest Dest = Dest | Src
 Watch out for argument order! Src,Dest
(Warning: Intel docs use “op Dest,Src”)
 No distinction between signed and unsigned int (why?) 43
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Some Arithmetic Operations

 One Operand Instructions
incq Dest Dest = Dest + 1
decq Dest Dest = Dest  1
negq Dest Dest =  Dest
notq Dest Dest = ~Dest

 See book for more instructions

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Example: Integer addition in x86 (CISC)

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Arithmetic Expression Example

arith:
leaq (%rdi,%rsi), %rax
long
long arith
arith addq %rdx, %rax
(long
(long x,
x, long
long y,y, long
long z)z) leaq (%rsi,%rsi,2), %rdx
{
{ salq $4, %rdx
long
long t1
t1 == x+y;
x+y; leaq 4(%rdi,%rdx), %rcx
long
long t2
t2 == z+t1;
z+t1; imulq %rcx, %rax
long
long t3
t3 == x+4;
x+4; ret
long
long t4
t4 == y
y ** 48;
48;
long
long t5
t5 == t3
t3 ++ t4;
t4;
Interesting Instructions
long
long rval
rval == t2
t2 *
* t5;
t5;  leaq: address computation
return
return rval;
rval;  salq: shift
}
}  imulq: multiplication
 But, only used once

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Understanding Arithmetic Expression

Example arith:
leaq (%rdi,%rsi), %rax # t1
long
long arith
arith addq %rdx, %rax # t2
(long
(long x,
x, long
long y,y, long
long z)z) leaq (%rsi,%rsi,2), %rdx
{
{ salq $4, %rdx # t4
long
long t1
t1 == x+y;
x+y; leaq 4(%rdi,%rdx), %rcx # t5
long
long t2
t2 == z+t1;
z+t1; imulq %rcx, %rax # rval
long
long t3
t3 == x+4;
x+4; ret
long
long t4
t4 == y
y ** 48;
48;
long
long t5
t5 == t3
t3 ++ t4;
t4; Register Use(s)
long
long rval
rval == t2
t2 *
* t5;
t5; %rdi Argument x
return
return rval;
rval;
}
} %rsi Argument y
%rdx Argument z,
t4
%rax t1, t2, rval
%rcx t5

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Today: Machine Programming I: Basics

 History of Intel processors and architectures
 Assembly Basics: Registers, operands, move
 Arithmetic & logical operations
 C, assembly, machine code

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Turning C into Object Code

 Code in files p1.c p2.c
 Compile with command: gcc –Og p1.c p2.c -o p
 Use debugging-friendly optimizations (-Og)
 Put resulting binary in file p

text C program (p1.c p2.c)

Compiler (gcc –Og -S)

text Asm program (p1.s p2.s)

Assembler (gcc –c or as)

binary Object program (p1.o p2.o) Static libraries

(.a)
Linker (gcc or ld)

binary Executable program (p)

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Compiling Into Assembly

C Code (sum.c) Generated x86-64 Assembly
long plus(long x, long y); sumstore:
pushq %rbx
void sumstore(long x, long y, movq %rdx, %rbx
long *dest) call plus
{ movq %rax, (%rbx)
long t = plus(x, y); popq %rbx
*dest = t; ret
}
Obtain (on shark machine) with command
gcc –Og –S sum.c
Produces file sum.s
Warning: Will get very different results on non-Shark
machines (Andrew Linux, Mac OS-X, …) due to
different versions of gcc and different compiler
settings. 50
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What it really looks like

.globl sumstore
.type sumstore, @function
sumstore:
.LFB35:
.cfi_startproc
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdx, %rbx
call plus
movq %rax, (%rbx)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE35:
.size sumstore, .-sumstore

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What it really looks like

.globl sumstore
Things that look weird
.type sumstore, @function and are preceded by a ‘.’
sumstore: are generally directives.
.LFB35:
.cfi_startproc
pushq %rbx
.cfi_def_cfa_offset 16 sumstore:
.cfi_offset 3, -16 pushq %rbx
movq %rdx, %rbx movq %rdx, %rbx
call plus call plus
movq %rax, (%rbx) movq %rax, (%rbx)
popq %rbx popq %rbx
.cfi_def_cfa_offset 8 ret
ret
.cfi_endproc
.LFE35:
.size sumstore, .-sumstore

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Object Code
Code for sumstore  Assembler
0x0400595:  Translates .s into .o
0x53
0x48  Binary encoding of each instruction
0x89  Nearly-complete image of executable code
0xd3  Missing linkages between code in different
0xe8
files
0xf2
0xff  Linker
0xff  Resolves references between files
0xff •
0x48
Total of 14 bytes  Combines with static run-time libraries
• Each instruction 
E.g., code for malloc, printf
0x89
1, 3, or 5 bytes
0x03  Some libraries are dynamically linked
0x5b • Starts at address  Linking occurs when program begins
0xc3 0x0400595
execution

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Machine Instruction Example

 C Code
*dest = t;  Store value t where designated by
dest
 Assembly
movq %rax, (%rbx)  Move 8-byte value to memory
Quad words in x86-64 parlance
 Operands:
t: Register %rax
dest: Register %rbx
*dest: Memory M[%rbx]
 Object Code
0x40059e: 48 89 03  3-byte instruction
 Stored at address 0x40059e

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Disassembling Object Code

Disassembled
0000000000400595 <sumstore>:
400595: 53 push %rbx
400596: 48 89 d3 mov %rdx,%rbx
400599: e8 f2 ff ff ff callq 400590 <plus>
40059e: 48 89 03 mov %rax,(%rbx)
4005a1: 5b pop %rbx
4005a2: c3 retq

 Disassembler
objdump –d sum
 Useful tool for examining object code
 Analyzes bit pattern of series of instructions
 Produces approximate rendition of assembly code
 Can be run on either a.out (complete executable) or .o file
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Alternate Disassembly
Disassembled

Dump of assembler code for function sumstore:

0x0000000000400595 <+0>: push %rbx
0x0000000000400596 <+1>: mov %rdx,%rbx
0x0000000000400599 <+4>: callq 0x400590 <plus>
0x000000000040059e <+9>: mov %rax,(%rbx)
0x00000000004005a1 <+12>:pop %rbx
0x00000000004005a2 <+13>:retq

 Within gdb Debugger

 Disassemble procedure
gdb sum
disassemble sumstore

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Alternate Disassembly
Disassembled
Object
Code
Dump of assembler code for function sumstore:
0x0400595: 0x0000000000400595 <+0>: push %rbx
0x53 0x0000000000400596 <+1>: mov %rdx,%rbx
0x48 0x0000000000400599 <+4>: callq 0x400590 <plus>
0x89 0x000000000040059e <+9>: mov %rax,(%rbx)
0xd3 0x00000000004005a1 <+12>:pop %rbx
0xe8 0x00000000004005a2 <+13>:retq
0xf2
0xff
0xff
0xff
 Within gdb Debugger
0x48  Disassemble procedure
0x89 gdb sum
0x03
disassemble sumstore
0x5b
0xc3  Examine the 14 bytes starting at sumstore
x/14xb sumstore
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What Can be Disassembled?

% objdump -d WINWORD.EXE

WINWORD.EXE: file format pei-i386

No symbols in "WINWORD.EXE".
Disassembly of section .text:

30001000 <.text>:
30001000: 55 push %ebp
30001001: 8b ec mov %esp,%ebp
30001003: 6a ff
Reverse engineering
push
forbidden by
$0xffffffff
30001005: 68Microsoft
90 10 00End
30 User
push License Agreement
$0x30001090
3000100a: 68 91 dc 4c 30 push $0x304cdc91

 Anything that can be interpreted as executable code

 Disassembler examines bytes and reconstructs assembly source
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Machine Programming I: Summary

 History of Intel processors and architectures
 Evolutionary design leads to many quirks and artifacts
 C, assembly, machine code
 New forms of visible state: program counter, registers, ...
 Compiler must transform statements, expressions, procedures into
low-level instruction sequences
 Assembly Basics: Registers, operands, move
 The x86-64 move instructions cover wide range of data movement
forms
 Arithmetic
 C compiler will figure out different instruction combinations to
carry out computation

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