LECTURE 7:

MEMORY
MANAGEMENT
TOPICS FOR DISCUSSION

Background
Swapping
Contiguous Memory Allocation
Paging
Structure of the Page Table
Segmentation

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 OBJECTIVES
To provide a detailed description of various ways of
organizing memory hardware
To discuss various memory-management techniques,
including paging and segmentation

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BASIC HARDWARE

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PROTECTION OF MEMORY SPACE
USING BASE AND LIMIT REGISTERS
Protection of memory required to ensure correct
operation-must be provided by hardware
o Protect OS from access by user processes
o Protect user processes from one another

One possible implementation is to use a pair of

base and limit registers
o To determine the range of legal addresses that the
process may access
o To ensure that the process can access only these
legal addresses.
o Base register – smallest legal memory address
o Limit register – Size of the range
o In the example given: Program can legally access
all addresses from 300040 through 420939.
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PROTECTION OF MEMORY SPACE
USING BASE AND LIMIT REGISTERS
(CONT…)

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ADDRESS BINDING (1)…

Multistep processing of user program

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ADDRESS BINDING
(CONT…)

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LOGICAL VS. PHYSICAL
ADDRESS SPACE
Logical address – Address generated by the CPU; also referred
to as virtual address
o Logical address space – Set of all logical addresses generated
by a program
Physical address – address seen by the memory unit (i.e)
address loaded into the memory address register (MAR) of the
memory
o Physical address space – Set of all physical addresses
corresponding to the logical addresses generated by a program
Logical and physical addresses are the same in compile-time and
load-time address-binding schemes
Logical (virtual) and physical addresses differ in execution-time
address-binding scheme
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MEMORY-MANAGEMENT UNIT (MMU) -
DYNAMIC RELOCATION USING A
RELOCATION REGISTER

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DYNAMIC LOADING

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DYNAMIC LINKING
Linking postponed until execution time
Small piece of code, called stub, used to locate the
appropriate memory-resident library routine
Stub replaces itself with the address of the routine, and
executes the routine
Operating system needed to check if routine is in
processes’ memory address (if yes, then can go for
execution)
Dynamic linking is particularly useful for libraries
System also known as shared libraries
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SWAPPING (CONT…)

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SWAPPING (3)… Example: Assume a multiprogramming
Environment with a round-robin CPU-
- SCHEMATIC scheduling algorithm

VIEW When each process finishes its quantum,

it will be swapped with another process
by memory manager.

In the meantime, CPU scheduler will

allocate a time slice to some other
process in memory.

Time slice is the period of time for which a

process is allowed to run uninterrupted in a
preemptive multitasking operating system.
The operating system scheduler is run once
every time slice to choose the next process
that needs to be run.
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 SWAPPING (4)… – ROLL OUT,
ROLL IN METHOD
A variant of swapping policy used for priority-based scheduling
algorithms – called Roll out, Roll in
If higher-priority process wants service,
oSwap out the lower-priority process by the memory manager
oLoad and execute the higher-priority process
oSwapped back in the lower-priority process after the finishing of
higher-priority process
If the address binding is done
oAt assembly or load time
A process that is swapped out will be swapped back into the
same memory space it occupied previously
oAt execution time
The process can be swapped into a different memory space
since the physical addresses are computed during execution
time.
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SWAPPING (5) - SWAP TIME (EX:
FOR QUIZ 2)

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CONTIGUOUS MEMORY
ALLOCATION (1)…
Main memory must accommodate both OS and various user
processes
Main memory is usually divided into two partitions:
o Resident operating system, usually held in low memory with
interrupt vector
o User processes then held in high memory
Several processes need to reside in memory at the same time
Need to consider how to allocate available memory to the
processes that are in the input queue
In Contiguous memory allocation, each process is contained in a
single contiguous section of memory
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CONTIGUOUS MEMORY
ALLOCATION (2)…MEMORY
MAPPING

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CONTIGUOUS MEMORY
ALLOCATION (3)… MEMORY
MAPPING
Memory mapping
 Relocation register (Base register) contains value of smallest
physical address
 Limit register contains range of logical addresses (off set)– each
logical address must be less than the limit register
 MMU maps logical address dynamically by adding the value in the
relocation register.
 This mapped address is sent to memory
Advantages:
 Relocation registers are used to protect user processes from each
other, and from changing operating-system code and data
 Every address generated by CPU is checked against these
registers
 Provides an effective way to allow the OS size to change
dynamically 20
CONTIGUOUS MEMORY
ALLOCATION (4)…
Multiple Partition Allocation Method
 Fixed Partition
oDivide the memory into several fixed sized partitions
oEach partition may contain exactly one process.
oDegree of multiprogramming is bound by the number of
partitions
oWhen a partition is free, a process is selected from the
input queue and is loaded into the free partition
oWhen the process terminates, the partition becomes
available for another process
oUsed by IBM OS/360 OS – no longer in use
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CONTIGUOUS MEMORY ALLOCATION
(5)…
Multiple-partition allocation method
 Variable/Dynamic Partition
 Hole – block of available memory; holes of various size are
scattered throughout memory
 When a process arrives, it is allocated memory from a hole
large enough to accommodate it
 Operating system maintains information about:
a) allocated partitions
b) free partitions (hole)

External Fragmentation

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CONTIGUOUS MEMORY ALLOCATION (6)-
DYNAMIC STORAGE-ALLOCATION
PROBLEM
How to satisfy a request of size n from a list of free holes

 First-fit and best-fit better than worst-fit in terms of speed and storage utilization, But suffer
from external fragmentation
 First-fit is generally faster 23
EXTERNAL FRAGMENTATION

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INTERNAL FRAGMENTATION

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EXTERNAL FRAGMENTATION VS
INTERNAL FRAGMENTATION

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EXTERNAL FRAGMENTATION
PROBLEM - SOLUTIONS
A) Compaction (Defragment)
 Shuffle memory contents to place all
free memory together in one large
block
 Compaction cannot be done if
relocation is static and done at
assembly or load time
 Compaction is possible only if
relocation is dynamic, and is done at
execution time
 Simplest compaction algorithm is
o Move all processes toward one
end of memory (normally to the
top)
o Move the holes in the other
direction (normally to the bottom)
o Produces one large hole of
available memory
o Can be expensive
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EXTERNAL FRAGMENTATION
PROBLEM - SOLUTIONS
B) Paging and Segmentation
 Permit the logical address space of the processes to be
noncontiguous (if got some free space, it’ll fit in) and physical
memory is allocated to the process, wherever available.

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PAGING
A memory-management scheme that permits the physical address
space of a process to be noncontiguous
Avoids external fragmentation and the need for compaction
Solves the problem of fitting memory chunks of varying sizes onto
the backing store.
Simple Paging method
o Here main memory is divided into a number of equal-size frames.
o Each process is divided into a number of equal-size pages of the
same length as frames.
o A process is loaded by loading all of its pages into available, not
necessarily contiguous, frames.

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SIMPLE PAGING (1
LEVEL)… - METHOD
Divide physical memory (RAM) into fixed-sized blocks called
frames (size is power of 2, between 512 bytes and 16MB)
Divide logical memory into blocks of same size called pages
Keep track of all free frames
To run a program of size n pages, need to find n free frames
and load program
Set up a page table to translate logical to physical addresses
Internal fragmentation problem arise

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SIMPLE PAGING (2)… -
ADDRESS TRANSLATION SCHEME
Address generated by CPU is divided into:
Page number (p) – used as an index into a page table which
contains base address of each page in physical memory

Page offset (d) – combined with base address to define the

physical memory address that is sent to the memory unit
 Assume the size of the logical address space 2m and page size 2n

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SIMPLE PAGING (3)… -
ADDRESS TRANSLATION
SCHEME

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SIMPLE PAGING (4)… -
PAGING MODEL OF LOGICAL
AND PHYSICAL MEMORY

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 SIMPLE PAGING (5) -
EXAMPLE
1 Page = 4 Bytes
1 Frame = 4 Bytes
F0
P0

P1 F1

P2 F2

P3 F3

F4

P D
F5
2 2

F6

F D F7
3 2

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32-byte memory and 4-byte pages
INTERNAL FRAGMENTATION
PROBLEM IN PAGING
No external fragmentation:
•If paging scheme is used, no external fragmentation
• Any free frame can be allocated to a process that needs it

Problem of internal Fragmentation

•If the memory requirements of a process do not happen to coincide
with page boundaries, the last frame allocated may not be completely
full.

Example:
Assume the page size is 2048 bytes, a process of 72766 bytes will need
35 pages (72766 / 2048) plus 1086 bytes (0.53027*2048).
It will be allocated 36 frames, resulting in internal fragmentation of
2048-1086 =962 bytes (internal fragmentation).
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ALLOCATION OF FREE FRAMES
IN PAGING (1)…

Before allocation After allocation

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ALLOCATION OF FREE
FRAMES IN PAGING (2)

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IMPLEMENTATION OF PAGE
TABLE
Page table is kept in main memory (Make RAM busy most of the time
& use system bus)
Page-table base register (PTBR) points to the page table
Page-table length register (PRLR) indicates size of the page table
In this scheme every data/instruction access requires two memory
accesses. One for the page table and one for the data/instruction.
The two-memory access problem can be solved by the use of a special
fast-lookup hardware cache called associative memory or
translation look-aside buffers (TLBs) – Store in microprocessor
Some TLBs store address-space identifiers (ASIDs) in each TLB
entry – uniquely identifies each process to provide address-space
protection for that process
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ASSOCIATIVE MEMORY
Associative memory – parallel search
Page # Frame #

Address translation (p, d)

 If p is in associative register, get frame # out
 Otherwise get frame # from page table in
memory
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 PAGING HARDWARE
WITH TLB
Successful = 80%
Unsuccessful = 20%

20ns
If the data is not in TLB,
it’ll search in page table

100ns

100ns

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HIT RATIO

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MEMORY PROTECTION
Memory protection implemented by associating
protection bit with each frame

Valid-invalid bit attached to each entry in the page

table:
o“valid (v)” indicates that the associated page is in the
process’ logical address space, and is thus a legal page
o“invalid (i)” indicates that the page is not in the
process’ logical address space

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VALID (V) OR INVALID (I)
BIT IN A PAGE TABLE

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SHARED PAGES
Shared code
One copy of read-only (reentrant) code shared among
processes (i.e., text editors, compilers, window systems).
Shared code must appear in same location in the logical
address space of all processes

Private code and data

Each process keeps a separate copy of the code and data
The pages for the private code and data can appear
anywhere in the logical address space
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SHARED PAGES
EXAMPLE

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STRUCTURE OF THE PAGE
TABLE
Hierarchical Paging

Hashed Page Tables

Inverted Page Tables

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HIERARCHICAL PAGE TABLES
Break up the logical address space into multiple
page tables

A simple technique is a two-level page table

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TWO-LEVEL PAGE-TABLE
SCHEME

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TWO-LEVEL PAGING
EXAMPLE

page offset

pi p2 d

12 10

where pi is an index into the outer page table, and p2 is the displacement
within the page of the outer page table
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ADDRESS-TRANSLATION
SCHEME

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THREE-LEVEL PAGING
SCHEME

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HASHED PAGE TABLES
Common in address spaces for size > 32 bits

The virtual page number is hashed into a page table

 This page table contains a chain of elements hashing to the
same location

Virtual page numbers are compared in this chain searching for

a match
 If a match is found, the corresponding physical frame is
extracted
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HASHED PAGE TABLE

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INVERTED PAGE TABLE

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INVERTED PAGE TABLE
ARCHITECTURE

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SEGMENTATION
Memory-management scheme that
supports user view of memory
A program is a collection of segments
A segment is a logical unit such as:
 Main program  Local variables, global variables
 Procedure  Common block
 Function  Stack
 Method  Symbol table
 Arrays
 Object

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USER’S VIEW OF A PROGRAM

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LOGICAL VIEW OF
SEGMENTATION
1

3
4

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SEGMENTATION
ARCHITECTURE (1)…

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SEGMENTATION
ARCHITECTURE
Protection
(2)
 With each entry in segment table associate:
 validation bit = 0  illegal segment
 read/write/execute privileges
Protection bits associated with segments; code sharing occurs at
segment level
Since segments vary in length, memory allocation is a dynamic
storage-allocation problem
A segmentation example is shown in the following diagram

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SEGMENTATION
HARDWARE

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EXAMPLE OF
SEGMENTATION

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REFERENCE
Slides adopted from the book

Abraham Silberschatz, Peter Baer

Galvin, Greg Gagne, “Operating System
Concepts”, 9/E, John Wiley & Sons.

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