EE334 INRO- MICROPROCESSOR

Intel 8088 (8086) Microprocessor

EE Department
UNIVERSITY OF TRIPOLI
Course outlines :

 Grading :
Two midterms, one final exam, lab ,.......... .As follow :
Test 1 15 % ( changeable )
Test 2 15% (changeable )
Final 40%
Practical 10%
Qizes , HW ,and Attendance . 20% (changeable )
 There are 2 tutorials (attend to one of them ) every week
starting from second week at Sunday and Wednesday .
 Attending to the lecture and tutorials most important thing of the
course , nonattendance over 25% of lectures , you will get zero
grade as final result .
 all student must switch off their Cell phone during lectures and
tutorials, or you will have to leave the class.
 do not try to enter the room after the lecturer .
 Overview
Textbook:
- Barry B. Brey, "The Intel Microprocessors: 8086/8088, 80186/80188,
80286, 80386, 80486 - Pentium and Pentium Processor - Architecture,
Programming and Interfacing," 4th Edition, Prentice Hall International Editions
- Microprocessor 8086 : Architecture, Programming and Interfacing
By Sunil Mathur
- Microprocessor By A.P.Godse, D.A.Godse 2009 1th
Main Objectives:
The course will provide knowledge to build and program
microprocessor-based systems.
 Microprocessor architecture
 8086/8088 instruction set
 assembly language programing
 Programming microprocessor-based systems
 8086/8088 hardware spesification
 8086/8088 memory interfacing
 8086/8088 I/O interfacing
 Evolution of Computers

 First generation (1939-1954) - vacuum tube

 Second generation (1954-1959) - transistor

 Third generation (1959-1971) - IC

 Fourth generation (1971-present) - microprocessor

 Evolution of Computers

 First generation (1939-1954) - vacuum tube

IBM 650, 1954

Http://history.acusd.edu/gen/recording/computer1.html
http://www.cs.virginia.edu/brochure/museum.html
http://www.columbia.edu/acis/history/650.html
 Evolution of Computers

 Second generation (1954-1959) - transistor

Manchester University Experimental Transistor Computer

Http://history.acusd.edu/gen/recording/computer1.html
http://www.computer50.org/kgill/transistor/trans.html
 Evolution of Computers

 Third generation (1959-1971) - IC

PDP-8, Digital Equipment Corporation

¾ Thanks to the use of ICs, the DEC PDP-8

is the least expensive general purpose small
computer in 1960s

Http://history.acusd.edu/gen/recording/computer1.html
http://www.piercefuller.com/collect/pdp8.html
 Evolution of Computers
 Fourth generation (1971-present) - microprocessor
¾ In 1971, Intel developed 4-bit 4004 chip for calculator
applications.

ROM/RAM buffer Timing Reset

Control logic
Instruction Program
decoder counter

ALU Reg.

I/O
Refresh
logic

System bus
http://www.intel.com

Block diagram of Intel 4004 4004 chip layout

A good review article: The History of The Microprocessor, Bell Labs Technical Journal,
Autumn, 1997
 Evolution of Intel Microprocessors
Number of transistors Minimum transistor sizes (µm)
100,000,000
7
P III 8080
Pentium 6
10,000,000 P4
1,000,000 80386 P II 5
80486
100,000 8088 4
80286
10,000 8088
3
1,000 8080
2 80386
100
Pentium
10 1 80286 P II P III P 4
0
80486
1
1974 1979 1982 1985 1989 1993 1997 1999 2000 1974 1979 1982 1985 1989 1993 1997 1999 2000

Clock frequencies (MHz) MIPS

10000 10000
P4
1000 P III
1000 P4
P II Pentium
100 P II
100
Pentium P III
80386 10 80386
80486
10 8088 80486
8080 1 8080 8088
80286 80286
1 0.1
1974 1979 1982 1985 1989 1993 1997 1999 2000 1974 1979 1982 1985 1989 1993 1997 1999 2000
 Other Commercial Microprocessors
 PowerPC (IBM, Motorola)
 Athlon, Dulon, Hammer (AMD)
 Crusoe (Transmeta)
 SPARC, UltraSPARC (Sun Microsystems)

 TI’s TMS DSP chips (Texas Instruments)

 StarCore (Motorola, Agere)

 ARM cores (Advanced RISC Machines)

 MIPS cores (MIPS Technologies)

 
Microcomputers, Microcontrollers, and Microprocessors

Microcomputer
Relatively small and inexpensive computer that is
contained on one or a few chips
Microcontroller
A single-chip microcomputer
Embedded systems use microcontrollers or microcomputers.
Microprocessor
The processor and control unit
part of the single-chip
computer(=microcontroller) is
called microprocessor.
 Microcontrollers
¾ A microcontroller is a simple
computer implemented in a
single VLSI chip.
RAM ROM
¾ In general, microcontrollers OSC.

are cheap and have low

performance CPU
I/O port

¾ Microcontrollers are widely Timer USART

used in industrial control,
automobile and home Interrupt A/D, D/A
applications

Block diagram of a microcontroller

 What are microprocessor-based systems?

 Microprocessor-based systems are electrical systems consisting

of microprocessors, memories, I/O units, and other peripherals.
¾ Microprocessors are the brains of the systems
¾ Microprocessors access memories and other units through buses
¾ The operations of microprocessors are controlled by instructions
stored in memories

Microprocessor
Control Bus
unit

Datapath
ALU
Output Input
Reg. Memory
units units
Basic Architecture
• There are many other architectures in use. They will be
discussed in a computer architecture course.
• Here, we will cover two major architecture of microcomputers.
– Von Neumann architecture and Harvard architecture
– The main difference is the memory structure
• Von Neumann architecture
– Single memory contains both the program code and the data.
• Harvard Architecture
– Two separate memories. One contains only data while the
other is containing only program code .
Microprocessor-Based Systems
 Computers
¾ System performance is normally the most important design concern
 PC block diagram • ROM (Read Only Memory)
(start-up program)
• RAM (Random Access Memory)
• Crystal P + • Bus • DRAM (Dynamic RAM) - high
oscillator associated controller
capacity, refresh needed
• Timing circuitry logic • Bus drivers • SRAM (Static RAM) - low
(counters dividing to circuitry: • power, fast, easy to interface
Coprocessor
lower frequencies)
Timing CPU Memory

System bus (data, address & control signals)

Parallel I/O Serial I/O Interrupt circuitry

Many wires, fast. Simple (only two wires At external unexpected events,
• Printer (high resolution) + ground) but slow. P has to interrupt the main
• External memory • Printer (low program execution, service the
• Floppy Disk resolution) interrupt request (obviously a
• Hard Disk • Modem short subroutine) and retake the
• Compact Disk • Operator’s console
main program from the point
• Other high speed devices • Mainframe
• Personal computer where it was interrupt.
 Speaker PC block diagram

Processor Coprocessor
Timer logic (8086 trough (8087 trough
(8253) Pentium 80387 System 640KB
ROM DRAM

System bus (data, address & control signals)

Keyboard logic DMA Controller Expansion Interrupt

(8253) (8237) logic logic (8259)

Video card
Disk controller
Serial port
Keyboard ...
Extension slots
 Objectives

 Hardware architecture of microprocessor-based systems

¾ Microprocessor architecture
¾ Memory organization
¾ I/O units of microprocessor-based systems
¾ How to put them together

 Programming of microprocessor-based systems

¾ Intel 80x86 instruction set
¾ Assembly language programming
¾ Microprocessor Interrupt services
 LECTURE 2
Memory concept &
Architecture of 8086 / 8088
Architecture of 8086
The architecture of 8086 includes
Arithmetic Logic Unit (ALU)
Flags
registers
Instruction queue register
Segment registers
 Pipelining / unPipelining concept
 In the 8085 microprocessor, the CPU could either fetch or execute at a given time.
CPU had to fetch an instruction from the memory, then execute it, then fetch again
and execute it and so on..
 Pipelining is the simplest form to allow the CPU to fetch and execute at the same
time. Note that the fetch and execute times can be different.

Non-Pipeline (8085 µp)

Pipeline (8086/8088 µp)

 Intel implemented the concept of pipelining by

splitting the internal structure of 8088/86 into two sections.
* the execution unit (EU)
* the bus interface unit (BIU)
EU & BIU
 The 8086/8088 µp has been divided into two
functional units Bus Interface Unit (BIU) and Execution Unit
(EU)
 The BIU has to interact with memory and input and
output devices in fetching the instructions and data
required by the EU
 EU is responsible for executing the instructions of the
programs and to carry out the required processing
 what is the major reason for µp separation to BIU
and EU ?
8086/8088 Architecture Diagram
 Execution Unit
The Execution Unit (EU) has

Control unit General registers

Instruction decoder Flag register
Arithmetic and Logical Unit Pointers
(ALU) Index registers
Control unit : responsible for the management of
all other units of the processor
ALU : performs various arithmetic and logical
operations over the data
Instruction decoder : translates the instructions
fetched from the memory into a series of actions
that are carried out by the EU
Execution Unit - Registers
General purpose registers : (AX , BX,CX,DX)
used for temporary storage and manipulation of
data and
instructions.
Accumulator register: (AX)
* consists of two 8-bit registers AL and AH, which can be
combined
together and used as a 16-bit register AX
Base* Accumulator
register : BXcan be used for I/O operations and string
*consists of two 8-bit registers BL and BH, which can be
manipulation
plus arithmetic operation>
combined
together and used as a 16-bit register BX .
* Usually contains a data pointer used for based, based
indexed or register
indirect addressing .
Count register: CX
* consists of two 8-bit registers CL and CH, which can be
combined
 Execution Unit - Registers
Data register : DX
* It consists of two 8-bit registers DL and DH, which can
be combined
together and used as a 16-bit register DX.
* Data register can be used as a port number in I/O
operations.
* In integer 32-bit multiply and divide instruction the DX register
contains
high-order word of the initial or resulting number.
 Execution Unit – Pointer/Index
 Pointer and index register : ( SP , BP , DI , and SI )
 Stack Pointer (SP) : * a 16-bit register.pointing to top of the stack.
 Base Pointer (BP): * a 16-bit register. pointing to data in stack segment.
 Source Index (SI) : * a 16-bit register. SI is used for indexed, based
indexed and register indirect addressing, as well as a
source data addresses in string manipulation instructions.
 Destination Index (DI): * a 16-bit register. DI is used for indexed, based
indexed and register indirect addressing, as well as a
destination data addresses in string manipulation
instructions.
Execution Unit – ALU/FLAGS
 A L U : (Arithmetic Logic Unit )
* is the calculator part of the execution unit. It consists of
electronic circuitry that performs arithmetic operations or
logical operations on the binary represented electrical signals.
result

16

operation ALU

16 16
a b
 Execution Unit - Flags
F l a g r e g i s t e r :
* Six flags are status flags- CF, AF, OF, SF, PF and ZF.
* Three flags are control flags -DF,IF, and TF.
 Carry Flag (CF):
* Set by arithmetic instructions that generate a carry or borrow. Also can
be set, and cleared with the STC, CLC instructions respectively.
 Auxiliary carry Flag(AF):
* Set if there was a carry from or borrow to bits 0-3 in the AL register.
 Overflow Flag (OF):
* Set when the result of signed arithmetic operation is too wide to fit into
destination.
 Sign Flag (SF):
* Set if the most significant bit of the result is set, i.e the result is negative.
 Parity Flag (PF) :
* Set if parity (the number of "1" bits) in the Least Significant Byte (LSB) of
the result is even.
 Zero Flag (ZF) - set if the result is zero.
 Execution Unit - Flags
Interrupt-enable flag (IF) :
* Enables or disables external interrupts.
 Trap flag (TF) :
* Puts the processor into a single-step mode for program debugging.
* Determines whether or not the CPU is halted after each instruction.
* Allows programmers to do tracing.
 Direction (DF):
* Tthis flag is used by some instructions
to process data chains (ex: MOVS) ,
when this flag is set to :
0 - the processing is done forward,
1 - the processing is done backward.
Execution Unit - Flags
Bus Interface Unit ( BIU )
· 8086/8088 Memory interface concept
· Instruction pointer
· Instruction queue register
· Segment registers
2- Instruction pointer
 IP Instruction Pointer :
contains the offset of the next instruction to be
executed.
3- Instruction Queue register
The instruction’s size vary from 1 to 6 bytes
The BIU feeds the instruction stream to the execution
unit through a 6 byte instruction queue register
 The BIU store the pre-fetched instruction in a first-in-first
out register (Queue register )
EU simply reads the next instruction byte(s) form the
queue register in BIU .
 - Memory (concept) :
 Need to distinguish between: N
* The address of a memory cell and
the content of a memory cell. 0000000000000001
 Memory width (W): 1 bit
0
* How many bits is each memory cell, typically
one byte (=8 bits) 1
 Address width (N): 2
* How many bits used to represent each address,
determines the maximum memory size = 2N
address space
...
* If address width is N-bits, then address space is
2N (0,1,...,2N-1)
 Memory sizes:
2N-1
* Kilobyte (KB)= 210 = 1,024 bytes 1 thousand
* Megabyte(MB)= 220 =1,048,576 bytes million
W
 - Memory interface (concept) :
* 8086 /8088 can access up to 1MByte of memory ( 20 bit address line in-need ).
* 8086/8088 registers are only 16-bits wide, and two registers are needed to produce
a 20-bit memory address.
• A segment register specifies the upper 16 bits of the address.
• Another register specifies the lower 16 bits of the address.
* These registers are then added together in
a special way. (discussed later )
4- Segment Registers
* Code Segment (CS) register is a 16-bit register
containing address of 64 KB segment that contain
processor instructions
* Stack Segment (SS) register is a 16-bit register
containing address of 64KB segment that contain
program stack
* Data Segment (DS) register is a 16-bit register
containing address of 64KB segment that contain
program data.
* Extra Segment (ES) register is a 16-bit register
containing address of 64KB segment, usually
contain program data.
4-Segment Registers FFFF

…..
F

code

data

address space
…
stack

...
extra

……..
0000
0
4-Segment Registers
 The memory of 8086 is divided into 4 segments namely
 Code segment (program memory) Stack memory (stack segment)
 Data segment (data memory)  Extra memory (extra segment)

Different Areas in Memory

 CS (code) segment holds code (programs and procedures) used
by the µp
 DS (data) contains most data used by a program.
 ES (extra) an additional data segment used by some
instructions to hold destination data.
 SS (stack) defines the area of memory used for the stack
A memory system showing the placement of four memory segments.
4-Segment Registers
 Used to generate memory addresses when its combined with
other registers in the µp.
 A segment register functions differently in real mode than in
protected mode ( addressing scheme).
 Following is a list of each segment register, along with its
function in the system.
 The scheme used in the 8086/808 is called
segmentation
 Every address has two parts, a SEGMENT and an OFFSET
(Segmnet:Offset )
 The segment indicates the starting of a 64 kilobyte portion
of memory, in multiples of 16
 The offset indicates the position within the 64k portion
 Absolute address = (segment * 16) + offset
 REAL MODE MEMORY ADDRESSING
 allows addressing of only 1M byte of memory space .
* The first 1M byte of memory is called the real memory, conventional memory,
or DOS memory system

Segments and Offsets

 All real mode memory addresses must consist of a segment address
plus an offset address.
* Segment address :defines the beginning address of any 64K-byte memory
segment.
* Offset address : selects any location within the 64K byte memory segment.
REAL MODE MEMORY ADDRESSING
 How can a 16-bit microprocessor generate 20-bit memory addresses?

Left shift 4 bits

FFFFF

16-bit register 0000 Addr1 + 0FFFF

Segment
+ 16-bit register Offset
Addr1
Offset
(64K)

20-bit memory address Segment

address
00000

Intel 80x86 memory address generation 1M memory space

REAL MODE MEMORY ADDRESSING
 Once the beginning address is known, the ending address is
found by adding FFFFH.
* Because a real mode segment of memory is64K in length
 The offset address is always added to the segment starting
address to locate the data.
 Segment and offset address is sometimes written as 1000:2000
( Logical address) .
• a segment address of 1000H; an offset of 2000H
physical address = segment address*16 + Offset address.
• A single 20-bit address can be specified in multiple
ways! . For instance, 0000:0040 is the same as 004:0000
(in hexadecimal notation).
Default Segment and Offset Registers
REAL MODE MEMORY ADDRESSING
REAL MODE MEMORY ADDRESSING
 Examples:
* Direct addressing: MOV AL, [0300H]

DS 1 2 3 4 0 (assume DS=1234H)
0 3 0 0
Physical address 1 2 6 4 0

* Register indirect addressing: MOV AL, [SI]

DS 1 2 3 4 0 (assume DS=1234H)
0 3 1 0 (assume SI=0310H)
Physical address 1 2 6 5 0

3-48
* Addressing mode refer to lecture 3
 Instruction Execution cycle
Fetch cycle :
* Place the instructions in the queue.
* IP is updated as follows:
IP = IP + Length of the fetched instruction
Decode cycle:
* Perform address translation
* Fetch Operands from memory.
Execute cycle:
* Perform the required calculation.
* Sore the result in register /memory.
* Set the status flags affected by last operation.