I/O MODULES

LECTURE 7
I/O INTERFACE
■ An interface is a shared boundary between two separate components
of the computer system which can be used to attach two or more
components to the system for communication purposes.
Definition:
An I/O interface is a hardware circuit used between the CPU and I/O
devices (peripherals) to supervise and synchronize all input and output
transfers.
– I/O interface provides a method for transferring information
between internal storage to external I/O devices.
– Peripherals connected to a computer need special communication
links for interfacing them with the CPU
I/O BUS AND INTERFACE
MODULES
■ In addition to the processor and a set of memory modules, the third
key of the computer system is a set of I/O modules.
■ Each module interfaces to the system bus or central switch to control
one or more peripheral devices.
■ An I/O modules is the entity within a computer responsible for the
control of one or more external devices and for the exchange of data
between those devices and main memory and / or CPU registers.
Thus, the I/O module must have an interface to the computer (to the
CPU and main memory) and an interface internal to the computer (to
the external device).
 Input and output modules (i/o
■ modules)
I/O modules stands for input/output modules which is a device that acts as
the connective bridge between a computer system at one end and an I/O or
peripheral device of some kind at the other such as printers, webcams, or
scanner.
■ A device connected to an I/O module of a computer is called a peripheral
device
Block Diagram of an I/O
Module
Importance of an I\O module
■ Operation method: variety of I/O devices are available with different
operation method. It was not possible to develop operation logic of each I/O
devices in the CPU itself.
■ Slow speed: The I/O devices are much slower than that of the CPU. Hence
it is not possible to match to match high speed of CPU with speed of I/O
devices.
■ Data formats: As I/O devices are made with different operation method
some of them uses different data formats. It was impractical to integrate
each data format in the CPU.
■ Storage and error detection: I/O module should have facilities like
buffer (storage area) and error detection mechanism. since there are speed
differences between CPU and I/O devices,
I/O module functions

■ Processor communication, that is to say exchange between the

processor and I/O devices, command decoding where modules accept
commands coming from the processor and address recognition.
■ Device communication, this is in the form of status reporting where
the device reports its status to the processor.
■ Control and timing, the I/O module must be to coordinate the flow of
data between the internal resources and external devices
■ Data buffering, this is done to match the speed of data transfer
between processor and memory and external devices.
■ Error detection, the I/O module must also be able to detect errors and
report them to the processor. The best way of detecting errors is by
using parity bits
Types of input-output commands
■ Control command. Issued to activate the peripheral and to inform it
what to do.
■ Status command. To test various status conditions in the interface
and the peripheral.
■ Data output command. This command causes the interfaces to
respond by transferring data from bus into one of its registers.
■ Data input command. This command transfers information (data)
from the peripheral to the interfacing circuit
techniques of i/o modules
Three techniques are possible for I/O operations
■ Programmed i/o
■ Interrupt driven i/o
■ Direct memory access
Programmed i/o
■ With programmed I/O, data are exchanged between the processor and
the I/O module.
■ The processor executes a program that gives it direct control of the
I/O operation, including sensing device status, sending a read or write
command, and transferring the data.
■ When the processor issues a command to the I/O module, it must wait
until the I/O operation is complete. If the processor is faster than the
I/O module, this is wasteful of processor time.
 Characteristics of
programmed I/O technique
■ The I/O operations are completely controlled by the CPU.
■ It is used in real time and embedded systems.
■ It is also used in CPUs which have a single input and a single output
instruction.
■ This techniques has a disadvantage that the CPU spends most of its
time waiting for the device to become ready.
In summary
■ CPU requests I/O operation
■ I/O module performs operation
■ I/O module sets status bits
■ CPU checks status bits periodically
■ CPU may wait or come back later
Programmed I/O is useful in cases whereby one character at a time is to
be transferred, for example, keyboard and character mode printers.
Although simple, programmed I/O is slow.
INTERRUPT-DRIVEN I/O
■ The problem with programmed I/O is that the processor has to wait a
long time for the I/O module of concern to be ready for either
reception or transmission of data.
■ The processor, while waiting, must repeatedly interrogate the status
of the I/O module. As a result, the level of the performance of the
entire system is severely degraded. An alternative is for the processor
to issue an I/O command to a module and then go on to do some
other useful work.
■ The I/O module will then interrupt the processor to request service
when it is ready to exchange data with the processor.
■ The processor then executes the data transfer, as before, and then
resumes its former processing
.Let us consider how this works, first from the point of
view of the I/O module.
■ For input, the I/O module receives a READ command from the
processor.
■ The I/O module then proceeds to read data in from an associated
peripheral.
■ Once the data are in the module’s data register, the module signals
an interrupt to the processor over a control line.
■ The module then waits until its data are requested by the processor.
■ When the request is made, the module places its data on the data bus
and is then ready for another I/O operation.
From the processor’s point of view, the action for input
is as follows.
■ The processor issues a READ command. It then goes off and does
something else (e.g., the processor may be working on several different
programs at the same time)
■ .At the end of each instruction cycle, the processor checks for interrupts .
When the interrupt from the I/O module occurs, the processor saves the
context (e.g., program counter and processor registers) of the current
program and processes the interrupt.
■ In this case, the processor reads the word of data from the I/O module
and stores it in memory.
■ It then restores the context of the program it was working on (or some
other program) and resumes execution.

Interrupt driven I/O is more efficient than programmed I/O because it

eliminates needless waiting. However, interrupt I/O still consumes a lot of
processor time, because every word of data that goes from memory to I/O
Drawbacks of Programmed I/O and
Interrupt Initiated I/O

■ The I/O transfer rate is limited by the speed with which the processor
can test and service a device.
■ The processor is tied up in managing an I/O transfer; a number of
instructions must be executed for each I/O transfer.
DIRECT MEMORY ACCESS
■ DMA uses special I/O CPU that take control of an I/O operation to move
large block of data. This technique adds additional module on system bus
■ DMA involves an additional module on the system bus. The DMA module
is capable of mimicking the processor and, indeed, of taking over control
of the system from the processor. It needs to do this to transfer data to
and from memory over the system bus. For this purpose, the DMA
module must use the bus only when the processor does not need it, or it
must force the processor to suspend operation temporarily.
■ The main idea of direct memory access (DMA) is to enable peripheral
devices to cut out the role of the CPU in data transfer. It allows peripheral
devices to transfer data directly from and to memory without the
intervention of the CPU. Having peripheral devices access memory
directly would allow the CPU to do other work, which would lead to
improved performance, especially in the cases of large transfers
DIRECT MEMORY ACCESS cont’d
■ In this, the interface transfers data to and from the memory through
memory bus. A DMA controller manages to transfer data between
peripherals and memory unit without the help of the processor.The
DMA controller is a piece of hardware that controls one or more
peripheral devices.
■ Many hardware systems use DMA such as disk drive controllers,
graphic cards, network cards and sound cards etc. It is also used for
intra chip data transfer in multi-core processors. In DMA, CPU has line
connecting to I/O module. Line is used to exchange control signal,
status signal and data between the I/O module and the I/O devices
When CPU needs to read or write data, it issues command to the
DMA module, by sending to the DMA module following information:
■ Whether a read and write is requested, using read, or write control line
between the CPU and DMA module.
■ The address of I/O module involved, communicated on the data line.
■ The starting location is in memory to read from or write to,
communicated on the lines and stored by the DMA module in its address
registers.
■ The number of words to be read or written, again communicated via the
data lines and stored in the data count register. The CPU then continues
with other work.
The processor then continues with other work. It has delegated this I/O
operation to the DMA module. The DMA module transfers the entire block of
data, one word at a time, directly to or from memory, without going through
the processor.
In summary
■ CPU tells DMA controller:-
– Read/Write
– Device address
– Starting address of memory block for data
– Amount of data to be transferred
■ CPU carries on with other work
■ DMA controller deals with transfer
■ DMA controller sends interrupt when finished
DMA Data Transfer Modes
There are three typed of data transfer modes and they are as follows:
■ Burst/Block Transfer Mode – In burst mode, the DMA controller keeps
control of the bus until all the data has been transferred to (from) memory
from (to) the peripheral device. This mode of transfer is needed for fast
devices where data transfer cannot be stopped until the entire transfer is
done. While data is transferring CPU does some internal operation that does
not require system bus interaction.
■ Cycle Stealing – In this case instead of transferring entire block of data, it
transfers only word by word.The DMA controller relinquishes the bus after
each transfer of one data word. This minimizes the amount of time that the
DMA controller keeps the CPU from controlling the bus, but it requires that
the bus request/acknowledge sequence be performed for every single
transfer. Cycle is stole only when CPU is using some work that does not
require system bus.
■ Interleaved – Interleaved is same as block transfer mode, only difference is
it takes control of system bus, when CPU is not using it.
 DMA Configuration
■ There are two types of configuration and they are as follows:
■ Single bus configuration: In first type, it allows DMA, I/O and all
types of modules to share the same system bus
DMA Configuration

■ Multiple bus configuration: In the second type, direct path should

be established between the DMA and I/O module without any
intervention of the system bus. Devices are connected using more
than one bus (e.g., separate I/O bus, memory bus, etc.).
Figure below shows diagram
of DMA
I/O MODULE STRUCTURE
■ I/O module is intermediate between I/O devices and CPU. The module
connects to the rest of the computer through a set of signal lines
(e.g., system bus lines). Data transferred to and from the module are
buffered in one or more data registers. There may also be one or more
status registers that provide current status information. A status
register may also function as a control register, to accept detailed
control information from the processor. The logic within the module
interacts with the processor via a set of control lines. The processor
uses the control lines to issue commands to the I/O module.
■ System buses are connected to the one end of I/O module and other
end is connected to the number of I/O devices. It used to exchange
information between I/O devices and CPU. I/O devices cannot be
directly connected to the system buses; they are connected to the
system buses through module.
Interrupt Processing
Let us consider the role of the processor in interrupt-driven I/O
in more detail.
The occurrence of an interrupt triggers a number of events, both in the
processor hardware and in software. Figure 7.6 shows a typical sequence.
When an I/O device completes an I/O operation, the following sequence
of hardware events occurs:
1.The device issues an interrupt signal to the processor.
2. The processor finishes execution of the current instruction before
responding to the interrupt
3. The processor tests for an interrupt, determines that there is one, and
sends an acknowledgment signal to the device that issued the interrupt.
The acknowledgment allows the device to remove its interrupt signal.
4. The processor now needs to prepare to transfer control to the interrupt
routine. To begin, it needs to save information needed to resume the
current program at the point of interrupt. The minimum information
required is (a) the status of the processor, which is contained in a
register called the program status word (PSW), and (b) the location of the
next instruction to be executed, which is contained in the program
counter. These can be pushed onto the system control stack.2
5. The processor now loads the program counter with the entry location
of the interrupt-handling program that will respond to this interrupt.
6. At this point, the program counter and PSW relating to the interrupted
program have been saved on the system stack. However, there is other
information that is considered part of the “state” of the executing
program..
7. The interrupt handler next processes the interrupt. This includes an
examination of status information relating to the I/O operation or other
event that caused an interrupt. It may also involve sending additional
commands or acknowledgments to the I/O device
 8. When interrupt processing is complete, the saved register values are
retrieved from the stack and restored to the registers.
9. The final act is to restore the PSW and program counter values from
the stack. As a result, the next instruction to be executed will be from the
previously interrupted program.
Note that it is important to save all the state information about the
interrupted program for later resumption. This is because the interrupt is
not a routine called from the program. Rather, the interrupt can occur at
any time and therefore at any point in the execution of a user program.
Its occurrence is unpredictable.
THE END