ATPG - test pattern generation process

1. Target faults
2. Generate test cube: 1-5%
3. Random fill: 99-95%

4. Stimuli on ATE
5. Response on ATE
Scan/ATPG - non-embedded solution
ATE stimuli ATE reference

The same width

The same frequency
Mirror images: ATE and scan
ATPG - the bandwidth problem

Deterministic
+ High fault coverage
+ Arbitrary fault models

+ Minimal number of
patterns Non-Embedded
+ Simplicity
- Limited number of
scan chains
- Limited bandwidth
 Logic BIST
100%
100%

P M
R I
P S
G R

Control

Fault coverage
Logic BIST
BIST-ready core requirement
Logic BIST + test points
 Random pattern testable
 X-free responses
Logic BIST

 Generators
E
q • Pseudorandom - PRPG
u
P M
R
a
I
• Biased
l
P S
G
i
R
• Smart
z
e • Deterministic
r

Control

 Test data eliminated completely

 Deigned for board and system test
Logic BIST

Pseudorandom
+ No stored patterns
- Lower coverage
- More patterns
- BIST-ready design
Embedded
- More complex
+ Unlimited number
of scan chains
+ Short scan load time
EDT™ - Embedded Deterministic Test
 Standard scan
D
 On-chip continuous flow D
E
E
CC
C
decompressor C
O
O
O
O
M
M
M
M
 On-chip continuous flow P
P
P
A
P
A
R
R
selective compactor E
E
S
S
CC
TT
O
O
 Highly compressed S
S
O
RR
O
deterministic patterns R
R

Compressed Compacted
Compressed
Stimuli
Stimuli
ATE Compacted
Responses
Responses
Embedded and deterministic test

Deterministic
+ High fault coverage
+ Arbitrary fault models

+ Minimal number of
patterns
Embedded
-+ More complex
Simple
+ Unlimited number
of scan chains
+ Short scan load time
ATPG cycles, coverage, and volume
100%

e
r ag
ove
80% c e
PG l um
AT vo
TPG
A
60%

40%

20%

0%
Cycles
LBIST cycles, coverage, and volume
100%
e
r ag ATPG top-up coverage
e
cov
80% I ST
B

60%

40%

me
volu
p
20% p-u
to
TPG
A
0%
Cycles
EDT 10X cycles, volume, and energy
100%
e
r ag ATPG top-up coverage
e e
cov r ag
I ST ove
80% B c e
PG l um
AT vo
TPG
A
60%

40%

me
volu
p
20% p-u
to
TPG
A
0%
Cycles

EDT
EDT 10X
10X LBIST
LBIST LTPG
LTPG ATPG
ATPG
Radar View of DFT Technologies
Reference
Quality

Volume Area

Core Test TTM

Energy Learning

Test Time Diagnosis

ATPG
Quality ATPG
EDT
Volume Area LBIST
LTPG

Core Test TTM

Energy Learning

Test Time Diagnosis

ATPG, Logic BIST
Quality ATPG
EDT
Volume Area LBIST
LTPG

Core Test TTM

Energy Learning

Test Time Diagnosis

… Logic BIST & ATPG top up patterns
Quality ATPG
EDT
Volume Area LBIST
LTPG

Core Test TTM

Energy Learning

Test Time Diagnosis

EDT
Quality ATPG
EDT
Volume Area LBIST
LTPG

Core Test TTM

4
6
8
10
Energy Learning

Test Time Diagnosis

Logic BIST summary
 Logic BIST is ideally suited for applications where
stored patterns are prohibitive, i.e. system test
 Test coverage objectives are achieved by
pseudorandom patterns and test points
 Unknown states have to be eliminated to allow
signature based compaction
 For manufacturing test ATPG top up patterns are
required to achieve the desirable test quality
 For very long test experiments some un-modeled
defects can be detected
EDT summary
 EDT is designed for optimized manufacturing test
 Based on standard scan
• No test point are required
• Handles unknown states
 Supports effectively variety of fault models,
including path delay faults
 Uses tester to execute the test
Deterministic forms of embedded test
 Designed for optimized manufacturing test
 Tester controls test application
 Very similar flow to scan/ATPG
• Based on standard scan
• Supports the same fault models as ATPG
• No test points necessary
• No bounding of X states necessary (in EDT)
 On-chip hardware facilitates the improved efficiency
• Compression of volume of scan test data
• Reduction of scan test time
Acknowledgements
Alfred Crouch, Motorola
Graham Hetherington, Texas Instruments
Mark Croft, Mentor Graphics
Geir Eide, Teseda
Rudy Garcia, NP Test
Abu Hassan, Mentor Graphics
Mark Kassab, Mentor Graphics
Nilanjan Mukherjee, Mentor Graphics
Jun Qian, CISCO
Nagesh Tamarapalli, Mentor Graphics
Robert Thompson, Magma DA
Janice Lawson Richards , Mentor Graphics
References and sources
 Conference proceedings and tutorial material
• International Test Conference
• Design Automation Conference
• Design and Test in Europe Conference
• VLSI Test Symposium
 Workshops
• Testing Embedded Core-based Systems
• Memory Technology, Design and Testing
• DFT and BIST Workshops
• Test Synthesis Workshop
References and sources
 Magazines and journals
• IEEE Design and Test of Computers
• IBM Journal of Research and Development
• ATT Technical Journal
• IEEE Transactions on CAD of IC&S
• IEEE Transactions on Computers
• Journal of Electronic Testing (JETTA)
 Books
• Abramovici et al., “Digital System Testing and Testable
Design”, Computer Science Press, 1990
• Bardel et al., “Built-In Test for VLSI”, Wiley, 1987
References and sources
 Books
• Van der Goor, “Testing Semiconductor Memories:
Theory and Practice”, John Wiley and Sons, 1991
• Alfred Crouch, “Design-For-Test for Digital ICs and
Embedded Core Systems”, Prentice Hall, 1999
• Janusz Rajski and Jerzy Tyszer, “Arithmetic Built-In
Self Test for Embedded Systems”, Prentice Hall, 1998
 Commercial EDA reference manuals and web pages
 ASIC vendors reference manuals and web pages
 Patent descriptions and US Patent and Trademark
Office web site