OPERATING SYSTEM

UNIT III

MEMORY MANAGEMENT
 BACKGROUND

 Memory consists of large array of words or bytes, each with its own address.

 The CPU fetch fetches instructions from memory according to the value of the
program counter.
 Program must be brought (from disk) into memory and placed within a process
for it to be run
 Main memory and registers are only storage CPU can access directly

 Register access in one CPU clock (or less)

 Main memory can take many cycles

 Cache sits between main memory and CPU registers

 Protection of memory required to ensure correct operation 2

 BASE AND LIMIT REGISTERS

 A pair of base and limit registers define the logical address space.

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 ADDRESS BINDING

 Address binding of instructions and data to memory addresses can happen

at three different stages
 Compile time: If memory location known a priori, absolute code can be
generated; must recompile code if starting location changes
 Load time: Must generate relocatable code if memory location is not
known at compile time
 Execution time: Binding delayed until run time if the process can be
moved during its execution from one memory segment to another. Need
hardware support for address maps (e.g., base and limit registers)
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MULTISTEP PROCESSING OF A USER
PROGRAM

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 LOGICAL VS. PHYSICAL ADDRESS SPACE

 The concept of a logical address space that is bound to a separate physical

address space is central to proper memory management
 Logical address - generated by the CPU; also referred to as virtual
address.
 Physical address - the one loaded into the memory address register of
the memory
 Logical and physical addresses are the same in compile-time and load-
time address-binding schemes; logical (virtual) and physical addresses
differ in execution-time address-binding scheme
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 LOGICAL VS. PHYSICAL ADDRESS SPACE

 Logical address space: The set of all logical addresses generated by a

program is logical address space.

 Physical address space: The set of all physical addresses corresponding

to these logical addresses is a physical address space.

 The run time mapping from virtual to physical addresses is done by a

hardware device called the memory management unit (MMU).

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DYNAMIC RELOCATION USING A
RELOCATION REGISTER

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 DYNAMIC LOADING

 Routine is not loaded until it is called.

 Better memory-space utilization; unused routine is never loaded.

 Useful when large amounts of code are needed to handle infrequently

occurring cases.
 No special support from the operating system is required implemented
through program design.

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 DYNAMIC LINKING

 Linking postponed until execution time.

 Small piece of code, stub, used to locate the appropriate memory-resident

library routine.
 Stub replaces itself with the address of the routine, and executes the
routine.
 Operating system needed to check if routine is in processes’ memory
address.
 Dynamic linking is particularly useful for libraries.

 System also known as shared libraries.

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 OVERLAYS

 Keep in memory only those instructions and data that are needed at any
given time.
 Needed when process is larger than amount of memory allocated to it.

 Implemented by user, no special support needed from operating system,

programming design of overlay structure is complex.

Pass 1 70 KB

Pass 2 80 KB

Symbol table 20 KB

Common routines 30 KB
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 OVERLAYS
 To load everything we would require 200 KB of memory. If only 150 KB
is available, we cannot run our process.
 We define two overlay:

Overlay A Overlay B

Pass 1 Pass 2

Symbol table Symbol table

Common routines Common routines

 We add an overlay driver(10KB) and start with overlay A.

 Finish pass 1, jump to overlay driver which reads overlay B into memory.
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 Overwriting overlay A then transfer control to pass 2.
OVERLAYS

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 SWAPPING
 A process can be swapped temporarily out of memory to a backing store, and then
brought back into memory for continued execution.

 For example: Round Robin Scheduling with quantum time.

 Backing store – fast disk large enough to accommodate copies of all memory
images for all users; must provide direct access to these memory images.

 Roll out, roll in – swapping variant used for priority-based scheduling algorithms;
lower-priority process is swapped out so higher-priority process can be loaded and
executed.

 Modified versions of swapping are found on many systems (i.e., UNIX, Linux,
and Windows).

 System maintains a ready queue of ready-to-run processes which have memory 14

images on disk.
SCHEMATIC VIEW OF SWAPPING

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 SWAPPING

 Major part of swap time is transfer time; total transfer time is directly
proportional to the amount of memory swapped.
 The context-switch time in such a swapping system is fairly high.

 Let us assume that the user process is of size 1MB and the backing store is a
standard hard disk with transfer rate of 5MB per second.

= 1000KB / 5000KB per second

= 1/5 second (0.2*1000)

= 200 milliseconds
 Average latency of 8 milliseconds, then swap time takes 208 milliseconds.
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 For swap our and swap in the total swap time is 416 milliseconds.
 SWAPPING

 If we have a computer system with 128 MB of main memory and resident

operating system with 5 MB, the maximum size of the user process is
123MB.
 1 MB user process need content switch time = 0.2 seconds

 123 MB user process need content switch time = 123*0.2

= 24.6 seconds

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 CONTIGUOUS MEMORY ALLOCATION

 Main memory usually into two partitions:

 Resident operating system, usually held in low memory or high memory

with interrupt vector.
 User processes then held in high memory.

 Memory Protection:

 Two major issues of memory protection are listed below,

1. Protecting the operating systems from user processes.

2. Protecting user processes from one another.

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 CONTIGUOUS MEMORY ALLOCATION

 Single-partition allocation:

 Relocation registers used to protect user processes from each other, and

from changing operating-system code and data.

 Base register contains value of smallest physical address.

 Limit register contains range of logical addresses – each logical

address must be less than the limit register.

 MMU maps logical address dynamically.

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 HARDWARE SUPPORT FOR
RELOCATION AND LIMIT REGISTERS

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 CONTIGUOUS MEMORY ALLOCATION

 Memory Allocation:

 Multiple-partition allocation:

Hole – block of available memory; holes of various size are

scattered throughout memory
When a process arrives, it is allocated memory from a hole large
enough to accommodate it
Operating system maintains information about:
a) allocated partitions

b) free partitions (hole)

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 CONTIGUOUS MEMORY ALLOCATION

OS OS OS OS

process 5 process 5 process 5 process 5

process 9 process 9

process 8 process
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process 2 process 2 process 2 process 2

Dynamic Storage-Allocation Problem:

First-fit: Allocate the first hole that is big enough.

Best-fit: Allocate the smallest hole that is big enough; must search
entire list, unless ordered by size. Produces the smallest leftover hole.
Worst-fit: Allocate the largest hole; must also search entire list.
Produces the largest leftover hole.
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First-fit and best-fit better than worst-fit in terms of speed and
storage utilization
 FRAGMENTATION

 Memory fragmentation is divided into two types:

1. Internal fragmentation - if the memory allocated to the process is larger

than its request, the portion of the memory will be wasted.

2. External fragmentation - when enough total memory is available to

satisfy a request, but it is not contiguous. This situation is know as external
fragmentation.
 Resolved by compaction.
 Compaction is the process of combining all free memory in one large block.
 Compaction is possible only if relocation is dynamic and is done at the
execution time. 23
 NON CONTIGUOUS MEMORY ALLOCATION
PAGING

 Logical address space of a process can be noncontiguous; process is allocated physical

memory whenever the latter is available

 Divide physical memory into fixed-sized blocks called frames. (size is power of 2,

between 512 bytes and 8,192 bytes)

 Divide logical memory into blocks of same size called pages.

 Keep track of all free frames.

 To run a program of size n pages, need to find n free frames and load program.

 Set up a page table to translate logical to physical addresses.

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 Internal fragmentation
 PAGING - BASIC METHOD
 Address generated by CPU is divided into:

 Page number (p) – used as an index into a page table which contains
base address of each page in physical memory

 Page offset (d) – combined with base address to define the physical
memory address that is sent to the memory unit

page number page offset

p d
m-n n
 For given logical address space 2m and page size 2n
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PAGING HARDWARE

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PAGING MODEL OF LOGICAL AND PHYSICAL
MEMORY

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PAGING EXAMPLE

Page 0: 5*4 =
20
Page 1: 6*4 =
24
Page 2: 1*4 =
4
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Page 3: 2*4 =
8
 FREE FRAMES

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Before allocation After allocation
 HARDWARE SUPPORT
IMPLEMENTATION OF PAGE TABLE

 Page table is kept in main memory.

 Page-table base register (PTBR) points to the page table

 Page-table length register (PRLR) indicates size of the page table

 In this scheme every data/instruction access requires two memory accesses. One
for the page table and one for the data/instruction.
 The memory access problem can be solved by the use of a special fast-lookup
hardware cache called associative memory or translation look-aside buffers
(TLBs)
 Some TLBs store address-space identifiers (ASIDs) in each TLB entry –
uniquely identifies each process to provide address-space protection for that
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process.
 TRANSLATION LOOK-ASIDE BUFFERS
(TLBS)
 Each entry in the TLB consists of two parts:

 Key
 Value
 Compared with all key simultaneously. Item is found corresponding value field is
returned.
 If the page is not in the TLB(known as TLB miss), a memory reference to the page
must be made.
 When the frame is obtained we can use it to access memory.
 If TLB is already full, the operating system must select one for replacement.
 Replacement policies range from least recently used(LRU) to random.
 TLB allow entries to be wired down, they cannot be removed from the TLB. Typically31
kernel code are often wired down.
 ASSOCIATIVE MEMORY
 Associative memory – parallel search
Page # Frame #

 Address translation (p, d)


If p is in associative register, get frame # out
 Otherwise get frame # from page table in
memory
Search is fast, hardware is expensive.
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PAGING HARDWARE WITH TLB

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 EFFECTIVE ACCESS TIME (EAT)

 Associative Lookup =  time unit

 Assume memory cycle time is 1 microsecond

 Hit ratio – percentage of times that a page number is found in the

associative registers; ratio related to number of associative registers
 Hit ratio = 

 Effective Access Time (EAT)

EAT = (1 + )  + (2 + )(1 – )
=2+–

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 EFFECTIVE ACCESS TIME (EAT)
 80 percent hit ratio means then we find desired page in TLB 80 percent of the
time. (80/100 = 0.80)
 If it takes 20 nanoseconds to search TLB, and 100 nanoseconds to access
memory, then memory access takes 120 nanoseconds when the page is in TLB.
 If we fail to find page number in the TLB (search 20 nanoseconds=0.20), then
access memory for page table and frame number (100 nanoseconds) and then
access the desired byte in memory (100 nanoseconds) for total 220 nanoseconds.
 Then effective memory access time = 0.8*120+0.20*220

= 140 nanoseconds.
 For a 98 percent hit ratio, we have

effective memory access time = 0.98*120+0.20*220 35

= 122 nanoseconds.
 MEMORY PROTECTION

 Memory protection implemented by associating protection bit with each

frame.
 Valid-invalid bit attached to each entry in the page table:

 “valid” indicates that the associated page is in the process’ logical address
space, and is thus a legal page
 “invalid” indicates that the page is not in the process’ logical address
space

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VALID (V) OR INVALID (I) BIT IN A
PAGE TABLE

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PAGING TO BE CONTINUE…