Single Event Effects (SEE) Test Results on the Virtex-II Digital Clock Manager (DCM)
Jason Moore1, Carl Carmichael1, Gary Swift2 and Jeff George3
1Xilinx
Corporation, San Jose CA 95124 2Jet Propulsion Laboratory / Caltech, Pasadena CA, 91109 3The Aerospace Corporation, El Segundo CA, USA
"This work was carried out in part by the Jet Propulsion Laboratory, California Institute of Technology, under contract with the National Aeronautics and Space Administration." "Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, does not constitute or imply its endorsement by the United States Government or the Jet Propulsion Laboratory, California Institute of Technology."
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DCM Functionality
What is a DCM?
Digital Clock Manager Embedded digital dedicated function in the FPGA that is configurable.
CLKIN CLKFB
RST DSSEN PSINCDEC PSEN PSCLK
DCM
CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 LOCKED STATUS[7:0] PSDONE
Delay-Locked Loop
Clock phase de-skew Duty cycle correction Temperature compensation
Improves device Tcko
Frequency Synthesis
CLKFX = CLKIN * (M/D)
Phase Shift
Fixed or Variable Mode Resolution = 1/256 * period OR resolution of tap (~50ps)
2
Clock signal Control signal
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Moore
DCM Functionality
Why use a DCM?
Most common function is the removal of clock insertion delay
Tcko of FPGA without a DCM
Tcko(FPGA) = Insertion Delay + Tcko (FF) + Data Delay
Tcko of FPGA with a DCM
Tcko(FPGA) = Tcko (FF) + Data Delay Clock at pad of FPGA and internal FFs are aligned
DCM
BUFG
This configuration was chosen for testing
Clock Path: clk to a_14(FF) Location Delay type Delay(ns) Logical Resource(s) -------------------------------------------------------D12.I Tiopi 0.653 clk (dcm_comp_CLKIN_IBUFG_INST) DCM_X0Y1.CLKIN net (fanout=1) 0.633 dcm_comp_CLKIN_IBUFG_OUT DCM_X0Y1.CLK0 Tdcmino -3.741 dcm_comp_DCM_INST BUFGMUX7P.I0 net (fanout=1) 0.674 dcm_comp_CLK0_BUF BUFGMUX7P.O Tgi0o 0.465 dcm_comp_CLK0_BUFG_INST U10.ICLK1 net (fanout=55) 0.742 clk_int -----------------------------------------------------------------------------------------------------------------------Moore 3
Removal of Clock Insertion Delay Significant Impact on High-Speed Designs!
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DCM Radiation Test Strategy
Elementary Tests
How hard is the DCM to upset?
SEUPI1 Analysis= 166 Configuration Memory Cells / DCM Empirical Analysis = 160 Configuration Memory Cells (2 are unused)
What common error modes are observed?
Advanced Tests
Detailed analysis of error modes Mitigation Evaluation
DCM Configurations
Not every permutation and combination of DCM options tested Focused on most common applications
CLK0 and CLKFX
1: Single Event Upset Probability Indicator
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Virtex-II Radiation Test Platform
CONFIGMON SW CONFIGMON HW
Virtex-II SEAKR Board
FUNCMON SW FUNCMON HW Service FPGA 2V3000 DUT FPGA 2V6000
Functional Monitor/Control : FUNCMON
User-Specific Functionality (e.g. DCM, I/O, Multipliers, etc)
Configuration Monitor/Control : CONFIGMON
Common Configuration Logic Scrubbing; Readback for SEFI Detection
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Virtex-II Radiation Test Board
JTAG I/F Service PROMs DUT FPGA
DUT PROMS
(design and mask)
Service FPGA
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Elementary DCM Test
November 03 : Texas A&M Cyclotron
Focus on Cross-Section Calculations Focus on Common Error Modes Device Under Test (DUT) FPGA Design
CLK0 de-skew : Most common application Six DCMs tested simultaneously Scrubbing configuration memory continuously
DCM
BUFG
Service FPGA Design
Basic Concept : Compare the output of three counters
Counters operate at 100MHz Two Radiation Counters, One Golden Counter Error Modes Detected Stuck At, Transients and Change in Frequency
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Elementary DCM Test
reset
OSC
Design Details
IBUFG DCM CLKIN CLKFX OBUF
SERVICE FPGA
3x MULT = 100MHz All clocks
To DUT DCMs (top)
DUT FPGA
DCM CLKIN OBUF CLKFX
IBUFG
CLKFB CLK0 CLKIN
BUFG
To DUT DCMs (bot)
(x6)
RST STATUS LOCK
DCM
Status Registers
IO Fail Count DCM Fail Count DCM Data A DCM Data B DCM Data C
CLKIN CLK0 CLKFX CLKFB
BUFG BUFG
DCMreset
Golden Clock
Error Detection and Reporting (x6)
Radiation Clocks
Redundant outputs from the DUT DCM allow detection of I/O errors
Routing errors are included in the DCM error analysis (worst case) Asynchronous FIFOs used to transfer count values across clock domains Dual-Port RAMs used to store status register values Upon every error, a flag is set and the values of LOCKED and STATUS(1) are recorded
Error Detection and Reporting Logic
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Elementary DCM Test
Results
Cross-Section Results
40.0 MeV/u Ne, LET=1.22 MeV/cm2/mg Cross Section: 8e-9 cm2/DCM
Need more visibility into Error Detection and Correction
Understanding of Mitigation Methods
Reset vs Scrub vs Reset and Scrub
Error Detection: Is LOCKED a reliable status?
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Advanced DCM Tests
June and August 04 : Texas A&M Cyclotron
Multiple LETs and Ions
Ne, Ar, Kr, 1.28, 4.28, 18.1 and 35.1 (MeV/mg/cm2)
Provided more User Control
Added Control FSM : User dictates Reset or Scrub command
Detailed Error Logging
Which errors are corrected by
Reset Scrub Scrub and Reset
2nd and 3rd DUT Configurations Created
CLKFX output CLK0 output at slower frequencies
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Device Under Test Configurations
DUT DCM Configuration
CLK0 w/feedback 100MHz in and out (CLK0FAST) 33MHz in and out (CLK0SLOW)
DCM1 DCM2
DUT DCM Configuration
CLKFX w/ CLK0 feedback 33MHz in -> 100MHz out CLKFX
DCM3
CLK0 33MHz or 100MHz
BUFG
DCM
33MHz or 100MHz
33MHz CLKFX DCM
BUFG 100MHz BUFG
DCM4
DCM5
DCM6
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DCM Control
Reset Only Data Path Errors Scrub required Configuration Errors
Wait for DCM Error
Reset DCM
fixed
Not fixed
Scrub DCM
fixed
Not fixed
Reset DCM
fixed
Test Operator has complete control of Correction Method
Reset, Scrub, Scrub and Reset
Scrub
Refresh of configuration memory while operating
Reset
DCM Reset Only
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DCM Functional Monitor SW
Logging
Run/Error Status
Per DCM Control and Status
User Controlled Reset
Real-time value of LOCKED output
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Cross-Section Results
DCM CLK0 and CLKFX outputs have statistically equivalent susceptibility
DCM
1.E-04
1.E-05
Cross Section
1.E-06 CLKFX 1.E-07 CLK0FAST CLK0SLOW 1.E-08
1.E-09 0 5 10 15 20 25 30 35 40
LET (MeV/mg/cm2)
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Cross-Section Results
No evidence of SET effects on the DCM between 33 and 100MHz.
CLK0
1.E-04 1.E-05
Cross Section
1.E-06 1.E-07 1.E-08 1.E-09 0 20 40 60
Frequency (MHz)
Ne 40MeV Kr 40MeV Ar 40MeV
80
100
120
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Cross-Section Analysis
1.E-04
Large % of errors at a high LET are in the datapath
DCM reset is all that is
required to restore operation 20-120us LOCK time (CLK0) 10ms LOCK time (CLKFX)
1.E-05
Cross Section (cm2/DCM)
1.E-06
1.E-07
1.E-08 DCM Cross-Section DCM Data Path Errors DCM Configuration Errors Configuration (single bit)
DCM Configuration Cell Usage is consistent
~38% (60 of 160) of the
DCM Configuration Cells are critical for the CLKFX and CLK0 designs.
1.E-09 0 5 10 15 20 25
LET (MeV/mg/cm2)
30
35
40
45
50
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Lessons Learned and Future Work
Lessons Learned
Elementary Tests are not efficient or cost effective
Development of Fault Injection capabilities will eliminate the need for beam time during the early stages of SEU evaluation
Future Work
Analysis and test of self-EDAC logic
Autonomous Detection and Correction using XTMR
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Summary
Results
The saturated DCM Cross-Section is ~1e-5 CLK0 and CLKFX Configuration Bit exposure is ~60 bits Data Path Errors dominate at LET > 5 MeV/cm2/mg
Only a reset is required to resynchronize DCM
No apparent frequency dependence from 33MHz to 100MHz DCM LOCKED output is not a reliable indicator of upsets Scrubbing the DCM does not disturb the LOCK signal An SEU in the DCM will not cause a functional failure of the if the Xilinx Triple Module Redundancy method is employed.
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