Chapter 3: Node Architecture

Outline
 The Sensing Subsystem
 Analog-to-Digital Converter
 The Processor Subsystem
 Architectural Overview
 Microcontroller
 Digital Signal Processor
 Application-specific Integrated Circuit
 Field Programmable Gate Array
 Comparison
 Communication Interfaces
 Serial Peripheral Interface
 Inter-Integrated Circuit
 Summary
 Prototypes
 The IMote Node Architecture
 The XYZ Node Architecture
 The Hogthrob Node Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 2

 Node Architecture
 Wireless sensor nodes are the essential building blocks
in a wireless sensor network
 sensing, processing, and communication
 stores and executes the communication protocols as well as
data processing algorithms
 The node consists of sensing, processing,
communication, and power subsystems
 trade-off between flexibility and efficiency – both in terms of
energy and performance

Fundamentals of Wireless Sensor Networks: Theory and Practice 3

 Node Architecture

Figure 3.1 Architecture of a wireless sensor node

Fundamentals of Wireless Sensor Networks: Theory and Practice 4

 Outline
 The Sensing Subsystem
 Analog-to-Digital Converter
 The Processor Subsystem
 Architectural Overview
 Microcontroller
 Digital Signal Processor
 Application-specific Integrated Circuit
 Field Programmable Gate Array
 Comparison
 Communication Interfaces
 Serial Peripheral Interface
 Inter-Integrated Circuit
 Summary
 Prototypes
 The IMote Node Architecture
 The XYZ Node Architecture
 The Hogthrob Node Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 5

 The Sensing Subsystem
 The sensing subsystem integrates

Sensor Sensed Event Explanation

2D and 3D acceleration of
Accelerometer Volcano activities
movements of people and objects

Stiffness of a structure
Stiffness of bones, limbs, joints; Motor
fluctuation in Parkinson’s disease
Irregularities in rail, axle box or wheels of a
train system
Defect of fragile objects during
transportation
Acoustic Elastic waves generated by the
Measures micro-structural changes or
emission energy released during crack
displacements
sensor propagation
Acoustic Vehicle detection; Measure structural
Acoustic pressure vibration
sensor irregularities; Gas contamination
Capacitance
sensor Solute concentration Measure the water content of a soil

Fundamentals of Wireless Sensor Networks: Theory and Practice 6

 The Sensing Subsystem

Sensor Sensed Event Explanation

ECG Heart rate

EEG Brain electrical activity
EMG Muscle activity
Electrical capacitance or inductance
Measure of nutrient contents and
Electrical sensors affected by the composition of
distribution
tested soil
Gyroscope Angular velocity Detection of gait phases
Humidity sensor Relative and absolute humidity
Concussive acoustic waves –
Infrasonic sensor
earth quake or volcanic eruption
Presence, intensity, direction,
Presence, speed and density of a
Magnetic sensor rotation and variation of a magnetic
vehicle on a street; congestion
field
Blood oxygenation of patient's Cardiovascular exertion and trending
Oximeter
hemoglobin of exertion relative to activity
Indicates the acid and alkaline
pH sensor Concentration of hydrogen ions content of a water measure of
cleanliness

Fundamentals of Wireless Sensor Networks: Theory and Practice 7

 The Sensing Subsystem

Sensor Sensed Event Explanation

Photo acoustic
Gas sensing Detects gas leak in a pipeline
spectroscopy
A leak produces a high frequency
Piezoelectric noise that produces a high
Gas velocity
cylinder frequency noise that produces
vibration

Soil moisture sensor Soil moisture Fertilizer and water management

Temperature sensor Pressure exerted on a fluid

Passive infrared
Infrared radiation from objects Motion detection
sensor
Measure primary and secondary seismic
Seismic sensor Detection of earth quake
waves (Body wave, ambient vibration)
Amount and proportion of oxygen in the
Oxygen sensor
blood
The Doppler shift of a reflected ultrasonic
Blood flow sensor
wave in the blood

Fundamentals of Wireless Sensor Networks: Theory and Practice 8

 Outline
 The Sensing Subsystem
 Analog-to-Digital Converter
 The Processor Subsystem
 Architectural Overview
 Microcontroller
 Digital Signal Processor
 Application-specific Integrated Circuit
 Field Programmable Gate Array
 Comparison
 Communication Interfaces
 Serial Peripheral Interface
 Inter-Integrated Circuit
 Summary
 Prototypes
 The IMote Node Architecture
 The XYZ Node Architecture
 The Hogthrob Node Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 9

 Analog-to-Digital Converter
 ADC converts the output of a sensor - which is a
continuous, analog signal - into a digital signal. It
requires two steps:
1. the analog signal has to be quantized
 allowable discrete values is influenced :
(a) by the frequency and magnitude of the signal
(b) by the available processing and storage resources

2. the sampling frequency

 Nyquist rate does not suffice because of noise and transmission error
 resolution of ADC - an expression of the number of bits that can be used
to encode the digital output

 where Q is the resolution in volts per step (volts per output code); Epp
is the peak-to-peak analog voltage; M is the ADC’s resolution in bits
Fundamentals of Wireless Sensor Networks: Theory and Practice 10
 Outline
 The Sensing Subsystem
 Analog-to-Digital Converter
 The Processor Subsystem
 Architectural Overview
 Microcontroller
 Digital Signal Processor
 Application-specific Integrated Circuit
 Field Programmable Gate Array
 Comparison
 Communication Interfaces
 Serial Peripheral Interface
 Inter-Integrated Circuit
 Summary
 Prototypes
 The IMote Node Architecture
 The XYZ Node Architecture
 The Hogthrob Node Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 11

 The Processor Subsystem
 The processor subsystem
 interconnects all the other subsystems and some additional
peripheries
 its main purpose is to execute instructions pertaining to sensing,
communication, and self-organization
 It consists of
 processor chip
 nonvolatile memory - stores program instructions
 active memory - temporarily stores the sensed data
 internal clock

Fundamentals of Wireless Sensor Networks: Theory and Practice 12

 Outline
 The Sensing Subsystem
 Analog-to-Digital Converter
 The Processor Subsystem
 Architectural Overview
 Microcontroller
 Digital Signal Processor
 Application-specific Integrated Circuit
 Field Programmable Gate Array
 Comparison
 Communication Interfaces
 Serial Peripheral Interface
 Inter-Integrated Circuit
 Summary
 Prototypes
 The IMote Node Architecture
 The XYZ Node Architecture
 The Hogthrob Node Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 13

 Architectural Overview
 The processor subsystem can be designed by employing
one of the three basic computer architectures
 Von Neumann architecture
 Harvard architecture
 Super-Harvard (SHARC) architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 14

 Von Neumann Architecture
 Von Neumann architecture
 provides a single memory space - storing program instructions
and data
 provides a single bus - to transfer data between the processor
and the memory
 Slow processing speed - each data transfer requires a separate
clock

Fundamentals of Wireless Sensor Networks: Theory and Practice 15

Von Neumann Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 16

 Harvard Architecture
 Harvard architecture
 provides separate memory spaces - storing program
instructions and data
 each memory space is interfaced with the processor with a
separate data bus
 program instructions and data can be accessed at the same
time
 a special single instruction, multiple data (SIMD) operation, a
special arithmetic operation and a bit reverse
 supports multi-tasking operating systems; but does not provide
virtual memory protection

Fundamentals of Wireless Sensor Networks: Theory and Practice 17

Harvard Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 18

 Super-Harvard Architecture
 Super-Harvard architecture (best known: SHARC)
 an extension of the Harvard architecture
 adds two components to the Harvard architecture:
 internal instruction cache - temporarily stores frequently used
instructions - enhances performance
 an underutilized program memory can be used as a temporary
relocation place for data
 Direct Memory Access (DMA)
 costly CPU cycles can be invested in a different task
 program memory bus and data memory bus accessible from outside the
chip

Fundamentals of Wireless Sensor Networks: Theory and Practice 19

 Super-Harvard Architecture

Program Memory Processor Data Memory

Instruction Cache

Address Bs

Data Bus

I/O Controller

Fundamentals of Wireless Sensor Networks: Theory and Practice 20

 Outline
 The Sensing Subsystem
 Analog-to-Digital Converter
 The Processor Subsystem
 Architectural Overview
 Microcontroller
 Digital Signal Processor
 Application-specific Integrated Circuit
 Field Programmable Gate Array
 Comparison
 Communication Interfaces
 Serial Peripheral Interface
 Inter-Integrated Circuit
 Summary
 Prototypes
 The IMote Node Architecture
 The XYZ Node Architecture
 The Hogthrob Node Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 21

 Microcontroller
 Structure of microcontroller
 integrates the following components:
 CPU core
 volatile memory (RAM) for data storage
 ROM, EPROM, EEPROM, or Flash memory
 parallel I/O interfaces
 discrete input and output bits
 clock generator
 one or more internal analog-to-digital converters
 serial communications interfaces

Fundamentals of Wireless Sensor Networks: Theory and Practice 22

 Microcontroller
 Advantages:
 suitable for building computationally less intensive, standalone
applications, because of its compact construction, small size,
low-power consumption, and low cost
 high speed of the programming and eases debugging, because
of the use of higher-level programming languages
 Disadvantages:
 not as powerful and as efficient as some custom-made
processors (such as DSPs and FPGAs)
 some applications (simple sensing tasks but large scale
deployments) may prefer to use architecturally simple but
energy- and cost-efficient processors

Fundamentals of Wireless Sensor Networks: Theory and Practice 23

 Outline
 The Sensing Subsystem
 Analog-to-Digital Converter
 The Processor Subsystem
 Architectural Overview
 Microcontroller
 Digital Signal Processor
 Application-specific Integrated Circuit
 Field Programmable Gate Array
 Comparison
 Communication Interfaces
 Serial Peripheral Interface
 Inter-Integrated Circuit
 Summary
 Prototypes
 The IMote Node Architecture
 The XYZ Node Architecture
 The Hogthrob Node Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 24

 Digital Signal Processor
 The main function:
 process discrete signals with digital filters
 filters minimize the effect of noise on a signal or enhance or
modify the spectral characteristics of a signal
 while analog signal processing requires complex hardware
components, digital signal processors (DSP) requires simple
adders, multipliers, and delay circuits
 DSPs are highly efficient
 most DSPs are designed with the Harvard Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 25

 Digital Signal Processor
 Advantages:
 powerful and complex digital filters can be realized with
commonplace DSPs
 useful for applications that require the deployment of nodes in
harsh physical settings (where the signal transmission suffers
corruption due to noise and interference and, hence, requires
aggressive signal processing)
 Disadvantage:
 some tasks require protocols (and not numerical operations) that
require periodical upgrades or modifications (i.e., the networks
should support flexibility in network reprogramming )

Fundamentals of Wireless Sensor Networks: Theory and Practice 26

 Outline
 The Sensing Subsystem
 Analog-to-Digital Converter
 The Processor Subsystem
 Architectural Overview
 Microcontroller
 Digital Signal Processor
 Application-specific Integrated Circuit
 Field Programmable Gate Array
 Comparison
 Communication Interfaces
 Serial Peripheral Interface
 Inter-Integrated Circuit
 Summary
 Prototypes
 The IMote Node Architecture
 The XYZ Node Architecture
 The Hogthrob Node Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 27

 Application-specific Integrated Circuit
 ASIC is an IC that can be customized for a specific
application
 Two types of design approaches: full-customized and
half-customized
 full-customized IC:
 some logic cells, circuits, or layout are custom made in order to
optimize cell performance
 includes features which are not defined by the standard cell library
 expensive and long design time
 half-customized ASICs are built with logic cells that are available
in the standard library
 in both cases, the final logic structure is configured by the end
user - an ASIC is a cost efficient solution, flexible, and reusable

Fundamentals of Wireless Sensor Networks: Theory and Practice 28

 Application-specific Integrated Circuit
 Advantages:
 relatively simple design; can be optimized to meet a specific
customer demand
 multiple microprocessor cores and embedded software can be
designed in a single cell
 Disadvantage:
 high development costs and lack of re-configurability
 Application:
 ASICs are not meant to replace microcontrollers or DSPs but to
complement them
 handle rudimentary and low-level tasks
 to decouple these tasks from the main processing subsystem

Fundamentals of Wireless Sensor Networks: Theory and Practice 29

 Outline
 The Sensing Subsystem
 Analog-to-Digital Converter
 The Processor Subsystem
 Architectural Overview
 Microcontroller
 Digital Signal Processor
 Application-specific Integrated Circuit
 Field Programmable Gate Array
 Comparison
 Communication Interfaces
 Serial Peripheral Interface
 Inter-Integrated Circuit
 Summary
 Prototypes
 The IMote Node Architecture
 The XYZ Node Architecture
 The Hogthrob Node Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 30

 Field Programmable Gate Array (FPGA)
 The distinction between ASICs and FPGAs is not always
clear
 FPGAs are more complex in design and more flexible to
program
 FPGAs are programmed electrically, by modifying a packaged
part
 programming is done with the support of circuit diagrams and
hardware description languages, such as VHDL and Verilog

Fundamentals of Wireless Sensor Networks: Theory and Practice 31

 Field Programmable Gate Array (FPGA)
 Advantages:
 higher bandwidth compared to DSPs
 flexible in their application
 support parallel processing
 work with floating point representation
 greater flexibility of control
 Disadvantages:
 complex
 the design and realization process is costly

Fundamentals of Wireless Sensor Networks: Theory and Practice 32

 Outline
 The Sensing Subsystem
 Analog-to-Digital Converter
 The Processor Subsystem
 Architectural Overview
 Microcontroller
 Digital Signal Processor
 Application-specific Integrated Circuit
 Field Programmable Gate Array
 Comparison
 Communication Interfaces
 Serial Peripheral Interface
 Inter-Integrated Circuit
 Summary
 Prototypes
 The IMote Node Architecture
 The XYZ Node Architecture
 The Hogthrob Node Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 33

 Comparison
 Working with a micro-controller is preferred if the design
goal is to achieve flexibility
 Working with the other mentioned options is preferred if
power consumption and computational efficiency is
desired
 DSPs are expensive, large in size and less flexible; they
are best for signal processing, with specific algorithms
 FPGAs are faster than both microcontrollers and digital
signal processors and support parallel computing; but
their production cost and the programming difficulty
make them less suitable

Fundamentals of Wireless Sensor Networks: Theory and Practice 34

 Comparison
 ASICs have higher bandwidths; they are the smallest in
size, perform much better, and consume less power than
any of the other processing types; but have a high cost
of production owing to the complex design process

Fundamentals of Wireless Sensor Networks: Theory and Practice 35

 Outline
 The Sensing Subsystem
 Analog-to-Digital Converter
 The Processor Subsystem
 Architectural Overview
 Microcontroller
 Digital Signal Processor
 Application-specific Integrated Circuit
 Field Programmable Gate Array
 Comparison
 Communication Interfaces
 Serial Peripheral Interface
 Inter-Integrated Circuit
 Summary
 Prototypes
 The IMote Node Architecture
 The XYZ Node Architecture
 The Hogthrob Node Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 36

 Communication Interfaces
 Fast and energy efficient data transfer between the
subsystems of a wireless sensor node is vital
 however, the practical size of the node puts restriction on
system buses
 communication via a parallel bus is faster than a serial
transmission
 a parallel bus needs more space
 Therefore, considering the size of the node, parallel
buses are never supported

Fundamentals of Wireless Sensor Networks: Theory and Practice 37

 Communication Interfaces
 The choice is often between serial interfaces :
 Serial Peripheral Interface (SPI)
 General Purpose Input/Output (GPIO)
 Secure Data Input/Output (SDIO)
 Inter-Integrated Circuit (I2C)
 Among these, the most commonly used buses are SPI
and I2C

Fundamentals of Wireless Sensor Networks: Theory and Practice 38

 Outline
 The Sensing Subsystem
 Analog-to-Digital Converter
 The Processor Subsystem
 Architectural Overview
 Microcontroller
 Digital Signal Processor
 Application-specific Integrated Circuit
 Field Programmable Gate Array
 Comparison
 Communication Interfaces
 Serial Peripheral Interface
 Inter-Integrated Circuit
 Summary
 Prototypes
 The IMote Node Architecture
 The XYZ Node Architecture
 The Hogthrob Node Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 39

 Serial Peripheral Interface
 SPI (Motorola, in the mid-80s)
 high-speed, full-duplex synchronous serial bus
 does not have an official standard, but use of the SPI interface
should conform to the implementation specification of others -
correct communication
 The SPI bus defines four pins:
 MOSI (MasterOut/SlaveIn)
 used to transmit data from the master to the slave when a device is
configured as a master
 MISO (MasterIn/SlaveOut)
 SCLK (Serial Clock)
 used by the master to send the clock signal that is needed to
synchronize transmission
 used by the slave to read this signal synchronize transmission
 CS (Chip Select) - communicate via the CS port
Fundamentals of Wireless Sensor Networks: Theory and Practice 40
 Serial Peripheral Interface
 Both master and slave devices hold a shift register
 Every device in every transmission must read and send
data
 SPI supports a synchronous communication protocol
 the master and the slave must agree on the timing
 master and slave should agree on two additional parameters
 clock polarity (CPOL) - defines whether a clock is used as
high- or low-active
 clock phase (CPHA) - determines the times when the data in
the registers is allowed to change and when the written data
can be read

Fundamentals of Wireless Sensor Networks: Theory and Practice 41

Serial Peripheral Interface

Fundamentals of Wireless Sensor Networks: Theory and Practice 42

 Outline
 The Sensing Subsystem
 Analog-to-Digital Converter
 The Processor Subsystem
 Architectural Overview
 Microcontroller
 Digital Signal Processor
 Application-specific Integrated Circuit
 Field Programmable Gate Array
 Comparison
 Communication Interfaces
 Serial Peripheral Interface
 Inter-Integrated Circuit
 Summary
 Prototypes
 The IMote Node Architecture
 The XYZ Node Architecture
 The Hogthrob Node Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 43

 Inter-Integrated Circuit
 Every device type that uses I2C must have a unique
address that will be used to communicate with a device
 In earlier versions, a 7 bit address was used, allowing
112 devices to be uniquely addressed - due to an
increasing number of devices, it is insufficient
 Currently I2C uses 10 bit addressing
 I2C is a multi-master half-duplex synchronous serial bus
 only two bidirectional lines: (unlike SPI, which uses four)
 Serial Clock (SCL)
 Serial Data (SDA)

Fundamentals of Wireless Sensor Networks: Theory and Practice 44

 Inter-Integrated Circuit
 Since each master generates its own clock signal,
communicating devices must synchronize their clock
speeds
 a slower slave device could wrongly detect its address on the
SDA line while a faster master device is sending data to a third
device
 I2C requires arbitration between master devices wanting
to send or receive data at the same time
 no fair arbitration algorithm
 rather the master that holds the SDA line low for the longest time
wins the medium

Fundamentals of Wireless Sensor Networks: Theory and Practice 45

 Inter-Integrated Circuit
 I2C enables a device to read data at a byte level for a
fast communication
 the device can hold the SCL low until it completes reading or
sending the next byte - called handshaking
 The aim of I2C is to minimize costs for connecting
devices
 accommodating lower transmission speeds
 I2C defines two speed modes:
 a fast-mode - a bit rate of up to 400Kbps
 high-speed mode - a transmission rate of up to 3.4 Mbps
 they are downwards compatible to ensure communication with
older components

Fundamentals of Wireless Sensor Networks: Theory and Practice 46

 Comparison
SPI I 2C
2 lines reduce space and simplify circuit layout;
4 lines enable full-duplex transmission
Lowers costs
Addressing enables multi-master mode; Arbitration
No addressing is required due to CS
is required
Allowing only one master avoids conflicts Multi-master mode is prone to conflicts
Hardware requirement support increases with an Hardware requirement is independent of the
increasing number of connected devices -- costly number of devices using the bus
The master's clock is configured according to the
Slower devices may stretch the clock -- latency but
slave's speed but speed adaptation slows down
keeping other devices waiting
the master.
Speed depends on the maximum speed of the
Speed is limited to 3.4 MHz
slowest device
Heterogeneous registers size allows flexibility in
Homogeneous register size reduces overhead
the devices that are supported.
Combined registers imply every transmission Devices that do not read or provide data are not
should be read AND write forced to provide potentially useless bytes
The absence of an official standard leads to Official standard eases integration of devices since
application specific implementations developers can rely on a certain implementation

Fundamentals of Wireless Sensor Networks: Theory and Practice 47

 Outline
 The Sensing Subsystem
 Analog-to-Digital Converter
 The Processor Subsystem
 Architectural Overview
 Microcontroller
 Digital Signal Processor
 Application-specific Integrated Circuit
 Field Programmable Gate Array
 Comparison
 Communication Interfaces
 Serial Peripheral Interface
 Inter-Integrated Circuit
 Summary
 Prototypes
 The IMote Node Architecture
 The XYZ Node Architecture
 The Hogthrob Node Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 48

 Communication Interfaces - Summary
 Buses are essential highways to transfer data
 due to the concern for size, only serial buses can be used
 serial buses demand high clock speeds to gain the same
throughput as parallel buses
 serial buses can also be bottlenecks (e.g., Von Neumann
architecture) or may not scale well with processor speed (e.g.,
I2C)
 Delays due to contention for bus access become critical,
for example, if some of the devices act unfairly and keep
the bus occupied

Fundamentals of Wireless Sensor Networks: Theory and Practice 49

 Outline
 The Sensing Subsystem
 Analog-to-Digital Converter
 The Processor Subsystem
 Architectural Overview
 Microcontroller
 Digital Signal Processor
 Application-specific Integrated Circuit
 Field Programmable Gate Array
 Comparison
 Communication Interfaces
 Serial Peripheral Interface
 Inter-Integrated Circuit
 Summary
 Prototypes
 The IMote Node Architecture
 The XYZ Node Architecture
 The Hogthrob Node Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 50

 The IMote Node Architecture
 The IMote sensor node architecture is a multi-purpose
architecture, consisting of :
 a power management subsystem
 a processor subsystem
 a sensing subsystem
 a communication subsystem
 an interfacing subsystem

Fundamentals of Wireless Sensor Networks: Theory and Practice 51

The IMote Node Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 52

 The IMote Node Architecture
 A multiple-sensor board contains :
 a 12-bit, four channels ADC
 a high-resolution temperature/humidity sensor
 a low-resolution digital temperature sensor
 a light sensor
 the I2C bus is used to connect low data rate sources
 the SPI bus is used to interface high data rate sources

Fundamentals of Wireless Sensor Networks: Theory and Practice 53

The IMote Node Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 54

 The IMote Node Architecture
 The processing subsystem provides
 main processor (microprocessor)
 operates in low voltage (0.85V) and low frequency (13MHz) mode
 Dynamic Voltage Scaling (104MHz - 416MHz)
 sleep and deep sleep modes
 thus enabling low power operation
 coprocessor (a DSP)
 accelerates multimedia operations - computation intensive

Fundamentals of Wireless Sensor Networks: Theory and Practice 55

 The XYZ Node Architecture
 Consists of the four subsystems:
 power subsystem
 communication subsystem
 mobility subsystem
 sensor subsystem

Fundamentals of Wireless Sensor Networks: Theory and Practice 56

The XYZ Node Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 57

 The XYZ Node Architecture
 The processor subsystem is based on the ARM7TDMI
core microcontroller
 fmax = 58MHz
 two different modes (32bits and 16bits)
 provides an on-chip memory of 4KB boot ROM and a 32KB
RAM - can be extended by up to 512KB of flash memory
 Peripheral components:
 DMA controller
 fopur 10-bit ADC inputs
 serial ports (RS232, SPI, I2C, SIO)
 42 multiplexed general purpose I/O pins

Fundamentals of Wireless Sensor Networks: Theory and Practice 58

 The XYZ Node Architecture
 The communication subsystem is connected to the
processing subsystem through a SPI interface
 CC2420 RF transceiver
 when an RF message has been successfully received, the SPI
interface enables the radio to wake up a sleeping processor
 the processor subsystem controls the communication subsystem
by either turning it off or putting it in sleep mode

Fundamentals of Wireless Sensor Networks: Theory and Practice 59

 The Hogthrob Node Architecture
 Designed for a specific application, namely, to monitor
pig production
 Motivation:
 monitors movements of a sow to predict onset of
estrus
 so that appropriate care can be given for pregnant sows
 detecting cough or limping to monitor illness

Fundamentals of Wireless Sensor Networks: Theory and Practice 60

The Hogthrob Node Architecture

Fundamentals of Wireless Sensor Networks: Theory and Practice 61

 The Hogthrob Node Architecture
 The processing subsystems consists of :
 microcontroller
 performs less complex, less energy intensive tasks
 initializes the FPGA and functions as an external timer and an ADC
converter to it
 Field Programmable Gate Array
 executes the sow monitoring application
 coordinates the functions of the sensor node

Fundamentals of Wireless Sensor Networks: Theory and Practice 62

 The Hogthrob Node Architecture
 There are a number of interfaces supported by the
processing subsystem, including
 the I2C interface for the sensing subsystem
 the SPI interface for the communication subsystem
 the JTAG interface for in-system programmability and debugging
 the serial (RS232) interface for interaction with a PC

Fundamentals of Wireless Sensor Networks: Theory and Practice 63