Assembly Languages

&
MIPS ISA
CS465
Lecture 2
 Outline
• Introduction to assembly languages
• MIPS instruction set architecture
– MIPS basic instructions
• Arithmetic instructions
• Data transfer instructions
• Control instructions
• Logical operations
– MIPS instruction format
– Encoding/decoding assembly code
 Instructions
• Instruction Set Architecture (ISA)
– An abstract interface between the hardware and software
that encompasses all the information necessary to write a
correct machine program
• The set of instructions that a particular CPU implements
• Hardware resources: registers, memory, I/O, …

– The set of instructions / primitive operations that a CPU

may execute is a major component of ISA
• Basic job of a CPU: execute instructions
• Different CPUs implement different sets of instructions, e.g: Intel
80x86 (Pentium 4), IBM/Motorola PowerPC (Macintosh), MIPS, Intel
IA64, ...

– Assembly language is a textual version of these instructions

 Assembly Language
• Assembly language vs. higher-level language
– Few, simple types of data
– Does not specify variable type
– Simple control flow: goto/jump
– Assembly language programming is more difficult and
error-prone, it is machine-specific; it is longer
• Assembly language vs. machine language
– Symbolic representation
• When assembly programming is needed
– Speed and size (eg. embedded computer)
– Time-critical parts of a program
– Specialized instructions
 Instruction Set Architectures
• Early trend was to add more and more
instructions to new CPUs to do elaborate
operations
– VAX architecture had an instruction to multiply
polynomials!
• RISC philosophy – Reduced Instruction Set
Computing
– Cocke (IBM), Patterson, Hennessy, 1980s
– Keep the instruction set small and simple, makes it
easier to build faster hardware
– Let software do complicated operations by composing
simpler ones
– Examples: MIPS, SPARC, IBM PowerPC, DEC Alpha
 MIPS Architecture
• We will study the MIPS architecture in
some detail in this class
– MIPS – semiconductor company that built
one of the first commercial RISC
architectures
• Why MIPS?
– MIPS is simple, elegant and similar to other
architectures developed since the 1980's
– MIPS widely used in embedded apps
• Almost 100 million MIPS processors
manufactured in 2002
• Used by NEC, Nintendo, Cisco, Silicon
Graphics, Sony, …
 MIPS Arithmetic
• All instructions have 3 operands
– One destination, two operands
• Operand order is fixed (destination first)
– Example:
C code: a = b + c
MIPS code: add a,b,c
C code: a = b + c + d;
MIPS code: add a, b, c
add a, a, d

– Design principle: Hardware implementation is simplified via

regularity
• Operands must be registers in MIPS
– Register set of a machine is a limited number of special locations
built directly into the hardware
 Assembly Variables: Registers
• Unlike HLL, assembly cannot use variables
– Why not? Keep hardware simple
• Different operand locations for different
architectures
– Stack, register, memory or a mix of them
– Every architecture design after 1980 uses a load-store
register architecture: ALU operands are all registers;
memory can only be accessed with load/store
• Advantages of load-store register architectures
– Registers are faster than memory
– Registers are more efficient for a compiler to use
• Drawback: the no. of registers is predetermined
– Assembly code must be very carefully put together to
efficiently use registers
 MIPS Registers
• 32 registers in MIPS
– Why 32? Design principle: Smaller is faster
– Registers are numbered from 0 to 31
• Each register can be referred to by number or name
– Number references: $0, $1, … $30, $31
– By convention, each register also has a name to make it
easier to code
• $t0 - $t7 for temporary variables ($8- $15)
• $ra for return address

• Each MIPS register is 32 bits wide

– Groups of 32 bits called a word in MIPS
MIPS Arithmetic with Registers
• MIPS Example
– C code: a = b + c
MIPS code: add $s1,$s2,$s3

– C code: a = b + c + d;
MIPS code: add $t1,$s2,$s3
add $s1,$t1,$s4
– $s0-$s7 conventionally are used for registers that
correspond to variables in C/Java programs ($16-$23)
C, Java Variables vs. Registers
• In C (and most high level languages), variables
declared first and given a type
– Example: int fahr, celsius;
char a, b, c, d, e;
– Each variable can ONLY represent a value of the type
it was declared as (cannot mix and match int and char
variables)

• In assembly language, the registers have no type;

operation determines how register contents are
treated
 MIPS Instructions
• Syntax of instructions:
op dest, src1, src2
– Op: operation by name
– Dest: operand getting result (“destination”)
– Src1: 1st operand for operation (“source1”)
– Src2: 2nd operand for operation (“source2”)
• Each line of assembly code contains at most 1
instruction
• Hash (#) is used for MIPS comments
– Anything from hash mark to end of line is a comment and
will be ignored
– Every line of your comments must start with a #
 Addition/Subtraction Example
• How to do the following C statement?
a = b + c + d - e;
• Break into multiple instructions
– add $t0, $s1, $s2 #temp = b + c
– add $t0, $t0, $s3 #temp = temp + d
– sub $s0, $t0, $s4 #a = temp - e
• Notice
– A single line of C code may break up into several lines of MIPS
code
– May need to use temporary registers ($t0 - $t9) for
intermediate results
– Everything after the hash mark on each line is ignored
(comments)
 Constant or Immediate Operands
• Immediates are numerical constants
– They appear often in code, so there are
special instructions for them
– Design principle: Make the common case fast
• Add Immediate:
– C code : f = g + 10
– MIPS code: addi $s0,$s1,10
• MIPS registers $s0, $s1 are associated with C
variables f, g
– Syntax similar to add instruction, except that
last argument is a number instead of a register
– How about subtraction? subi?
 Constant or Immediate
Operands
• There is NO subtract immediate instruction in
MIPS: Why?
– ISA design principle: limit types of operations that can
be done to minimum
– If an operation can be decomposed into a simpler
operation, do not include it
– addi …, -X = subi …, X => so no subi
• Example
– C code: f = g - 10
– MIPS code: addi $s0,$s1,-10
• MIPS registers $s0,$s1 are associated with C variables f, g
 Register Zero
• One particular immediate, the number zero (0),
appears very often in code
• So we define register zero ($0 or $zero) to
always have the value 0
– Often used to move values or set constant values
– f = g (in C)
– add $s0,$s1,$zero (in MIPS)
• MIPS registers $s0, $s1 are associated with C variables f, g
• $zero defined in hardware
– Instruction add $zero,$zero,$s0 will not do anything!
 Recap
• In MIPS assembly language:
– Registers replace C variables
– One instruction (simple operation) per line
– Simpler is better
– Smaller is faster
• There are no types in MIPS
– Types are associated with the instructions
• New instructions:
– add, addi, sub
• New registers:
– C variables: $s0 - $s7
– Temporary variables: $t0 - $t9
– Zero: $zero
 Anatomy Registers
of a Computer
are in the datapath of the
processor; program data are in
Personal Computer memory, we must transfer them to the
processor to operate on them, and then
transfer back to memory when done

Computer
Processor Memory Devices

Control Input
(“brain”)
Store (to)
Datapath
Registers Output
Load (from)

These are “data transfer” instructions…

 Memory Organization
• Viewed as a large, single-dimension array
• A memory address is an index into the
array
– "Byte addressing" means that the index points
to a byte of memory 0 8 bits of data
1 8 bits of data

2 8 bits of data

3 8 bits of data

4 8 bits of data

5 8 bits of data

6 8 bits of data

...
 Memory Organization
• Bytes are nice, but most data items use larger
"words"
– For MIPS, a word is 32 bits or 4 bytes 0 32 bits of data

4 32 bits of data

8 32 bits of data

12 32 bits of data

...

• MIPS register holds 32 bits of data

– 232 bytes with byte addresses from 0 to 232-1
– 230 words with byte addresses 0, 4, 8, ... 232-4
• Words are aligned: they must start at addresses that
are multiples of 4
 Specify Memory Addresses
• To transfer data, we need to specify:
– Register: specify this by number ($0 - $31) or symbolic name
($s0,…, $t0, …)
– Memory address: supply a pointer/index to the byte-addressed
one-dimensional array
• Often, we want to be able to offset from a pointer: e.g. element A[2],
date.month
• The general format for a memory address offset(base
register) specifying
– A register containing a pointer to memory
– A numerical offset (in bytes)
• The desired memory address is the sum of these two
values
– Example: 8($t0) specifies memory[$t0+8] (byte)
 Data Transfer Instructions
• MIPS has two basic data transfer instructions for
accessing memory
lw $t0,4($s3) #load word from memory
sw $t0,8($s3) #store word to memory
• Load instruction syntax: lw reg1, offset(reg2)
– Operator name: lw (meaning Load Word, so 32 bits or one
word are loaded at a time)
– Reg1: register that will receive the transferred data
– Offset: a numerical offset in bytes
– Reg2: register containing pointer to memory, called base
register
 Load Word Example
Data flow

• Example: lw $t0,12($s0)
– This instruction will take the pointer in $s0, add 12
bytes to it, and then load the value from the memory
pointed to by this calculated sum into register $t0
• $s0 is called the base register
• 12 is called the offset
– Offset is generally used in accessing elements of
array or structure: base register points to beginning
of array or structure
 Store Instruction
• Also want to store from register into memory
– sw: meaning Store Word, so 32 bits or one word
are loaded at a time)
– Store instruction syntax is identical to Load’s

Data flow
• Example: sw $t0,12($s0)
– This instruction will take the pointer in $s0, add 12
bytes to it, and then store the value from register
$t0 into that memory address
– Remember: “Store INTO memory”
 Example
• C code: A[12] = h + A[8];
MIPS code:
lw $t0, 32($s3) # base addr of array A in $s3
# 1 array element is 4-byte
add $t0, $s2, $t0 # h is associated with $s2
sw $t0, 48($s3) # offset=12*4=48

• Can refer to registers by name (e.g., $s2, $t2) instead of

number
• Store word has destination last
• Remember arithmetic operands are registers, not
memory!
– Can’t write: add 48($s3), $s2, 32($s3)
 Pointers vs. Values
• Key concept: a register can hold any 32-bit
value
– That value can be a signed int, an unsigned
int, a pointer (memory address), and so on
– If you write add $t2,$t1,$t0, then $t0 and $t1
better contain values
– If you write lw $t2,0($t0), then $t0 better
contains a pointer
• Don’t mix these up!
•
Notes about Memory
Pitfall: forgetting that sequential word addresses
in machines do not differ by 1
– To transfer a word, the sum of the base address and
the offset must be a multiple of 4 (to be word aligned)
0 1 2 3 Last hex digit of address
Aligned 0, 4, 8, or Chex
1, 5, 9, or Dhex
Not
Aligned 2, 6, A, or Ehex
3, 7, B, or Fhex
• What if more variables than registers?
– Compiler tries to keep most frequently used variable in
registers
– Less common in memory: spilling
 Loading & Storing Bytes
• In addition to word data transfers, MIPS has byte data
transfers for characters (char type)
– Load byte: lb; store byte: sb
– Same format as lw, sw
• What to do with other 24 bits in the 32 bit register?
– lb: sign extends to fill upper 24 bits

xxxx xxxx xxxx xxxx xxxx xxxx xzzz zzzz

byte
• Normally do not to
…is copied want to sign extend chars
“sign-extend”
loaded
– MIPS instruction that does not sign extend when loading
bytes -- load byte unsigned: lbu This bit
 Outline
• Introduction to assembly language
• MIPS instruction set architecture
– MIPS basic instructions
• Arithmetic instructions: add, addi, sub
• Data transfer instructions: lw, sw, lb, sb, lbu
• Control instructions
• Logical operations
– MIPS instruction format
– Encoding/decoding assembly code
 C Decisions: if Statements
• 2 kinds of if statements in C
– if (condition) clause
– if (condition) clause1 else clause2
• Rearrange if-else using goto and labels into:
if (condition) goto L1;
clause2;
goto L2;
L1: clause1;
L2:
• Not as elegant as if-else, but same meaning
 MIPS Decision Instructions
• Decision instructions in MIPS
– beq register1, register2, L1
• beq is “branch if equal”
• same meaning as: if (register1==register2) goto L1
– bne register1, register2, L1
• bne is “branch if not equal”
• same meaning as: if (register1!=register2) goto L1

• Called conditional branches

– Can be used to implement complex control-flow
constructs for high level langauages
 MIPS Goto Instruction
• In addition to conditional branches, MIPS has
an unconditional branch:
j label
– Called a Jump Instruction: jump (or branch) directly
to the given label without needing to satisfy any
condition
– Same meaning as: goto label
• Technically, it’s the same as:
– beq $0,$0,label
• Condition always satisfied
 Compiling C if into MIPS
(true) (false)
i == j? i != j
• C code i == j
– if (i == j) f=g+h;
else f=g-h; f=g+h f=g-h
– Use mapping:
f: $s0, g: $s1, h: $s2, i: $s3,
j: $s4 Exit
• Final compiled MIPS code:
beq $s3,$s4,True # branch i==j
sub $s0,$s1,$s2 # f=g-h(false)
j Fin # goto Fin
True: add $s0,$s1,$s2 # f=g+h (true)
Fin:
• Note: Compiler automatically creates labels to handle decisions
(branches)
 Loops in C/Assembly (1/3)
• Simple loop in C; A[] is an array of integers
do { g = g + A[i];
i = i + j;
} while (i != h);
• Rewrite this as:
Loop:g = g + A[i];
i = i + j;
if (i != h) goto Loop;
• Use this mapping:
g, h, i, j, base of A
$s1, $s2, $s3, $s4, $s5
 Loops in C/Assembly (2/3)
• Original code:
Loop: g = g + A[i];
i = i + j;
if (i != h) goto Loop;
• Final compiled MIPS code:
Loop: sll $t1,$s3,2 #$t1= 4*i
add $t1,$t1,$s5 #$t1=addr A
lw $t1,0($t1) #$t1=A[i]
add $s1,$s1,$t1 #g=g+A[i]
add $s3,$s3,$s4 #i=i+j
bne $s3,$s2,Loop# goto Loop
# if i!=h
 Loops in C/Assembly (3/3)
• There are three types of loops in C:
– while
– do… while
– for
• Each can be rewritten as either of the other two, so
the method used in the previous example can be
applied to while- and for- loops as well

• Key concept: though there are multiple ways of

writing a loop in MIPS, the key to decision making is
conditional branch
 Recap
• Arithmetic instructions: add, addi, sub
• Data transfer instructions: lw, sw, lb, sb, lbu
– A pointer is just a memory address, so we can add to it
or subtract from it (using offset)
• A decision allows us to decide what to execute at
run-time rather than compile-time
– C decisions are made using conditional statements
within if, while, do while, for
– MIPS decision making instructions are the conditional
branches: beq and bne
– MIPS unconditional branch: j
 Inequalities in MIPS (1/3)
• General programs need to test < and > as well
as equalities (== and != in C)
• MIPS inequality instruction:
slt reg1,reg2,reg3
– “Set on Less Than”
– Meaning:
reg1reg1
• if (reg2 < reg3) = (reg2
= 1; < reg3);
• else reg1 = 0;
– In computereeze, “set” means “set to 1”,
“reset” means “set to 0”
 Inequalities in MIPS (2/3)
• How do we use this? Compile by hand:
if (g<h) goto Less; #g:$s0, h:$s1
• Answer: compiled MIPS code…
slt $t0,$s0,$s1 # $t0 = 1 if g<h
bne $t0,$0,Less # goto Less
# if $t0!=0
# (if (g<h)) Less:
– Branch if $t0 != 0  (g < h)
– Register $0 always contains the value 0, so bne and beq
often use it for comparison after an slt instruction
• A slt  bne pair means if(… < …)goto…
 Inequalities in MIPS (3/3)
• Now, we can implement <, but how do we
implement >, ≤ and ≥ ?
• We could add 3 more instructions, but:
– MIPS goal: simpler is better
• Can we implement ≤ in one or more
instructions using just slt and the branches?
• What about >?
• What about ≥?
 Immediates in Inequalities
• There is also an immediate version of slt to
test against constants: slti
– C loop
if (g >= 1) goto Loop
Loop: . . .
– MIPS loop
slti $t0,$s0,1 # $t0 = 1 if
# $s0<1 (g<1)
beq $t0,$0,Loop # goto Loop
# if $t0==0
# (if (g>=1)

A slt  beq pair means if(… ≥ …)goto…

 Outline
• Introduction to assembly language
• MIPS instruction set architecture
– MIPS basic instructions
• Arithmetic instructions: add, addi, sub
• Data transfer instructions: lw, sw, lb, sb
• Control instructions: bne, beq, j, slt, slti
• Logical operations
– MIPS instruction format
– Encoding/decoding assembly code
 Bitwise Operations
• Up until now, we’ve done arithmetic (add, sub,addi ),
memory access (lw and sw), and branches and
jumps
• All of these instructions view contents of register as a
single quantity (such as a signed or unsigned
integer)
• New perspective: view register as 32 raw bits rather
than as a single 32-bit number
– We may want to access individual bits (or groups of bits)
rather than the whole
– Two new classes of instructions: logical & shift operations
 Logical Operators
• Logical instruction syntax:
op dest, src1, src2
– Op: operation name (and, or, nor)
– Dest: register that will receive value
– Src1: first operand (register)
– Src2: second operand (register) or immediate
• Accept exactly 2 inputs and produce 1 output
– Benefit: rigid syntax simpler hardware
– Why nor?
• nor $t0, $t1, $t2 # $t0 = not ($t1 or $t2)
• Immediate operands
– andi, ori: both expect the third argument to be an immediate
Uses for Logical Operators (1/3)
• Use AND to create a mask
– Anding a bit with 0 produces a 0 at the output
while anding a bit with 1 produces the original
bit
• Example:
1011 0110 1010 0100 0011 1101 1001 1010
0000 0000 0000 0000 0000 1111 1111 1111
Mask retaining the last 12 bits
0000 0000 0000 0000 0000 1101 1001 1010
Uses for Logical Operators (2/3)
• A bit pattern in conjunction with AND is called
a mask that can conceal some bits
– The previous example a mask is used to isolate
the rightmost 12 bits of the bit-string by masking
out the rest of the string (e.g. setting it to all 0s)
– Concealed bits are set 0s, while the rest bits are
left alone
– In particular, if the first bit-string in the above
example were in $t0, then the following
instruction would mask it:
andi $t0,$t0,0xFFF
Uses for Logical Operators (3/3)
• Similarly effect of OR operation
– Oring a bit with 1 produces a 1 at the output while
oring a bit with 0 produces the original bit
– This can be used to force certain bits to 1s
• Example
– $t0 contains 0x12345678, then after this
instruction:
ori $t0, $t0, 0xFFFF
– $t0 contains 0x1234FFFF (e.g. the high-order 16
bits are untouched, while the low-order 16 bits are
forced to 1s)
 Shift
• Move (shift) all the bits in a word to the left
or right by a number of bits
– Example: shift right by 8 bits
0001 0010 0011 0100 0101 0110 0111 1000
0000 0000 0001 0010 0011 0100 0101 0110
– Example: shift left by 8 bits
0001 0010 0011 0100 0101 0110 0111 1000

0011 0100 0101 0110 0111 1000 0000 0000

 Logical Shift Instructions
• Shift instruction syntax:
op dest,reg,amt
– Op: operation name
– Dest: register that will receive value
– Reg: register with the value to be shifted
– Amt: shift amount (constant < 32)
• MIPS logical shift instructions:
– sll (shift left logical): shifts left and fills emptied bits with 0s
– srl (shift right logical): shifts right and fills emptied bits with
0s
– MIPS also has arithmetic shift instructions that fills with the
sign bit
 Outline
• Introduction to assembly language
• MIPS instruction set architecture
– MIPS basic instructions
• Arithmetic instructions: add, addi, sub
• Data transfer instructions: lw, sw, lb, sb
• Control instructions: bne, beq, j, slt, slti
• Logical operations: and, andi, or, ori, nor, sll, srl
– MIPS instruction format
– Encoding/decoding assembly code
 Stored Program Concept
• Instructions are represented as numbers/bits
• Programs are stored in memory
— to be read or written just like data
memory for data, programs,
compilers, editors, etc.

Processor Memory

• Fetch & execute cycle

– Instructions are fetched and put into a special register
– Bits in the register "control" the subsequent actions
– Fetch the “next” instruction and continue
 Consequence I: Everything
Addressed
• Since all instructions and data are stored in memory
as numbers, everything has a memory address
– Both branches and jumps use these
• C pointers are just memory addresses: they can
point to anything in memory
– Unconstrained use of addresses can lead to nasty bugs;
up to you in C; limits in Java
• One register keeps address of instruction being
executed: Program Counter (PC)
– Basically a pointer to memory: Intel calls it Instruction
Address Pointer, a better name
 Consequence II: Binary
Compatibility
• Programs are distributed in binary form
– Programs bound to specific instruction set
– Different versions for Macintoshes and PCs
• New machines want to run old programs/binaries as well as
programs compiled to new instructions
– Leads to instruction set evolving over time
– Selection of Intel 8086 in 1981 for 1st IBM PC is major
reason latest PCs still use 80x86 instruction set (Pentium
4); could still run program from 1981 PC today
• A stored-program machine is reprogrammable
– One important motivation was the need for a program to
increment or otherwise modify the address portion of
instructions
 Instruction Representation
• Instructions in MIPS are 32-bit long (one
word) and divided into “fields”
– Each field tells computer something about an
instruction
• We could define different fields for each
instruction, but MIPS defines only three basic
types of instruction formats due to simplicity
– R-format: register format
– I-format: immediate format
– J-format: jump format
 Instruction Formats
• I-format: immediate format
– Instructions with immediates
• Excluding shift instructions
– Data transfer instructions (since the offset counts as an
immediate)
– Branches (beq and bne)
• J-format: jump format
– j and jal (more details later)
• R-format: used for all other instructions
• It will soon become clear why the instructions have
been partitioned in this way
 R-Format Instructions (1/4)
• Define six fields of the following number of bits
each: 6 + 5 + 5 + 5 + 5 + 6 = 32
6 5 5 5 5 6
opcode rs rt rd shamt funct
– Each field has a name
– Each field is viewed as a 5- or 6-bit unsigned
integer, not as part of a 32-bit integer
– 5-bit fields can represent any number 0-31 (00000
- 11111) while 6-bit fields can represent any
number 0-63 (000000-111111)
 R-Format Instructions (2/4)
6 5 5 5 5 6
opcode rs rt rd shamt funct
• opcode: partially specifies the operation
– Also implies the instruction format: opcode=0 for all R-type
instructions
• funct: combined with opcode, exactly specifies the instruction
• rs (source register): generally register containing the 1st
operand
• rt (target register): generally register containing the 2nd
operand (note that name is misleading)
• rd (destination register): generally register which will receive
the result of computation
 R-Format Instructions (3/4)
• Notes about register fields:
– Each register field is exactly 5 bits, which means
that it can specify any unsigned integer in the
range 0-31
– Each of these fields specifies one of the 32
registers by number
– The word “generally” was used because there are
exceptions that we’ll see later
• E.g. multiplication will generate a result of 64 bit stored
in two special registers: nothing important in the rd field
 R-Format Instructions (4/4)
• Final field: shamt
– Shift amount: the amount a shift instruction will
shift by
– Shifting a 32-bit word by more than 31 is
useless, so this field is only 5 bits (so it can
represent the numbers 0-31)
– This field is set to 0 in all but the shift
instructions
• For a detailed description of field usage for
each instruction, see green insert in COD
3/e
 R-Format Example
• MIPS Instruction: add $8,$9,$10
– Encode to decide the value of each field
• opcode = 0, funct = 32 (look up in table in book)
• rd = 8 (destination)
• rs = 9 (first operand), rt = 10 (second operand)
• shamt = 0 (not a shift)
– Decimal number per field representation
0 9 10 8 0 32
– Binary number per field representation
000000 01001 01010 01000 00000 100000
hex
– Machine language instruction:
• Hex representation: 012A 4020hex
• Decimal representation: 19,546,144ten
 I-Format Instructions (1/4)
• What about instructions with immediates?
– 5-bit field only represents numbers up to the value
31: immediates may be much larger
– Ideally, MIPS would have only one instruction format
for simplicity: unfortunately, we need to compromise

– Still, try to define new instruction format that is

partially consistent with R-format
• The first three fields of both formats are the same size and
have the same names
• The rest three fields in R-format are merged to form a
single field for the immediate operand
 I-Format Instructions (2/4)
• Define four fields of the following number
of bits each: 6 + 5 + 5 + 16 = 32
6 5 5 16
opcode rs rt immediate

– Again, each field has a name

– Design key
• Only one field is inconsistent with R-format
• Most importantly, opcode is still in the same
location
 I-Format Instructions (3/4)
6 5 5 16
opcode rs rt immediate

• opcode: uniquely specifies an instruction

– No funct field
• rs: specifies the only register operand (if
there is one)
• rt: specifies register which will receive
result of computation
– This is why it’s called the target register “rt”
 I-Format Instructions (4/4)
• The immediate field
– Used to specify immediates for instructions with a
numerical constant operands
– Used to specify address offset in data transfer
instructions: lw, sw, etc.
– Used to specify branch address in bne and beq

– Range
• Both positive and negative numbers
• 16 bits  can be used to represent immediate up to 2 16
different values
• What if the number we want to represent is out of the range?
 I-Format Example
• MIPS Instruction: addi $21,$22,-50
– Encode for each field
• opcode = 8 (look up in table in book) Negative number
encoding: 2’s
• rs = 22 (register containing operand) complement
• rt = 21 (target register)
• immediate = -50 (by default, this is decimal)
– Decimal number per field representation
8 22 21 -50
– Binary number per field representation
001000 10110 10101 1111111111001110
– Hexadecimal representation: 22D5 FFCEhex
Decimal representation: 584,449,998ten
 Large Immediates
• Range of immediates is limited
– Length of immediate field is 16 bits
– Considered as a signed number (sign bit)
• Arithmetic operands or address offset can be larger
– 32-bit data / address in MIPS
– We need a way to deal with a 32-bit immediate in any I-
format instruction
• Solution:
– Handle it in software + new instruction
– Don’t change the current instructions: instead, add a new
instruction to help out
 Large Immediates
• New instruction:
lui register, immediate
– Load Upper Immediate
– Takes 16-bit immediate and puts these bits in the
upper half (high order half) of the specified register;
lower half is set to 0s
– Example:
• Want to write: addi $t0,$t0, 0xABABCDCD
• Need to write a sequence instead:
lui $at, 0xABAB ori
$at, $at, 0xCDCD add
$t0,$t0,$at
 Immediates in Conditional
Branches
• Branch instructions bne and beq
opcode rs rt immediate
– Field rs and rt specify registers to compare
– Field immediate specify branch address
• 16 bit is too small since we have 32-bit pointer to memory
• Observation
– Branches are used for if-else, while-loop, for-loop: tend to
branch to a nearby instruction
– We only need to know the difference between the branch
target and the current instruction address, which is much
smaller and 16-bit addressing might suffice in most cases
 PC-Relative Addressing
• Solution to branches in a 32-bit instruction: PC-
relative addressing
– PC is the special register containing the address of
the current instruction
– New program counter = PC + branch address
• Let the 16-bit immediate field be a signed two’s
complement integer to be added to the PC if we take the
branch
• Now we can branch ± 215 bytes from the PC,
which should be enough to cover almost any
loop
– Any ideas to further optimize this?
 PC-Relative Addressing
• Note: Instructions are words, so they are word
aligned
– The byte address of an instruction is always a
multiple of 4, i.e. it must end with 00 in binary
 The number of bytes to add to the PC will
always be a multiple of 4
 Specify the immediate in words
• Now, we can branch ± 215 words from the PC
(or ± 217 bytes), so we can handle loops 4
times as large
 Branch Address Calculation
• Calculation:
– If we do not take the branch:
PC = PC + 4
• PC+4 = byte address of next instruction
– If we do take the branch:
PC = (PC + 4) + (immediate * 4)
• Observations
– Immediate field specifies the number of words to jump, which is
simply the number of instructions to jump
– Immediate field can be positive or negative
– Due to hardware, add immediate to (PC+4), not to PC; will be
clearer why later in course
 Branch Example
• MIPS Code:
– Loop: beq $9,$0,End
add $8,$8,$10
addi $9,$9,-1
j Loop
End:
• Encoding in I-Format:
– opcode = 4 (look up in table)
– rs = 9 (first operand)
– rt = 0 (second operand)
– immediate field: no. of instructions to add to (or subtract from)
the PC, starting at the instruction following the branch
• Here, immediate = 3
 Branch Example
• MIPS Code:
– Loop: beq $9,$0,End
add $8,$8,$10
addi $9,$9,-1
j Loop
End:

• Decimal representation
4 9 0 3
• Binary representation
000100 01001 00000 0000000000000011
 Outline
• Introduction to assembly language
• MIPS instruction set architecture
– MIPS basic instructions
• Arithmetic instructions: add, addi, sub
• Data transfer instructions: lw, sw, lb, sb
• Control instructions: bne, beq, j, slt, slti
• Logical operations: and, andi, or, ori, nor, sll, srl
– MIPS instruction format
• R-format
• I-format
• J-format
– Encoding/decoding assembly code
 J-Format Instructions
• J-format is used by MIPS jump instructions
– j and jal
– 6-bit opcode + 26-bit jump address

6 bits 26 bits
opcode
• Key concepts target address
– Keep opcode field identical to R-format and I-format for
consistency
– Combine all other fields to make room for large target
address
• Goto statements and function calls tend to have larger offsets than
branches and loops
 J-Format Addressing
• We have 26 bit to specify the target address
– We cannot fit both a 6-bit opcode and a 32-bit address into a single 32-
bit word, so we compromise
– Like branches, jumps will only jump to word aligned addresses  the
26-bit field covers 28 bits of the 32-bit address space
• Where do we get the other 4 bits?
– Take the 4 highest order bits from the PC
– Technically, this means that we cannot jump to anywhere in memory,
but it’s adequate 99.9999…% of the time, since programs aren’t that
long
• Only if straddle a 256 MB boundary
– If we absolutely need to specify a 32-bit address, we can always put it in
a register and use the jr instruction
 J-Format Addressing
• Target address calculation
– New PC = { PC[31..28], target address, 00 }
– Understand where each part came from!

– Note: { , , } means concatenation

{ 4 bits , 26 bits , 2 bits } = 32 bit address
– { 1010, 11111111111111111111111111, 00 }
= 10101111111111111111111111111100
 MIPS Instruction Formats
Summary
• Minimum number of instructions required
– Information flow: load/store
– Logic operations: logic and/or/nor, shift
– Arithmetic operations: addition, subtraction, etc.
– Branch operations: bne, beq
– Jump operations: j, jal
• Instructions have different number of operands
• 32 bits representing a single instruction

Name Fields Comments

Field size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits All MIPS instructions 32 bits
R-format op rs rt rd shamt funct Arithmetic instruction format
I-format op rs rt address/immediate Transfer, branch, imm. format
J-format op target address Jump instruction format
 MIPS Addressing Modes
• Register addressing (R-Type)
– Operand is stored in a register
• Base or displacement addressing (I-Type)
– Operand at the memory location specified by a register
value plus a displacement given in the instruction; Eg: lw,
$t0, 25($s0)
• Immediate addressing (I-Type)
– Operand is a constant within the instruction itself
• PC-relative addressing (I-Type)
– The address is the sum of the PC and a constant in the
instruction
• Pseudo-direct addressing (J-type)
– New PC = {(upper 4 bits of PC+4), 26-bit constant, 00}
 Decoding Machine Language
• How do we convert 1s and 0s to C code?
– Machine language  Assembly language  C?
• For each 32 bits:
– Look at opcode: 0 means R-Format, 2 or 3 mean J-
Format, otherwise I-Format
– Use instruction type to determine which fields exist
– Write out MIPS assembly code, converting each field
to name, register number/name, or decimal/hex
number
– Logically convert this MIPS code into valid C code
 Decoding Example (1/5)
• Here are six machine language instructions in
hexadecimal:
00001025hex
0005402Ahex
11000003hex
00441020hex
20A5FFFFhex
08100001hex
– Let the first instruction be at address 4,194,304ten
(0x00400000hex)
• Next step: convert hex to binary
 Decoding Example (2/5)
• The six machine language instructions in binary:
R 00000000000000000001000000100101
R 00000000000001010100000000101010
I 00010001000000000000000000000011
R 00000000010001000001000000100000
I 00100000101001011111111111111111
J 00001000000100000000000000000001

•R Next0step: identify
rs opcode
rt and
rd format
shamt funct
I 1, 4-31 rs rt immediate
J 2 or 3 target address
 Decoding Example (3/5)
• Next: fields separated based on format /
R opcode:
0 0 0 2 0 37
R 0 0 5 8 0 42
I 4 8 0 +3
R 0 2 4 2 0 32
I 8 5 5 -1
J 2 1,048,577

• Next step: translate (disassemble) to MIPS

instructions
 Decoding Example (4/5)
• MIPS assembly (Part 1):
Address Assembly instructions
0x00400000 or $2,$0,$0 0x00400004
slt $8,$0,$5 0x00400008 beq
$8,$0,3 0x0040000c add $2,$2,$4
0x00400010 addi $5,$5,-1
0x00400014 j 0x100001

• Better solution: translate to more meaningful MIPS

instruction (fix the branch/jump, add labels and
register names)
 Decoding Example (5/5)
• MIPS Assembly (Part 2):
or $v0,$0,$0
Loop: slt $t0,$0,$a1
beq $t0,$0,Exit
add $v0,$v0,$a0
addi $a1,$a1,-1
j Loop
Exit:
• Next step: translate to C code (be creative!)
product = 0; $v0: product
while (multiplier > 0) { $a0: multiplicand
product += multiplicand; $a1: multiplier
multiplier -= 1;
}
 Revisit: lui
• Example of lui
addi $t0,$t0, 0xABABCDCD

lui $at, 0xABAB
ori $at, $at, 0xCDCD
add $t0,$t0,$at
• Wouldn’t it be nice if the translation can be
done automatically?
– If number too big, then just automatically replace
addi with a sequence of lui, ori, add
 Pseudoinstructions
• We introduce pseudoinstruction
– A MIPS instruction that doesn’t turn directly into a machine
language instruction, but into other MIPS instructions
– Previous example: addi with a large immediate is
considered as a pseudoinstruction
• The compiler / assembly programmer can write code
with pseudoinstructions
– Assembler is responsible to break one pseudoinstruction
into several “real” MIPS instructions
• Instructions implemented by hardware
– This makes assembly programming much easier
 Example Pseudoinstructions
• Register move
– Format: move reg2,reg1
– Equivalent to: add reg2,$zero,reg1
• Load immediate
– Format: li reg,value
– If value fits in 16 bits: addi reg,$zero,value
– Otherwise: lui reg, upper 16 bits of value
ori reg,$zero,lower 16 bits
• Easy addition
– addu reg,reg,value # should be addiu
– If value fits in 16 bits: addiu reg,reg,value
– Otherwise: lui $at,upper 16 bits of value
ori $at,$at,lower 16 bits
addu reg,reg,$at
 Pseudoinstruction Translation
• Problem:
– When breaking up a pseudoinstruction, the
assembler may need to use an extra register
– If it uses any regular register, it’ll overwrite
whatever the program has put into it
• Solution:
– Reserve a register ($1, called $at for “assembler
temporary”) that assembler will use to break up
pseudo-instructions
– Since the assembler may use this at any time,
it’s not safe to code with it
 Summary
• Introduction of assembly language
• MIPS instruction set architecture
– MIPS basic instructions
• Arithmetic instructions: add, addi, sub
• Data transfer instructions: lw, sw, lb, sb
• Control instructions: bne, beq, j, slt, slti
• Logical operations: and, andi, or, ori, nor, sll, srl
– MIPS instruction format
• R-format, I-format, J-format
– Encoding/decoding assembly code
• Disassembly starts with opcode
• Pseduoinstructions are introduced
 Summary
• Important principles in ISA and hardware
design
– Simplicity favors regularity
– Smaller is faster
– Make the common case fast
– Good design demands good compromises
– Stored program concept: instructions are
represented as numbers and stored in
memory