Course: Electronic Devices
Chapter-7: FET Biasing (JFET)
Reference book: Electronic Devices and
Circuit Theory
Robert L. Boylestad and L. Nashelsky , (11th Edition)
OBJECTIVES
• Be able to perform a dc analysis of JFET, MOSFET, and MESFET networks.
• Become proficient in the use of load-line analysis to examine FET networks.
• Develop confidence in the dc analysis of networks with both FETs and BJTs.
• Understand how to use the Universal JFET Bias Curve to analyze the various
FET configurations.
The source of these information is Ref. book (11th Edition). 2
GENERAL RELATIONSHIPS
• For all FETs: I G 0 A I D I S
VGS 2
• For JFETs and Depletion-Type MOSFETs: ID IDSS (1 )
VP
2
• For Enhancement-Type MOSFETs: I D k (VGS VT )
• BJT: Linear Relationship between IB and IC
• FET: Non-linear Relationship between VGS and ID.
The source of these information is Ref. book (11th Edition). 3
COMMON FET BIASING CIRCUITS
• JFET
• Fixed – Bias
• Self-Bias
• Voltage-Divider Bias
• Depletion-Type MOSFET
• Self-Bias
• Voltage-Divider Bias
• Enhancement-Type MOSFET
• Feedback Configuration
• Voltage-Divider Bias
The source of these information is Ref. book (11th Edition). 4
FIXED-BIAS JFET
• The simplest biasing arrangements:
I G 0 A I D I S
VGS 2
ID IDSS (1 )
VP
• For the DC analysis,
• Capacitors are open circuits
I G 0 A V RG I G RG (0 A) RG 0V
• The zero-volt drop across RG permits
replacing RG by a short-circuit.
The source of these information is Ref. book (11th Edition). 5
FIXED-BIAS JFET
• Can be solved using either Mathematical Approach or Graphical Approach:
Mathematical Approach Graphical Approach
VGS VGG
VDS VDD I D RD
VS 0
VD VDS
VG VGS
VGS 2
I D I DSS (1 )
VP
The source of these information is Ref. book (11th Edition). 6
FIXED-BIAS JFET EXAMPLE
• Determine VGSQ, IDQ, VDS, VD, VG, VS.
The source of these information is Ref. book (11th Edition). 7
FIXED-BIAS JFET EXAMPLE
Graphical Approach
VGS ID
0 IDSS
0.3VP IDSS/2
0.5VP IDSS/4
VP 0mA
The source of these information is Ref. book (11th Edition). 8
JFET: SELF-BIAS CONFIGURATION
• The self-bias configuration eliminates the need for two dc supplies.
I G 0 A
I D I S
VGS 2
ID IDSS (1 )
VP
The source of these information is Ref. book (11th Edition). 9
SELF-BIAS CONFIGURATION
• Can be solved using either Mathematical Approach or Graphical Approach:
VGS I D RS
VDS VDD I D ( RS RD )
2
VGS
ID I DSS 1
VP
2
I D RS
ID I DSS 1
VP
The source of these information is Ref. book (11th Edition). 10
SELF-BIAS CONFIGURATION
Graphical Approach
• Draw the device transfer characteristic using shorthand method.
• Draw the network load line
• Use VGS I D RS to draw straight line.
• First point, I D 0, VGS 0
• Second point, any point from ID = 0 to ID = IDSS. Choose
I DSS
ID then
2
I R
VGS DSS S
2
• The Q-point obtained at the intersection of the straight line plot and the device
characteristic curve.
• The quiescent value for ID and VGS can then be determined and used to find the
other quantities of interest.
The source of these information is Ref. book (11th Edition). 11
SELF-BIAS CONFIGURATION
The source of these information is Ref. book (11th Edition). 12
SELF-BIAS EXAMPLE
• Determine VGSQ, IDQ,VDS,VS,VG and VD.
VGS I D RS
VDS VDD I D ( RS RD )
The source of these information is Ref. book (11th Edition). 13
SELF-BIAS EXAMPLE Contd.
• Plot ID vs VGS and draw a line from the origin of the axis.
The source of these information is Ref. book (11th Edition). 14
SELF-BIAS EXAMPLE Contd.
• Plot the transfer curve using IDSS and VP using shorthand method:
VGS ID
0 IDSS
0.3VP IDSS/2
0.5VP IDSS/4
VP 0mA
The source of these information is Ref. book (11th Edition). 15
SELF-BIAS EXAMPLE Contd.
• Superimpose the load line on top of the transfer curve:
The source of these information is Ref. book (11th Edition). 16
JFET: VOLTAGE-DIVIDER BIAS
• The source VDD was separated into two equivalent sources to permit a further
separation of the input and output regions of the network.
• Since IG = 0A, Kirchoff’s current law requires that IR1= IR2 and the series
equivalent circuit appearing to the left of the figure can be used to find the
level of VG.
The source of these information is Ref. book (11th Edition). 17
VOLTAGE-DIVIDER BIAS
• VG can be found using the voltage divider rule:
R2VDD
VG
R1 R2
• Using Kirchoff’s Law on the output loop:
V D V DD I D R D VDS VDD I D ( RD RS )
VS I D RS VGS VG I D RS
• Rearranging and using ID =IS:
V DD
I R1 I R 2
R1 R2
• Again the Q point needs to be established
by plotting a line that intersects the
The source of these information is Ref. book (11th Edition). 18
transfer curve.
VOLTAGE-DIVIDER BIAS
• Graphical Approach ( to find VGSQ and IDQ):
• Plot a line for:
• VGS = VG when ID = 0A
• ID = VG/RS when VGS = 0V.
• Plot the transfer curve using IDSS and VP using shorthand method.
• The Q-point is located at the intersection.
VGS VG I D RS
VGS ID
0 IDSS
0.3VP IDSS/2
0.5VP IDSS/4
VP 0mA
The source of these information is Ref. book (11th Edition). 19
EFFECT OF INCREASING VALUES OF RS
The source of these information is Ref. book (11th Edition). 20
JFET: VOLTAGE-DIVIDER BIAS EXAMPLE
• Determine IDQ, VGSQ, VD, VS, VDS and VDG.
R2VDD
VG VGS VG I D RS
R1 R2
VDS VDD I D ( RD RS )
VGSQ 1.8V I DQ 2.4mA
VD 10.24V VS 3.6V
VDS 6.64V VDG 8.24V
The source of these information is Ref. book (11th Edition). 21
VOLTAGE-DIVIDER BIAS EXAMPLE Contd.
• Graphical Approach ( to find VGSQ and IDQ):
• Plot a line for:
• VGS = VG when ID = 0A
• VGS = 0V when ID = VG/RS.
• Plot the transfer curve using IDSS and VP
using shorthand method.
• Identify the Q-point.
R2VDD VS I D RS
VG
R1 R2
VDS VDD I D ( RD RS )
VGS VG I D RS
VDS VD VS
V D V DD I D R D
V V V
DGof these information
The source D G is Ref. book (11th Edition). 22
End Of Chapter 7 (JFET Part)
