System Software

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Outline
 Introduction
 System Software and Machine Architecture
 The Simplified Instructional Computer
(SIC)
 SIC Machine Architecture
 SIC/XE Machine Architecture
 SIC Programming Examples
 Traditional (CISC) Machines
 RISC Machines

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System Software: What It Consists Of
 System Software is not just one program, but
a collection of programs that manage and
support the computer's core operations

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System Software: What It Consists Of
 System Software is not just one program, but
a collection of programs that manage and
support the computer's core operations

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1.1 Introduction

 System Software consists of a variety of

programs that support the operation of a
computer.
 The programs implemented in either software
and (or) firmware that makes the computer
hardware usable.
 The software makes it possible for the users to
focus on an application or other problem to be
solved, without needing to know the details of
how the machine works internally.

 BIOS (Basic Input Output System)

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1.2 System Software and Machine
Architecture
 System Software vs Application
 One characteristic in which most system
software differs from application software is
machine dependency.
 System programs are intended to support the
operation and use of the computer itself, rather
than any particular application.
 Examples of system software
 Text editor, assembler, compiler, loader or
linker, debugger, macro processors, operating
system, database management systems,
software engineering tools, …

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1.2 System Software and Machine
Architecture

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1.2 System Software and Machine
Architecture
 Text editor
 To create and modify the program
 Compiler and assembler
 You translated these programs into machine
language
 Loader or linker
 The resulting machine program was loaded
into memory and prepared for execution
 Debugger
 To help detect errors in the program

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System Software Concept
Users

Application Program

Utility Program
Debugger Macro Processor Text Editor
(Library)

Compiler Assembler Load and Linker

OS
Memory Process Device Information
Management Management Management Management

Bare Machine (Computer)

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System Software and Machine Architecture
 Machine dependent
 Instruction Set, Instruction Format, Addressing
Mode, Assembly language …
 Machine independent
 General design logic/strategy, Two passes
assembler…

Machine independent
Machine Dependent

Computer

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1.3 The Simplified Instructional
Computer
 Like many other products, SIC comes in
two versions
 The standard model
 An XE version
 “extra equipments”, “extra expensive”
 The two versions has been designed to be
upward compatible
 SIC (Simplified Instructional Computer)
 SIC/XE (Extra Equipment)

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1.3 The Simplified Instructional
Computer
 SIC
 Upward compatible
 Memory consists of 8-bit bytes, 3 consecutive
bytes form a word (24 bits)
 There are a total of 32768 bytes (32 KB) ( 2 power
15) in the computer memory.
 5 registers, 24 bits in length ADDR 0, 1 → ADDR A, X
 A 0 Accumulator
 X 1 Index register "Take contents of
register 1 (X), add to
 L 2 Linkage register (JSUB)
register 0 (A), store
 PC 8 Program counter result in A."
 SW 9 Status word (Condition Code)
 The Linkage Register (L) is a special register that holds the address to
which control should return after a subroutine call. In the case of JSUB
(Jump to Subroutine)
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1.3.1 SIC Machine Architecture
 Data Formats
 Integers are stored as 24-bit binary number
 2’s complement representation for negative
values
 Characters are stored using 8-bit ASCII codes
 No floating-point hardware on the standard
version of SIC (There is no built-in hardware support for floating-point
arithmetic.)

 range of 0 to 224−12 24 −1 (i.e., from 0 to

16,777,215) in unsigned format.
 In 2's complement, the most significant bit
(MSB) is used as the sign bit. the MSB is 0 for
positive and 1 -ve
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Instruction Cycle
 CPU
 Control Unit (CU)
 Arithmetic and Logic Unit (ALU)
 Register
 Instruction Cycle
 Fetch Cycle
 Execution Cycle

Fetch Fetch
Decoder Computation Store Result
Instruction Operand

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1.3.1 SIC Machine Architecture
 Instruction format
 24-bit format
 The flag bit x is used to indicate indexed-
addressing mode 8 1 15
opcode x address

 Addressing Modes
 There are two addressing modes available
 Indicated by x bit in the instruction
 (X) represents the contents of reg. X

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1.3.1 SIC Machine Architecture
 Instruction set
 Format 3
 Load and store registers (LDA, LDX, STA, STX,
etc.)
 Integer arithmetic operations (ADD, SUB, MUL,
DIV)
 Compare instruction (COMP)
 Conditional jump instructions (JLT, JEQ, JGT)
 JSUB jumps to the subroutine, placing the
return address in register L.
 RSUB returns by jumping to the address
contained in register L.

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1.3.1 SIC Machine Architecture
 I/O
 I/O are performed by transferring 1 byte at a
time to or from the rightmost 8 bits of register
A.
 Each device is assigned a unique 8-bit code as
an operand.
 Test Device (TD): tests whether the addressed
device is ready to send or receive
 < ready = not ready
 Read Data (RD)
 Write Data (WD)

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1.3.2 SIC/XE Machine Architecture
 1 megabytes (1024 KB) (2 power 20) in
memory
 3 additional registers, 24 bits in length
 B 3 Base register; used for addressing
 S 4 General working register
 T 5 General working register
 1 additional register, 48 bits in length
 F 6 Floating-point accumulator
(48 bits)

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1.3.2 SIC/XE Machine Architecture
 Data format
 24-bit binary number for integer, 2’s complement for
negative values
 48-bit floating-point data type
 S - sign bit (0=positive, 1=negative)
 Fraction – a value between 0 and 1
 The exponent is between 0 and 2047
 If exponent is e and the fraction is f then the absolute
value of the number is represented as, f*2(e-1024)
 To represent value 0: set all bits to 0 (sign, exponent
and fraction)
1 11 36

S exponent fraction

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1.3.2 SIC/XE Machine Architecture
 Instruction formats
 Relative addressing - format 3 (e=0)
 Extend the address to 20 bits - format 4 (e=1)
 Don’t refer memory at all - formats 1 and 2

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 n – indirect addressing
 i- immediate addressing
 x – indexed addressing
 b – base relative addressing
 p – program counter relative addressing
 e – ( 0 – format 3, 1- format 4)
 If b and p are 0, then it is direct addressing
 If bits i and n are both 0or both 1 – simple
addressing
 Indexing cannot be used with immediate or indirect
addressing modes.

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SIC/XE supports flexible addressing modes using two key bits: n (indirect) and
i (immediate), and x, b, p, e bits for indexing, base-relative, PC-relative, and
extended formats.

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1.3.2 SIC/XE Machine Architecture
 Addressing modes
 n i x b p e
 Simple n=0, i=0 (SIC) or n=1, i=1
 Immediate n=0, i=1 TA=Valus
 Indirect n=1, i=0 TA=(Operand)
 Base relative b=1, p=0 TA=(B)+disp
0 <= disp <= 4095
 PC relative b=0, p=1 TA=(PC)+disp
-2048 <= disp <= 2047

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1.3.2 SIC/XE Machine Architecture
 Addressing mode
 Direct b=0, p=0 TA=disp
 Index x=1 TAnew=TAold+(X)
 Index+Base relative x=1, b=1, p=0

TA=(B)+disp+(X)
 Index+PC relative x=1, b=0, p=1
TA=(PC)
+disp+(X)
 Index+Direct x=1, b=0, p=0
 Format 4 e=1
 Appendix and Fig. 1.1 Example
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Figure 1.1

 Memory address
 00000
(0000 0000 0000 0000 0000)
 ~FFFFF (Byte)
(1111 1111 1111 1111 1111)

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1.3.2 SIC/XE Machine Architecture
 Instruction set
 Format 1, 2, 3, or 4
 Load and store registers (LDB, STB, etc.)
 Floating-point arithmetic operations (ADDF,
SUBF, MULF, DIVF)
 Register-to-register arithmetic operations
(ADDR, SUBR, MULR, DIVR)
 A special supervisor call instruction (SVC) is
provided
 I/O
 1 byte at a time, TD, RD, and WD
 SIO, TIO, and HIO are used to start, test, and
halt the operation of I/O channels.
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1.3.3 SIC Programming Examples
 Sample data movement operations
 No memory-to-memory move instructions (Fig.
1.2)
LDA five LDA #5
… …
five word 5

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1.3.3 SIC Programming Examples

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1.3.3 SIC Programming Examples
 Sample arithmetic operations
 (ALPHA+INCR-1) assign to BETA (Fig. 1.3)
 (GAMMA+INCR-1) assign to DELTA

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1.3.3 SIC Programming Examples

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1.3.3 SIC Programming Examples
 String copy

Load the character at STR1 + X into accumulator (register A).

Increment X, then compare it to the value at memory label ELEVEN.

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1.3.3 SIC Programming Examples

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1.3.3 SIC Programming Examples

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1.3.3 SIC Programming Examples

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1.3.3 SIC Programming Examples

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1.3.3 SIC Programming Examples

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1.3.3 SIC Programming Examples

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Traditional (CISC) Machines
 Complex Instruction Set Computers (CISC)
 complicated instruction set
 different instruction formats and lengths
 many different addressing modes
 e.g. VAX or PDP-11 from DEC
 e.g. Intel x86 family
 Reduced Instruction Set Computer (RISC)

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VAX Architecture (1/6)
 Virtual Address EXtension
 Memory
 All addresses are byte address
 word (2bytes), longword (4bytes),
 quadworad (8bytes), octaword (16bytes)
 All VAX programs operate in a virtual address space of 232 bytes
 One half is used for system space
 The other half is called process space, and is defined for
each program
 VAX Architecture (2/6)
 Registers
 16 general purpose registers: R0~R15
 each register is 32-bit long
 R15 (PC): Program Counter
 R14 (SP): Stack Pointer
 R13 (FP): Frame Pointer
 R12 (AP): Argument Pointer
 R6~R11: general
 R0~R5: are used by some instructions
 PSL: process status longword

The PSL holds key status and

control information about a
process or program currently
being executed
 VAX Architecture (3/6)

 Data Formats
» Integers: byte, word, longword, quadword, or octaword
» Negative integers: 2’s complement representation
» Floating-point: 4~16bytes
» packed decimal: (C:positive, D:negative, F:unsigned)
4 4 4 4 4 S

» zoned decimal: (digits are represented with ASCII codes)

0011 4 0011 4 S 4

– e.g. +53842, 53842C (packed), 35333834C2 (zoned)

– e.g. -6071, 6071D(packed), 363037D1
» numeric format: trailing numeric, leading separate numeric

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 4. Packed Decimal Stores two decimal digits per byte.
 Last nibble (4 bits) indicates sign:
 C → Positive D → Negative F → Unsigned
Examples:+53842 → 53842C
-6071 → 6071D
5. Zoned Decimal Each digit is stored as an ASCII character.
The last byte’s zone nibble stores the sign.
Examples:+53842 → 35333834C2 (53 38 42 in ASCII + sign nibble)
-6071 → 363037D1

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 VAX Architecture (4/6)

 Instruction Formats
» variable -length instruction format
 Addressing Modes Move Longword
» register mode MOVL R1, R2 Moves data directly between registers.
» register deferred modeMOVL (R1), R2 Uses the address in R1 to fetch
the data from memory.

» autoincrement and autodecrement modes MOVL (R1)+, R2

MOVL -(R1), R2
» several base relative addressing modes
» program-counter relative modes
» indirect addressing mode (called deferred modes)
» immediate operands

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 VAX Architecture (5/6)

 Instruction Set
» Goal: symmetric with respect to data type
» The instruction mnemonics are formed by
– a prefix that specifies the type of operation
– a suffix that specifies the data type of the operands
– a modifier that gives the number of operands involved
» e.g. ADDW2, MULL3, CVTWL
» A single instruction for
– saves a designated set of registers
– passes a list of arguments to the procedure
– maintains the stack, frame, and argument pointers
– sets a mask tomultiplying
enabletwoerror traps for arithmetic operations
Adds two 16-bit (word) values. 32-bit (longword) integers and storing the result in a
third location
Convert Word to Longword
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Component Description Example
Prefix Operation to perform ADD, MOV, CMP, MUL
B (Byte), W (Word), L
Suffix Data type (Long), F (Float), D
(Double float), G, H
Number of operands
Modifier (implicitly inferred from Usually 2 or 3 operands
the instruction form)

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 VAX Architecture (6/6)

 Input and Output

» I/O device controllers
» Each controller has a set of control/status and data
registers, which are assigned locations in the physical
address space (called I/O space)
» No special instructions are required to access registers in
I/O space
» The association of an address in I/O space with a physical
register in a device controller is handled by the memory
management routines

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I/O Device Controllers
An I/O device controller is a hardware component that
acts as an intermediary between the CPU and an I/O
device.
Each device controller:
• Manages control/status and data registers
• Is mapped to specific addresses in the physical
memory, also called the I/O space
• Responds to read/write operations from the CPU

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Registers in I/O Device Controllers
Each controller typically has:
1. Control Register – Used to send commands (like "start",
"read", "write") to the device.
2. Status Register – Used to check the status (like "busy",
"ready", "error") of the device.
3. Data Register – Used to read data from or write data to
the device.
 These registers are memory-mapped, meaning they are
assigned specific locations in the physical address
space (the I/O space).

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I/O Space and Memory Mapping
• I/O space is a region of physical memory reserved
for device communication.
• The CPU accesses I/O device registers as though it
were accessing regular memory addresses.
• This is called Memory-Mapped I/O (MMIO).

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 Pentium Pro Architecture (1/5)
 Memory
» physical level: byte addresses, word, doubleword
» logical level: segments and offsets
» In some cases, a segment can also be divided into pages
» The segment/offset address specified by the programmer is
translated into a physical address by the x86 MMU (Memory
Management Unit)

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 Pentium Pro Architecture (2/5)
 Registers
» General-purpose registers:EIGHT 32 BIT
– EAX, EBX, ECX, EDX: data manipulation
– ESI, EDI, EBP, ESP: address
» Special-purpose registers:
– EIP: next instruction
– FLAGS: status word
– CS: code segment register
– SS: stack segment register SIX 16-bit segment registers
– DS, ES, FS, and GS: data segments
» Floating-point unit (FPU)
» Registers reserved for system programs

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General-Purpose Registers
(GPRs)
Register Purpose
Accumulator – used in arithmetic,
EAX logic, and I/O operations. Often
holds return values.
Base register – can hold addresses
EBX
or data.
Counter – used in loops and
ECX shift/rotate instructions (like LOOP,
REP).
Data – used in
EDX division/multiplication (holds high-
order bits).
Source Index – often used for
ESI string and memory copy
operations.
Destination Index – used
EDI
alongside ESI in string operations.
Base Pointer – points to the base
EBP of the current stack frame (used in
function calls).
Stack Pointer – always points to
ESP
the top of the stack.

E prefix stands for "Extended" (32-bit). 61

 Special-Purpose Register

Register Purpose
Instruction Pointer – points to the
EIP next instruction to execute. Auto-
incremented after instruction fetch.
Status Register – contains
condition codes (e.g., Zero, Carry,
FLAGS
Overflow flags) and control flags
(e.g., Interrupt Enable).

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 Segment Registers
These are used in x86 real mode and protected mode memory models to implement segmented memory. They help define
the base addresses for different parts of memory.

Register Segment Controlled

Code Segment – base for
CS
instructions
Stack Segment – base for stack
SS
operations
Data Segment – default base for
DS
general data
Extra Segment – often used for
ES
string operations
General-purpose data segment –
FS used for thread-local storage or
special purposes
General-purpose data segment –
GS
platform- or OS-specific uses

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 Pentium Pro Architecture (3/5)
 Data Formats
» Integers:
– 8-, 16-, 32-bit binary numbers
– negative values: 2’s complement
– FPU can also handle 64-bit signed integers
– The least significant part of a numeric value is stored at the
lowest-numbered address (little-endian)
– binary coded decimal (BCD)
 unpacked: 0000____0000____0000____…...0000____
 packed: |____|____|____|____|____|____|…..|____|____|
» Floating-point data formats
– single-precision: 32 bits=24+7-bit exponent+sign bit
– double-precision: 64 bits=53+10-bit exponent+sign bit
– extended-precision: 80 bits=64+15-bit exponent+sign bit

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 Pentium Pro Architecture (4/5)
 Instruction Formats
» prefix (optional) containing flags that modify the operation of
instruction
– specify repetition count, segment register, etc.
» opcode (1 or 2 bytes)
» operands and addressing modes
 Addressing Modes
» TA=(base register)+(index register)*(scale factor)+displacement
» base register: any general-purpose registers
» index register: any general-purpose registers except ESP
» scale factor: 1, 2, 4, 8
» displacement: 8-, 16-, 32- bit value
» eight addressing modes

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An x86 instruction can consist of up to 6 components (not all are always
present):
1.Prefix (optional)
•Modifies the behavior of the instruction.
•Types of prefixes:
•Lock/Repeat prefixes: e.g., LOCK REP REPE REPNE
, , ,

•Segment override: e.g., ES: CS: SS: DS: FS: GS:

, , , , ,

•Operand-size override: changes operand size (16-bit ↔ 32-bit)

•Address-size override: changes address size (16-bit ↔ 32-bit)
2.Opcode (1 or 2 bytes)
•Specifies the actual operation (e.g., MOV ADD SUB
, , , etc.)

3.ModR/M byte (optional)

•Specifies the addressing mode, register, or memory involved.

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•SIB byte (optional)
•Scale-Index-Base byte (used in complex memory addressing)
•Displacement (optional)
•A constant value used in address calculation
•Immediate (optional)
•Constant value used directly in instruction

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Effective Address Calculation
Address in memory is computed using the formula:
TA = Base + (Index × Scale) + Displacement
•Base: A general-purpose register (e.g., EBX, ECX, etc.)
•Index: Any general-purpose register except ESP
•Scale: Multiplier (1, 2, 4, or 8)
•Displacement: A constant offset (8-, 16-, or 32-bit)
This is mainly used when SIB (Scale Index Base) byte is present.

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 Pentium Pro Architecture (5/5)
 Instruction Set R-REGISTER M-MEMORY
» 400 different machine instructions
– R-to-R instructions, R-to-M instructions, M-to-M instructions
– immediate values,
» special purpose instructions for high-level programming language
– entering and leaving procedures,
– checking subscript values against the bounds of an array
 Input and Output
» Input is performed by instructions that transfer one byte, word, or
doubleword from an I/O register EAX
» Repetition prefixes allow these instructions to transfer an entire
string in a single operation

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RISC Machines
 RISC system
 instruction
 standard, fixed instruction format
 single-cycle execution of most instructions
 memory access is available only for load and store
instruction
 other instructions are register-to-register operations
 a small number of machine instructions, and instruction
format
 a large number of general-purpose registers
 a small number of addressing modes
 Three RISC machines
 SPARC family
 PowerPC family
 Cray T3E
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Comparison of CISC and RISC

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