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UNIT-V
Behavioral Modeling
Structured Procedures, Procedural Assignments, Timing
control, Conditional statements, Sequential and Parallel
Blocks. Switch level Modelling, Introduction to tasks
and functions, Useful modelling Techniques, Procedural
continuous assignments, Overriding parameters,
Conditional compilation and execution, Introduction to
Logic Synthesis. Concept of Programming using FPGA
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Structured Procedures
• Structured Procedures: used in behavioral modelling
• There are two structured procedure statements in Verilog: always and
initial. These statements are the two most basic statements in
behavioral modeling. All other behavioral statements can appear only
inside these structured procedure statements.
• Verilog is a concurrent programming language unlike the C
programming language, which is sequential in nature. Activity flows in
Verilog run in parallel rather than in sequence.
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• Each always and initial statement represents a separate activity flow
in Verilog.
• Each activity flow starts at simulation time 0. The statements always
and initial cannot be nested.
• All statements inside an initial statement constitute an initial block.
An initial block starts at time 0, executes exactly once during a
simulation, and then does not execute again. If there are multiple
initial blocks, each block starts to execute concurrently at time 0. Each
block finishes execution independently of other blocks. Multiple
behavioral statements must be grouped, typically using the keywords
begin and end.
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Example of Initial block
• module Testing;
reg x,y, a,b, m;
initial
m = 1'b0; //single statement; does not need to be grouped
initial
begin
#5 a = 1'b1; //multiple statements; need to be grouped
#25 b = 1'b0;
end
initial
begin
#10 x = 1'b0;
#25 y = 1'b1;
end
initial
#50 $finish;
endmodule
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always statement
• All behavioral statements inside an always statement constitute an
always block. The always statement starts at time 0 and executes the
statements in the always block continuously in a looping fashion. This
statement is used to model a block of activity that is repeated
continuously in a digital circuit. An example is a clock generator
module that toggles the clock signal every half cycle.
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Procedural Assignments
• We have already seen that continuous assignment updates net, but
procedural assignment update values of reg, real, integer or time variable.
The constant part select, indexed part select and bit select are possible for
vector reg.
• There are two types of procedural assignments called blocking and non-
blocking. Blocking assignment, as the name says, gets executed in the order
statements are specified. The “=” is the symbol used for blocking assignment
representation. Non-blocking assignment allows scheduling of assignments.
It will not block the execution. The symbol “<=" is used for non-blocking
assignment representation and mainly used for concurrent data transfers.
Following example shows the differences in the simulation result by using
blocking and non-blocking assignments.
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Conditional statements
• module multiplexer4_1 ( din ,sel ,dout );
output dout ;
reg dout ;
input [3:0] din ;
wire [3:0] din ;
input [1:0] sel ;
wire [1:0] sel ;
always @ (din or sel) begin
if (sel==0)
dout = din[3];
else if (sel==1)
dout = din[2];
else if (sel==2)
dout = din[1];
else
dout = din[0];
end
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endmodule Hyd
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Sequential and Parallel Blocks
• The block statements are the grouping of two or more statements
together, which act syntactically like a single statement. There are two
types of blocks in the Verilog
• Sequential block
• Parallel block
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• Characteristics
• The sequential block has the following characteristics, such as:
Statements will be executed in the sequence, one after another.
• Delay values for each statement are treated relative to the simulation
time of the previous statement's execution.
• Control can pass out of the block after the last statement executes.
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Switch level Modelling
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CMOS NAND Gate
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Functions and tasks
• Tasks and functions are used to reduce code repetition. If in your
project you need to do something many times it is better to use a task
or a function that will reduce code writing and it will be more
readable
• Tasks can have any number of inputs and outputs
• The order of inputs/outputs to a task dictates how it should be wired
up when called
• Tasks can have time delay (posedge, # delay, etc)
• Tasks can call other tasks and functions
• Tasks can drive global variables external to the task
• Variables declared inside a task are local to that task
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• The task-enabling arguments (x, y, z) correspond to
the arguments (a, b, c) defined by the task.
Since a and b are inputs, values of x and y will be
placed in a and b respectively. Because c is declared as
an output and connected with z during invocation, the
sum will automatically be passed to the
variable z from c.
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module operation; task bitwise_oper;
parameter delay = 10; output [15:0] ab_and, ab_or,
reg [15:0] A, B; ab_xor; //outputs from the task
reg [15:0] AB_AND, AB_OR, input [15:0] a, b; //inputs to the
AB_XOR; task
always @(A or B) //whenever A or B begin
changes in value
#delay ab_and = a & b;
begin
//invoke the task bitwise_oper.
ab_or = a | b;
provide 2 input arguments A, B ab_xor = a ^ b;
//Expect 3 output arguments end
AB_AND, AB_OR, AB_XOR
endtask
bitwise_oper(AB_AND, AB_OR,
AB_XOR, A, B);
end endmodule
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• module operation;
• parameter delay = 10;
• reg [15:0] A, B;
• reg [15:0] AB_AND, AB_OR, AB_XOR;
• always @(A or B) //whenever A or B changes in value
• begin
• //invoke the task bitwise_oper. provide 2 input arguments A, B
• //Expect 3 output arguments AB_AND, AB_OR, AB_XOR
• bitwise_oper(AB_AND, AB_OR, AB_XOR, A, B);
• end
• task bitwise_oper;
• output [15:0] ab_and, ab_or, ab_xor; //outputs from the task
• input [15:0] a, b; //inputs to the task
• begin
• #delay ab_and = a & b;
• ab_or = a | b;
• ab_xor = a ^ b;
• end
• endtask
•
• endmodule
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Function rules
•A function cannot contain any time-controlled statements
like #, @, wait, posedge, negedge
•A function cannot start a task because it may consume simulation time, but can call
other functions
•A function should have atleast one input
•A function cannot have non-blocking assignments or force-
release or assign-deassign
•A function cannot have any triggers
•A function cannot have an output or inout
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Procedural Assignments
• We have already seen that continuous assignment updates net, but
procedural assignment update values of reg, real, integer or time variable.
The constant part select, indexed part select and bit select are possible for
vector reg.
• There are two types of procedural assignments called blocking and non-
blocking. Blocking assignment, as the name says, gets executed in the order
statements are specified. The “=” is the symbol used for blocking assignment
representation. Non-blocking assignment allows scheduling of assignments.
It will not block the execution. The symbol “<=" is used for non-blocking
assignment representation and mainly used for concurrent data transfers.
Following example shows the differences in the simulation result by using
blocking and non-blocking assignments.
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Conditional compilation and
execution
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UNIT-III
• Sequential Logic Design
Sequential Logic Design: Latches, Flipflops, Difference
between latch and flipflop, types of flipflops like S-R, D,
T, JK and Master-Slave JK Flip Flop, Flip flop conversions,
setup and hold times, Ripple and Synchronous counters,
Shift registers, Finite state machines, Design of
synchronous FSM, Algorithmic State Machines charts.
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Finite state machines(FSM)
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Mealy State machine
A Finite State Machine is said to be Mealy state machine, if outputs depend on both present
inputs & present states.
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Example of Mealy State machine
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Moore state machine
• A Finite State Machine is said to be Moore state machine, if outputs
depend only on present states.
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Example of Moore State machine
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Synchronous counter
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4 bit synchronous Up counter using
T flip flop
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3 bit synchronous down counter
using T flip flop
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• Increasing the delay of flip-flop
• The propagation delay (delta t) should be made greater than the duration of the
clock pulse (T). But it is not a good solution as increasing the delay will decrease
the speed of the system.
• Use of edge-triggered flip-flop
• If the clock is High for a time interval less than the propagation delay of the flip
flop then racing around condition can be eliminated. This is done by using the
edge-triggered flip flop rather than using the level-triggered flip-flop.
• Use of master-slave JK flip-flop
• If the flip flop is made to toggle over one clock period then racing around
condition can be eliminated. This is done by using Master-Slave JK flip-flop.
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How Can We Eliminate Race Around
Condition?
There are three ways using which we can
eliminate the race around condition in JK flip
flop, which are discussed below:
1.Race around condition exists when tp ≥ Δt.
Thus, by keeping tp < Δt, we can avoid race
around condition.
2.Use of edge triggering in flip flops.
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