Unit -1-Microprocessor

 Architecture of 8086
Segmented memory
Addressing modes
Instruction set
Minimum and Maximum mode of
operations
 INTRODUCTION TO MICROPROCESSOR:
OVERVIEW OF A SIMPLE MICRO COMPUTER:
The major parts are the central processing unit or CPU, memory, and
the input and output devices or I/O. Connecting these parts together
are three sets of parallel lines called buses. The three buses are the
address bus, the data bus, and the control bus.

i)MEMORY: The memory consists of RAM and ROM. It may also have
magnetic floppy disks, magnetic hard disks, or laser optical disks.
Memory has two purposes. The first purpose is to store the binary codes
for the sequence of instructions you want the computer to carry out.
When you write a computer program, what you are really doing is just
writing a sequential list of instructions for the computer. The second
purpose of the memory is to store the binary-coded data with which the
 i)INPUT/OUTPUT: The input/output or I/O section allows the
computer to take in data from the outside world or send data to the
outside world. These allow the user and the computer to communicate
with each other. The actual physical devices used to interface the
computer buses to external systems are often called ports.

ii)CPU: The central processing unit or CPU controls the operation

of the computer. It fetches binary-coded instruction of the computer. It
fetches binary-coded instructions from memory, decodes the instructions
into a series of simple actions, and carries out these actions. The CPU
contains an arithmetic logic unit, or ALU. Which can perform add,
subtract, OR, AND, invert, or exclusive-OR operations on binary words
when instructed to do so. The CPU also contains an address counter
which is used to hold the address of the next instruction or data to be
fetched from memory, general-purpose registers which are used for
temporary storage of binary data, and circuitry which generates the
control bus signals.
 iv)ADDRESS BUS: The address bus consists of 16, 20, 24, or more
parallel signal lines. On these lines the CPU sends out the address of
the memory location that is to be written to or read from. The number
of address lines determines the number of memory locations that the
CPU can address. If the CPU has N address lines then it can directly
address 2N memory locations.

v)DATA BUS: The data bus consists of 8, 16, 32 or more parallel

signal lines. As indicated by the double-ended arrows on the data bus
line, the data bus lines are bi-directional. This means that the CPU can
read data in on these lines from memory or from a port as well as send
data out on these lines to memory location or to a port. Many devices in
a system will have their outputs connected to the data bus, but the
outputs of only one device at a time will be enabled.

vi)CONTROL BUS: The control bus consists of 4-10 parallel signal

lines. The CPU sends out signals on the control bus to enable the
outputs of addressed memory devices or port devices. Typical control
bus signals are memory read, memory write, I/O read, and I/O writer.
To read a byte of data from a memory location, for example, the CPU
sends out the address of the desired byte on the address bus and then
sends out a memory read signal on the control bus.
What is a Microprocessor?
• The word comes from the combination micro and processor.
Processor means a device that processes numbers, specifically binary numbers,
0’s and 1’s.
– Micro is a new addition.
– In the late 1960’s, processors were built using discrete elements.
– These devices performed the required operation, but were too large and too
slow.
– In the early 1970’s the microchip was invented. All of the components that
made up the processor were now placed on a single piece of silicon. The
size became several thousand times smaller and the speed became
several hundred times faster.
– The
Definition of“Micro” Processor was born.
Microprocessor:
 Microprocessor is a multipurpose, programmable device that accepts
digital data as input, processes it according to instructions stored in its
memory, and provides results as output.
or
 A microprocessor is a multipurpose, programmable, clock-driven, register-
based electronic device that reads binary instructions from a storage device
called memory accepts binary data as input and processes data according to
instructions, and provides result as output.
Processor No. of bits Clock speed (Hz) Year of introduction

4004 4 740K 1971

8008 8 500K 1972
8080 8 2M 1974
8085 8 3M 1976
8086 16 5, 8 or 10M 1978
8088 16 5, 8 or 10M 1979
80186 16 6M 1982
80286 16 8M 1982
80386 32 16 to 33M 1986
80486 32 16 to 100M 1989
Pentium 32 66M 1993
Pentium II 32 233 to 500M 1997
Pentium III 32 500M to 1.4G 1999
Pentium IV 32 1.3 to 3.8G 2000
Dual core 32 1.2 to 3 G 2006
Core 2 Duo 64 1.2 to 3G 2006

i3, i5 and i7 64 2.4G to 3.6G 2010

8086 Microprocessor features:
• It is 16-bit microprocessor
• It has a 16-bit data bus, so it can read data from or write data to
memory and ports either 16-bit or 8-bit at a time.
• It has 20 bit address bus and can access up to 220 memory
locations (1 MB).
• It can support up to 64K I/O ports
• It provides 14, 16-bit registers
• It has multiplexed address and data bus AD0-AD15 & A16-A19
• It requires single phase clock with 33% duty cycle to provide internal
timing.
• Prefetches up to 6 instruction bytes from memory and queues them in
order to speed up the processing.
• 8086 supports 2 modes of operation
• Minimum mode
Architecture of 8086 microprocessor:
• Maximum mode
 As shown in the below figure, the 8086 CPU is divided into two independent
functional parts
o Bus Interface Unit(BIU)
o Execution Unit(EU)
 Dividing the work between these two units’ speeds up processing.
The Execution Unit (EU):

 The execution unit of the 8086 tells the BIU where to fetch instructions or
data from, decodes instructions, and executes instructions.
 The EU contains control circuitry, which directs internal operations.
 A decoder in the EU translates instructions fetched from memory into a
series of actions, which the EU carries out.
 The EU has a 16-bit arithmetic logic unit (ALU) which can add, subtract,
AND, OR, XOR, increment, decrement, complement or shift binary numbers.
 The main functions of EU are:
o Decoding of Instructions
o Execution of instructions
 Steps
 EU extracts instructions from top of queue in BIU
 Decode the instructions
 Generates operands if necessary
 Passes operands to BIU & requests it to perform read or write bus
cycles to memory or I/O
 Perform the operation specified by the instruction on operands

Bus Interface Unit (BIU):

 The BIU sends out addresses, fetches instructions from memory, reads
data from ports and memory, and writes data to ports and memory.
 In simple words, the BIU handles all transfers of data and addresses on
the buses for the execution unit.

8086 HAS PIPELINING ARCHITECTURE:

 While the EU is decoding an instruction or executing an instruction,
which does not require use of the buses, the BIU fetches up to six
instruction bytes for the following instructions.
 The BIU stores these pre-fetched bytes in a first-in-first-out register set
called a queue.
 When the EU is ready for its next instruction from the queue in the
BIU. This is much faster than sending out an address to the system
memory and waiting for memory to send back the next instruction
byte or bytes.
 Except in the case of JMP and CALL instructions, where the queue
must be dumped and then reloaded starting
from a new address, this pre-fetch and queue scheme greatly speeds
up processing.
 Fetching the next instruction while the current instruction executes is
called pipelining.
Register organization:
 8086 has a powerful set of registers known as general purpose
registers and special purpose registers.
 All of them are 16-bit registers.
 General purpose registers:
o These registers can be used as either 8-bit registers or 16-bit
registers.
o They may be either used for holding data, variables and
intermediate results temporarily or for other purposes like a
counter or for storing offset address for some particular
addressing modes etc.
 Special purpose registers:
o These registers are used as segment registers, pointers, index
registers or as offset storage registers for particular addressing
modes.
 The 8086 registers are classified into the following types:
o General Data Registers
o Segment Registers
o Pointers and Index Registers
o Flag Register
General Data Registers:
 The registers AX, BX, CX and DX are the general purpose 16-bit registers.
 AX is used as 16-bit accumulator. The lower 8-bit is designated as AL and higher
8-bit is designated as AH. AL can be used as an 8-bit accumulator for 8-bit
operation.
 All data register can be used as either 16 bit or 8 bit. BX is a 16 bit register, but BL
indicates the lower 8-bit of BX and BH indicates the higher 8-bit of BX.
 The register BX is used as offset storage for forming physical address in case of
certain addressing modes.
 The register CX is used default counter in case of string and loop instructions.
 DX register is a general purpose register which may be used as an implicit
operand or destination in case of a few instructions. Page 13
Segment Registers:
There are 4 segment registers. They are:
o Code Segment Register(CS)
o Data Segment Register(DS)
o Extra Segment Register(ES)
o Stack Segment Register(SS)
 The 8086 architecture uses the concept of
segmented memory. 8086 able to address a
memory capacity of 1 megabyte and it is byte
organized. This 1 megabyte memory is divided into 16
logical segments. Each segment contains 64 kbytes of
memory.
 Code segment register (CS): is used for addressing
memory location in the code segment of the memory,
where the executable program is stored.
 Data segment register (DS): points to the data
segment of the memory where the data is stored.
 Extra Segment Register (ES) : also refers to a segment
in the memory which is another data segment in the
memory.
 Stack Segment Register (SS): is used for addressing
stack segment of the memory. The stack segment is
that segment of memory which is used to store stack
data.
 While addressing any location in the memory bank, the
physical address is calculated from two parts:
Physical address= segment address + offset
address
 The first is segment address, the segment registers
Pointers and Index Registers:
 The index and pointer registers are given below:

IP—Instruction pointer-store memory location of next instruction to be

executed
o BP—Base pointer
o SP—Stack pointer
o SI—Source index
o DI—Destination index
 The pointers registers contain offset within the particular segments.
o The pointer register IP contains offset within the code segment.
o The pointer register BP contains offset within the data segment.
o Thee pointer register SP contains offset within the stack
segment.
 The index registers are used as general purpose registers as well
as for offset storage in case of indexed, base indexed and relative
base indexed addressing modes.
 The register SI is used to store the offset of source data in data
segment.
 The register DI is used to store the offset of destination in data or
extra segment.
 The index registers are particularly useful for string manipulation.
8086 flag register and its functions:
 The 8086 flag register contents indicate the results of
computation in the ALU. It also contains some flag bits to
control the CPU operations.
 A 16 bit flag register is used in 8086. It is divided into two
parts .
o Condition code or status flags
o Machine control flags
 The condition code flag register is the lower byte of the
16-bit flag register. The condition code flag register is identical
to 8085 flag register, with an additional overflow flag.
 The control flag register is the higher byte of the flag register. It
contains three flags namely direction flag (D), interrupt flag (I) and trap
flag (T).

Flag register configuration

The description of each flag bit is as follows:

SF- Sign Flag: This flag is set, when the result of any computation
is negative. For signed computations the sign flag equals the MSB
of the result.

ZF- Zero Flag: This flag is set, if the result of the computation or
comparison performed by the previous instruction is zero.

PF- Parity Flag: This flag is set to 1, if the lower byte of the result
contains even number of 1’s.

CF- Carry Flag: This flag is set, when there is a carry out of MSB in
case of addition or a borrow in case of subtraction.

AF-Auxilary Carry Flag: This is set, if there is a carry from the lowest
nibble, i.e, bit three during addition, or borrow for the lowest
nibble, i.e, bit three, during subtraction.

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OF- Over flow Flag: This flag is set, if an overflow occurs, i.e, if the
result of a signed operation is large enough to accommodate in a
destination register. The result is of more than 7-bits in size in
case of 8-bit signed operation and more than 15-bits in size in
case of 16-bit sign operations, and then the overflow will be set.

TF- Tarp Flag: If this flag is set, the processor enters the single
step execution mode. The processor executes the current
instruction and the control is transferred to the Trap interrupt
service routine.

IF- Interrupt Flag: If this flag is set, the mask able interrupts
are recognized by the CPU, otherwise they are ignored.

D- Direction Flag: This is used by string manipulation instructions. If

this flag bit is ‘0’, the string is processed beginning from the lowest
address to the highest address, i.e., auto incrementing mode.
Otherwise, the string is processed from the highest address
towards the lowest address, i.e., auto decrementing mode.
Memory Segmentation:
 The memory in an 8086 based system is organized as segmented memory.
 The CPU 8086 is able to access 1MB of physical memory. The complete 1MB of
memory can be divided into 4 segments, each of 64KB size and is addressed by
one of the segment register.
 The 16-bit contents of the segment register actually point to the starting location
of a particular segment. The address of the segments may be assigned as 0000H
to F000h respectively.
 To address a specific memory location within a segment, we need an offset
address. The offset address values are from 0000H to FFFFH so that the physical
addresses range from 00000H to FFFFFH.

Physical address is calculated as below: Ex:

Segment address ------- 1005H Offset address ----------
 5555H
Segment address ------- 1005H ----- 0001 0000 0000
0101
Shifted left by 4 Positions------ 0001 0000 0000 0101
0000
+
 The main advantages of the segmented memory scheme are as follows:
1. Allows the memory capacity to be 1MB although the actual addresses to be handled
are of 16-bit size.
2. Allows the placing of code, data and stack portions of the same program in different
parts (segments) of memory, for data and code protection.
3. Permits a program and/or its data to be put into different areas of memory each
time the program is executed, i.e., provision for relocation is done.
Overlapping and Non-overlapping Memory segments:
 In the overlapping area locations physical address = CS1+IP1 = CS2+IP2.
Where ‘+’ indicates the procedure of physical address formation.
Addressing modes of 8086:
 Addressing mode indicates a way of locating data or operands.
 The addressing modes describe the types of operands and the way
they are accessed for executing an instruction.
 According to the flow of instruction execution, the instructions may be
categorized as the control transfer instructions, on the other hand,
transfer control to some predefined address or the address somehow
specified in the instruction, after their execution. For example, INT,
CALL, RET and JUMP instructions fall under this category.

The different ways in which a source operand is denoted in an instruction is

known as addressing modes.
•There are 8 different addressing modes in 8086 assembly programming −
ADDRESSING MODES OF 8086
1.Immediate
2.Direct
3.Register
4.Register Indirect
5.Indexed
6.Register Relative
7.Based Indexed
8.Relative Based Indexed
 The addressing modes for sequential control transfer instructions are:
1.Immediate: In this type of addressing, immediate data is a part of instruction and
appears in the form of successive byte or bytes.
Ex: MOV AX, 0005H-here, 0005H is the immediate data. The immediate data may be 8-
bit or 16-bit in size.

2.Direct: In the direct addressing mode a 16-bit memory address (offset) is directly
specified in the instruction as a part of it.

Ex: MOV AX, [5000H]

Here, data resides in a memory location in the data segment, whose effective address
may be completed using 5000H as the offset address and content of DS as segment
address. The effective address here, is 10H * DS + 5000H.

3.Register: In register addressing mode, the data is stored in a register and is referred
using the particular register. All the registers, except IP, may be used in this mode. Ex:
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MOV BX, AX
 Sequential control flow instructions and Control transfer
instructions
Sequential control flow instructions are the instructions,
which after execution, transfer control to the next instruction
appearing immediately after it (in the sequence) in the program. For
example, the arithmetic, logic, data transfer and processor control
instructions are sequential control flow instructions.

4.Register Indirect: Sometimes, the address of the memory location,

which contains data or operand, is determined in an indirect way, using the
offset register. This mode of addressing is known as register indirect
mode. In this addressing mode, the offset address of data is in either BX or
SI or DI register. The default segment is either DS or ES. The data is
supposed to be available at the address pointed to by the content of any of
the above registers in the default data segment.
Ex: MOV AX, [BX]
Here, data is present in a memory location in DS whose offset address
is in BX. The effective address of the data is given as 10H * DS+[BX].
 5.Indexed: In this addressing mode, offset of the operand is
stored in one of the index registers. DS and ES are the default
segments for index registers, SI and DI respectively. This is a
special case of register indirect addressing mode.
Ex: MOV AX, [SI]
Here, data is available at an offset address stored in SI in DS.
The effective address, in this case, is computed as 10*DS+[SI].
6.Register Relative: In this addressing mode, the data is
available at an effective address formed by adding an 8-bit or 16-
bit displacement with the content of any one of the registers BX,
BP, SI and DI in the default (either DS or ES) segment. Ex: MOV
AX, 50H[BX]
Here, the effective address is given as 10H *DS+50H+[BX]

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 7.Based Indexed: The effective address of data is formed, in this
addressing mode, by adding content of a base register (any one of BX or
BP) to the content of an index register (any one of SI or DI). The default
segment register may be ES or DS.
Ex: MOV AX, [BX][SI]
Here, BX is the base register and SI is the index register the effective address
is computed as 10H * DS + [BX] + [SI].

8. Relative Based Indexed: The effective address is formed by adding an 8

or 16-bit displacement with the sum of the contents of any one of the base
register (BX or BP) and any one of the index register, in a default segment.
Ex: MOV AX, 50H [BX] [SI]
Here, 50H is an immediate displacement, BX is base register and SI is an
index register the effective address of data is computed as
10H * DS + [BX] + [SI] + 50H

For control transfer instructions, the addressing modes depend upon

whether the destination is within the same segment or different one. It also
depends upon the method of passing the destination address to the
processor.
Basically, there are two addressing modes for the control transfer
instructions, intersegment addressing and intrasegment addressing
modes.
If the location to which the control is to be transferred lies in a different
segment other than the current one, the mode is called intersegment mode.
If the destination location lies in the same segment, the mode is called
intrasegment mode.
The following table describes the default offset values to the
corresponding
memory segments.
 Intersegment direct

Intersegment

Modes for control Intersegment indirect

Transfer instructions Intrasegment direct

Intrasegment
Intrasegment indirect

Addressing modes for Control Transfer Instructions

9.Intrasegment Direct Mode: In this mode, the address to which the

control is to be transferred lies in the same segment in which the control
transfer instruction lies and appears directly in the instruction as an
immediate displacement value. In this addressing mode, the displacement is
computed relative to the content of the instruction pointer IP.
The effective address to which the control will be transferred is given by the
sum of 8 or 16-bit displacement and current content of IP. In the case of jump
instruction, if the signed displacement (d) is of 8-bits (i.e –128<d<+128) we
term it as short jump and if it is of 16-bits (i.e-32, 768<d<+32,768) it is termed
as long jump.

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 10.Intrasegment Indirect Mode: In this mode, the displacement to which
the control is to be transferred, is in the same segment in which the
control transfer instruction lies, but it is passed to the instruction
indirectly. Here, the branch address is found as the content of a register
or a memory location. This addressing mode may be used in
unconditional branch instructions.
11.Intersegment Direct: In this mode, the address to which the control is
to be transferred is in a different segment. This addressing mode provides
a means of branching from one code segment to another code segment.
Here, the CS and IP of the destination address are specified directly in the
instruction.
12.Intersegment Indirect: In this mode, the address to which the
control is to be transferred lies in a different segment and it is passed to
the instruction indirectly, i.e contents of a memory block containing four
bytes, i.e IP (LSB), IP(MSB), CS(LSB) and CS (MSB) sequentially. The
starting address of the memory block may be referred using any of the
addressing modes, except immediate mode.
Forming the effective Addresses:

The following examples explain forming of the effective addresses in the different modes.

Ex: 1. The contents of different registers are given below. Form effective addresses for different
addressing modes.

Offset (displacement)=5000H

[AX]-1000H, [BX]- 2000H, [SI]-3000H, [DI]-4000H, [BP]-5000H,

[SP]-6000H, [CS]-0000H, [DS]-1000H, [SS]-2000H, [IP]-7000H

Shifting segment address four bits to the left is equivalent to

multiplying it by 16D or 10H
i. Direct addressing mode:
MOV AX,[5000H]

DS : OFFSET  1000H : 5000H

10H*DS  10000—segment address

offset  +5000---offset address

15000H – Effective address

ii. Register indirect:

MOV AX, [BX]

DS: BX  1000H: 2000H

10H*DS  10000—segment address

[BX]  +2000---offset address

12000H – Effective address

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 Register relative:
MOV AX, 5000 [BX]

DS : [5000+BX]

10H*DS  10000

offset  +5000

[BX]  +2000

17000H –
Based indexed: Effective
address
MOV AX, [BX] [SI]

DS : [BX + SI]
10H*DS  10000
[BX]  +2000
[SI]  +3000
_______
15000H – Effective address
 v. Relative based index:
MOV AX, 5000[BX][SI]
DS : [BX+SI+5000]

10H*DS  10000

[BX]  +2000

[SI]  +3000

+500
0

1A0
00H
–
Effec
tive
addr
ess
Pin Diagram of
8086:
Signal
description of
8086:
 The 8086 is a 16-bit microprocessor. This microprocessor
operates in single processor or multiprocessor configurations
Common Signals for both Minimum mode and Maximum
mode:

AD7 - AD0 : The address/ data bus lines are the multiplexed address
data bus and contain the right most eight bit of memory address
or data. The address and data bits are separated by using ALE
signal.

AD15 - AD8 : The address/data bus lines compose the upper

multiplexed address/data bus. This lines contain address bit A15 -

A8 or data bus D15 - D8 . The address and data bits are separated
by using ALE signal.

A19 / S6  A18 / S3 The address/status bus bits are multiplexed to provide address

signals A19  A16 and also status bits S6  S3 . The address bits are separated from the

status bits using the ALE signals. The status bit S6 is always a logic 0, bit S5
The S4 and S3 indicate which segment register is
presently being used for memory access.

S4 S3 Type of segment register used

0 0 Extra segment
0 1 Stack segment
1 0 Code or no segment
1 1 Data Segment
BHE / S7 The bus high enable (BHE) signal is used to indicate the transfer of data over the higher order

D15  D8  data bus. It goes low for the data transfer over D15  D8 and is used to derive
chip select of odd address memory bank or peripherals.

BHE A0 Indication

0 0 Whole word

0 1 Upper byte from or to odd

address

1 0 Lower byte from or to even

address
1 1 None

RD : Read: whenever the read signal is at logic Low-0, the data bus receives the data
from the memory or I/O devices connected to the system
READY: This is the acknowledgement from the slow devices or memory
that they have completed the data transfer operation. This signal is
active high.

INTR: Interrupt Request: Interrupt request is used to request a hardware

interrupt of INTR is held high when interrupt enable flag is set, the
8086 enters an interrupt acknowledgement cycle after the current
instruction has completed its execution.

TEST : This input is tested by “WAIT” instruction. If the TEST input goes
low; execution will continue. Else the processor remains in an idle
state.

NMI- Non-maskable Interrupt: The non-maskable interrupt input is similar to

INTR except that the NMI interrupt does not check for interrupt enable
flag is at logic 1, i.e, NMI is not maskable internally by software. If
NMI is activated, the interrupt input uses interrupt vector 2.

RESET: The reset input causes the microprocessor to reset itself. When
8086 reset, it restarts the execution from memory location FFFF0H.
The reset signal is active high and must be active for at least four clock
cycles.
 VCC (+5V): Power supply for the operation of the internal circuit

GND: Ground for the internal circuit

MN / MX : The minimum/maximum mode signal to select the mode of

operation either in minimum or maximum mode configuration. Logic
1 indicates minimum mode.

Minimum mode Signals: The following signals are for minimum

mode operation of 8086.

M / IO - Memory/IO M / IO signal selects either memory operation or I/O

operation. This line indicates that the microprocessor address bus
contains either a memory address or an I/O port address. Signal
high at this pin
indicates a memory operation. This line is logically equivalent to S2 in
maximum mode.
 INTA - Interrupt acknowledge: The interrupt acknowledge signal is a response to the
INTR input signal. The INTA signal is normally used to gate the interrupt vector
number onto the data bus in response to an interrupt request.

ALE- Address Latch Enable: This output signal indicates the availability of valid address on
the address/data bus, and is connected to latch enable input of latches.

DT / R : Data transmit/Receive: This output signal is used to decide the direction of

date flow through the bi- directional buffer. DT / R  1 Indicates transmitting and DT / R 

0 indicates receiving the data.

DEN Data Enable: Data bus enable signal indicates the availability of valid data over
the address/data lines.

𝑊̅𝑅̅ WR: whenever the write signal is at logic 0, the data bus transmits the data to
̅

the memory or I/O devices connected to the system.

HOLD: The hold input request a direct memory access (DMA). If the hold signal is at logic
1, the micro process stops its normal execution and places its address, data and
control bus at the high impedance state.
 S2 S1 S0 Function
0 0 0 Interrupt Acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code Access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive (In active)

LOCK : The lock output is used to lock peripherals off the system, i.e,
the other system bus masters will be prevented from gaining the
system bus.

QS1 and QS0 - Queue status: The queue status bits shows the status
of the internal instruction queue. The encoding of these signals is
as follows
QS1 QS0 Function

0 0 No operation, queue is idle

0 1 First byte of opcode

1 0 Queue is empty

1 1 Subsequent byte of opcode

 RQ / GT1 and RQ / GT 0 - request/Grant: The request/grant pins are

used by other local bus masters to force the processor to release the
local bus at the end of the processors current bus cycle.

These lines are bi- directional and are used to both request and grant a

DMA operation. RQ / GT 0 is having higher priority than RQ / GT1

8086 Minimum mode system operation with timing diagrams:

 In a minimum mode 8086 system, the microprocessor 8086 is
 In this mode, all the control signals are given out| by the
operated in minimum mode by strapping its MN/MX pin to
microprocessor
logic1. chip itself. There is a single microprocessor
in the minimum mode system. The remaining components
in the system are latches, transreceivers, clock generator,
memory and I/O devices.
 Some type of chip selection logic may be required for selecting
memory or I/O devices, depending upon the address map of the
system.
 The general system organization is shown in below figure.
Figure: Minimum mode 8086 system
 The latches are generally buffered output D-type flip-flops, like, 74LS373
or 8282.
 They are used for separating the valid address from the multiplexed
address/data signals and are controlled by the ALE signal generated by
8086.
 Since it has 20 address lines and 16 data lines, the 8086 CPU requires
three octal address latches and two octal data buffers for the complete
address and data separation.
 Transreceivers are the bidirectional buffers and sometimes they are
called as data amplifiers. They are required to separate the valid data
from the time multiplexed address/data signal.
 They are controlled by two signals, namely, DEN’ and DT/R’. The DEN’
signal indicates that the valid data is available on the data bus, while
DT/R’ indicates the direction of data, i.e. from or to the processor.
 The system contains memory for the monitor and users program
storage. Usually, EPROMS are used for monitor storage, while RAMs
for users program storage.
 A system may contain I/O devices for communication with the
processor as well as some special purpose I/O devices.
 The clock generator generates the clock from the crystal oscillator and
then shapes it and divides to make it more precise so that it can be
used as an accurate timing reference for the system.
 The clock generator also synchronizes some external signals with the
system clock.
 The working of the minimum mode configuration system can be
better described in terms of the timing diagrams rather than
The opcode fetch and read cycles are similar. Hence the timing diagram can be
categorized in two parts, the first is the timing diagram for read cycle and the second is
the timing diagram for write cycle.

Timing Diagrams:
 Timing diagram is graphical representation of the operations of microprocessor
with respect to the time.
 State: one cycle of the clock is called state.
 Machine cycle: The basic microprocessor operation such as reading a byte from
memory or writing a byte to a port is called machine cycle and made up of more
than one state.
 Instruction cycle: The time required for microprocessor to fetch and execute
an entire instruction is called Instruction cycle and made up of more than one
machine cycle.

Note: An instruction cycle is made up of machine cycles, and a machine cycle is

made up of states. The time for a state is determined by the frequency of the clock
signal.
Read cycle timing diagram for Minimum mode:
 The best way to analyze a timing diagram such as the one to think of time as a
vertical line moving from left to right across the diagram.
 The read cycle begins in T1 with the assertion of the address latch enable (ALE)
signal and also M/IO’ signal.
 During the negative going edge of this signal, the valid address is latched on
the local bus. The BHE’ and A0 signals address low, high or both bytes.
 From T1 to T4, the M/IO’ signal indicate a memory or I/O operation. At T2, the
address is removed from the local bus and is sent to the output. The bus is
then tristated. The read () control signal is also activated in T2.
 A write cycle also begins with the assertion of ALE and the emission of the
address. The M/IO’ signal is again asserted to indicate a memory or I/O
operation.
  In T2, after sending the address in T1, the processor sends the data to be
written to the addressed location. The data remains on the bus until middle of
T4 state. The WR’ becomes active at the beginning of T2 (unlike RD’ is
somewhat delayed in T2 to provide time for floating).
 The BHE’ and A0 signals are used to select the proper byte or bytes of memory
or I/O word to be read or The M/IO’, RD’ and WR’ signals indicate the types of
data transfer as specified in Table

8086 Maximum mode system operation with timing diagrams:

 In the maximum mode, the 8086 is operated by strapping the
MN/MX’ pin to ground. In this mode, the processor derives the
status signals S2’, S1’ and S0’. Another chip called bus
controller derives the control signals using this status
information.
 In the maximum mode, there may be more than one
microprocessor in the system configuration. The other
components in the system are the same as in the minimum
8086 Maximum mode system operation
 IORC*, IOWC* are I/O read command and I/O write command
signals respectively. These signals enable an IO interface to read
or write the data from or to the addressed port. The MRDC*,
MWTC* are memory read command and memory write command
signals respectively and may be used as memory read and write
signals. All these command signals instruct the memory to
accept or send data from or to the bus.
 The maximum mode system timing diagrams are also divided in
two portions as read (input) and write (output) timing diagrams.
The address/data and address/status timings are similar to the
minimum mode. ALE is asserted in T1, just like minimum mode.
The only difference lies in the status signals used and the
available control and advanced command signals.
READ cycle timing diagram for Maximum mode:
Write cycle timing diagram for Maximum mode:
 UNIT-2
The instruction format contains two fields
1.operation code / opcode 2.Operand field
OPERATION CODE / OPCODE:
It indicates the type of the operation to be performed by CPU
Example : MOV , ADD …
OPERAND:
The CPU executes the instruction using the information resides in these fields .
There are six general formats of instructions in 8086 instruction set. The
instruction of 8086 vary from 1to 6 bytes length
ONE BYTE INSTRUCTION:
It is only one byte long and may have implied data or register operands.
The least three significant 3 bits of the opcode are used for specifying register
operand if any otherwise all the 8 bits form an opcode and the operands are implied.
REGISTER TO REGISTER
The format is 2 byte long
The first byte of the code specifies the opcode and width
The second byte of the code shows the register operand and R/M field
The Register represented by REG is one of the operands . The R/M field specifies
another register or memory location .ie the other operand
REGISTER TO/FROM MEMORY WITH NO DISPLACEMENT
The format is 2 byte long
This is similar to the register to register format except for the MOD field is shown.
The MOD field shows the mode of addressing
 INSTRUCTION SET OF 8086
The 8086 microprocessor supports 8 types of instructions −
 Data Transfer Instructions
 Arithmetic Instructions
 logical Instructions
 String Instructions
 Program Execution Transfer Instructions (Branch & Loop Instructions)
 Processor Control Instructions
 Iteration Control Instructions
 Interrupt Instructions

1.DATA TRANSFER INSTRUCTIONS

These instructions are used to transfer the data from the source operand to the destination operand.
Following are the list of instructions under this group −
INSTRUCTION TO TRANSFER A WORD
 MOV − Used to copy the byte or word from the provided source to the provided
destination.
 PPUSH − Used to put a word at the top of the stack.
 POP − Used to get a word from the top of the stack to the provided location.
 PUSHA − Used to put all the registers into the stack.
 POPA − Used to get words from the stack to all registers.
  XCHG − Used to exchange the data from two locations.
 XLAT − Used to translate a byte in AL using a table in the memory.

INSTRUCTIONS FOR INPUT AND OUTPUT PORT TRANSFER

 IN − Used to read a byte or word from the provided port to the
accumulator.
 OUT − Used to send out a byte or word from the accumulator to the
provided
INSTRUCTIONS
port. TO TRANSFER THE ADDRESS
 LEA − Used to load the address of operand into the provided register.
 LDS − Used to load DS register and other provided register from the memory
 LES − Used to load ES register and other provided register from the memory.

INSTRUCTIONS TO TRANSFER FLAG REGISTERS

 LAHF − Used to load AH with the low byte of the flag register.
 SAHF − Used to store AH register to low byte of the flag register.
 PUSHF − Used to copy the flag register at the top of the stack.
 POPF − Used to copy a word at the top of the stack to the flag register.
2. ARITHMETIC INSTRUCTIONS
These instructions are used to perform arithmetic operations like
addition, subtraction, multiplication, division, etc.
Following is the list of instructions under this group −
INSTRUCTIONS TO PERFORM ADDITION
 ADD − Used to add the provided byte to byte/word to word.
 ADC − Used to add with carry.
 INC − Used to increment the provided byte/word by 1.
 AAA − Used to adjust ASCII after addition.
 DAA − Used to adjust the decimal after the addition/subtraction operation.

INSTRUCTIONS TO PERFORM SUBTRACTION

 SUB − Used to subtract the byte from byte/word from word.

 SBB − Used to perform subtraction with borrow.
 DEC − Used to decrement the provided byte/word by 1.
 NPG − Used to negate each bit of the provided byte/word and add 1/2’s
complement.
 CMP − Used to compare 2 provided byte/word.
 AAS − Used to adjust ASCII codes after subtraction.
 DAS − Used to adjust decimal after subtraction.
 INSTRUCTION TO PERFORM MULTIPLICATION

 MUL − Used to multiply unsigned byte by byte/word by word.

 IMUL − Used to multiply signed byte by byte/word by word.
 AAM − Used to adjust ASCII codes after multiplication.

INSTRUCTIONS TO PERFORM DIVISION

 DIV − Used to divide the unsigned word by byte or unsigned double
word by
word.
 IDIV − Used to divide the signed word by byte or signed double word by
word.
 AAD − Used to adjust ASCII codes after division.
 CBW − Used to fill the upper byte of the word with the copies of sign bit
of the
lower byte.
 CWD − Used to fill the upper word of the double word with the sign bit of
the lower word.
3. LOGICAL INSTRUCTIONS
These instructions are used to perform operations where data bits are
involved,
i.e. operations like logical, shift, etc.
INSTRUCTIONS TO PERFORM LOGICAL OPERATION
 NOT − Used to invert each bit of a byte or word.
 AND − Used for adding each bit in a byte/word with the corresponding bit
in
another byte/word.
 OR − Used to multiply each bit in a byte/word with the corresponding bit
in another byte/word.
 XOR − Used to perform Exclusive-OR operation over each bit in a byte/word
with the corresponding bit in another byte/word.
 TEST − Used to add operands to update flags, without affecting operands.
INSTRUCTIONS TO PERFORM SHIFT OPERATIONS
 SHL/SAL − Used to shift bits of a byte/word towards left and put zero(S) in
LSBs.
 SHR − Used to shift bits of a byte/word towards the right and put zero(S)
in
MSBs.
 SAR − Used to shift bits of a byte/word towards the right and copy the old
INSTRUCTIONS TO PERFORM ROTATE OPERATIONS
MSB
 ROLinto the new
− Used MSB. bits of byte/word towards the left, i.e. MSB to LSB
to rotate
and to
Carry Flag [CF].
 ROR − Used to rotate bits of byte/word towards the right, i.e. LSB to MSB
and to
  RCR − Used to rotate bits of byte/word towards the right, i.e. LSB to CF
and CF to MSB.
 RCL − Used to rotate bits of byte/word towards the left, i.e. MSB to CF and
CF to LSB.
4.STRING INSTRUCTIONS
String is a group of bytes/words and their memory is always allocated in
a sequential order.
Following is the list of instructions under this group −
 REP − Used to repeat the given instruction till CX ≠ 0.
 REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero
flag ZF = 1.
 REPNE/REPNZ − Used to repeat the given instruction until CX = 0 or
zero flag ZF = 1.
 MOVS/MOVSB/MOVSW − Used to move the byte/word from one string
to another.
 COMS/COMPSB/COMPSW − Used to compare two string bytes/words.
 INS/INSB/INSW − Used as an input string/byte/word from the I/O port to
the provided memory location.
 OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the
provided
memory location to the I/O port.
 SCAS/SCASB/SCASW − Used to scan a string and compare its byte with
5.PROGRAM EXECUTION TRANSFER INSTRUCTIONS (BRANCH AND LOOP
INSTRUCTIONS)

These instructions are used to transfer/branch the instructions during an

execution. It includes the following instructions −
Instructions to transfer the instruction during an execution without any
condition −
 CALL − Used to call a procedure and save their return address to the
stack.
 RET − Used to return from the procedure to the main program.
JMP − Used to jump to the provided address to proceed to the next
instruction.
Instructions to transfer the instruction during an execution with some
conditions −
 JA/JNBE − Used to jump if above/not below/equal instruction satisfies.
 JAE/JNB − Used to jump if above/not below instruction satisfies.
 JBE/JNA − Used to jump if below/equal/ not above instruction satisfies.
 JC − Used to jump if carry flag CF = 1
 JE/JZ − Used to jump if equal/zero flag ZF = 1
 JG/JNLE − Used to jump if greater/not less than/equal instruction satisfies.
  JGE/JNL − Used to jump if greater than/equal/not less than instruction
satisfies.
 JL/JNGE − Used to jump if less than/not greater than/equal instruction
satisfies.
 JLE/JNG − Used to jump if less than/equal/if not greater than
instruction satisfies.
 JNC − Used to jump if no carry flag (CF = 0)
 JNE/JNZ − Used to jump if not equal/zero flag ZF = 0
 JNO − Used to jump if no overflow flag OF = 0
 JNP/JPO − Used to jump if not parity/parity odd PF = 0
 JNS − Used to jump if not sign SF = 0
 JO − Used to jump if overflow flag OF = 1
 JP/JPE − Used to jump if parity/parity even PF = 1
 JS − Used to jump if sign flag SF = 1

6.PROCESSOR CONTROL INSTRUCTIONS

These instructions are used to control the processor action by
setting/resetting the flag values. Following are the instructions under this
group −
 STC − Used to set carry flag CF to 1
 CLC − Used to clear/reset carry flag CF to 0
 CMC − Used to put complement at the state of carry flag CF.
7.ITERATION CONTROL INSTRUCTIONS
These instructions are used to execute the given instructions for number of
times.
Following is the list of instructions under this group −
LOOP − Used to loop a group of instructions until the condition satisfies,
i.e., CX
=0
 LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF =
1 & CX = 0
 LOOPNE/LOOPNZ − Used to loop a group of instructions till it satisfies
ZF = 0 &
CX = 0
 JCXZ − Used to jump to the provided address if CX = 0
 INT − Used to interrupt the program during execution and calling
8.INTERRUPT INSTRUCTIONS
service
These instructions are used to call the interrupt during program execution.
specified.
 INTO − Used to interrupt the program during execution if OF = 1
 IRET − Used to return from interrupt service to the main program
 ASSEMBLER DIRECTIVES
Assembler directives are the Instructions to the Assembler, linker and loader
regarding the program being executed. also called ‘pseudo instructions. Control
the generation of machine codes and organization of the program; but no machine
codes are generated for assembler directives.
They are used to
› specify the start and end of a program
› attach value to variables
› allocate storage locations to input/ output data
› define start and end of segments, procedures, macros etc..
ASSUME
Used to tell the assembler the name of the logical segment it should use for a
specified segment. You must tell the assembler that what to assume for any
segment you use in the program.
Example
ASSUME: CODE
Tells the assembler that the instructions for the program are in segment named
CODE.
DB – Defined Byte
Used to declare a byte type variable or to set aside one or more locations of type
byte in memory.
Example
PRICES DB 49H, 98H, 29H:
Declare array of 3 bytes named PRICES and initialize 3 bytes as shown.

DD – Define Double Word

Used to declare a variable of type doubleword or to reserve a memory
location which can be accessed as doubleword.
DQ – Define Quadword
Used to tell the assembler to declare the variable as 4 words of storage in
memory.

DT – Define Ten Bytes

Used to tell the assembler to declare the variable which is 10 bytes in length or reserve
10 bytes of storage in memory.

DW – Define Word
Used to tell the assembler to define a variable type as word or reserve word
in memory.

DUP: used to initialize several locations and to assign values to location

END – End the Program

To tell the assembler to stop fetching the instruction and end the program execution.
Tells the assembler to increment the location counter to the next even address if it is not
already at an even address.
EXTRN
Used to tell the assembler that the name or labels following the directive are in some
other assembly module.
GLOBAL – Declares Symbols As Public Or Extrn
Used to make the symbol available to other modules.It can be used in place of EXTRN or PUBLIC keyword.
GROUP – Group related segment
Used to tell the assembler to group the logical segments named after the directive into one logical
segment. This allows the content of all the segments to be accessed from the same group.
INCLUDE – include source code from file
Used to tell the assembler to insert a block of source code from the named file into the current
source module. This shortens the source code.
LABEL
Used to give the name to the current value in the location counter. The LABEL directive
must be followed by a term which specifies the type you want associated with that name.
LENGTH -Used to determine the number of items in some data such as string or array.
NAME -Used to give a specific name to a module when the programs consisting of several modules.
OFFSET It is an operator which tells the assembler to determine the offset or displacement of named
data item or procedure from the start of the segment which contains it.
ORG – Originate
Tells the assembler to set the location counter value.
Example, ORG 7000H sets the location counter value to point to 7000H location in memory.
$ is often used to symbolically represent the value of the location counter. It is used with ORG to tell
the assembler to change the location according to the current value in the location counter. E.g. ORG $
+100.
 8086 ASSEMBLY PROGRAM TO Data Segment
ADD TWO 16-BIT NUMBERS
•a dw 0202h: This line declares a 16-bit word variable
data segment
named a and
a dw 0202h
initializes it with the hexadecimal value 0202.
b dw 0408h •b dw 0408h: Similarly, this declares a 16-bit word variable b and
c dw ? initializes
data ends it with the hexadecimal value 0408.
•c dw ?: This declares a 16-bit word variable c but does not
code segment initialize it.
It will store the result of the addition operation
assume cs:code,ds:data
start: Code Segment
mov ax,data •mov ax,data: This instruction moves the address of the data
mov ds,ax segment into the AX register.
mov ax,a •mov ds,ax: This sets the Data Segment (DS) register to the value
mov bx,b in AX, effectively making the data segment accessible for data
operations.
add ax,bx •mov ax,a: This moves the value of a (0202h) into the AX register.
mov c,ax •mov bx,b: This moves the value of b (0408h) into the BX register.
nt 3 •add ax,bx: This adds the contents of BX to the contents of AX.
code ends The result (060Ah) is stored in AX.
end start •mov c,ax: This moves the result from AX to the variable c.
•int 3: This is a breakpoint instruction that causes the program to
halt,
allowing for debugging and inspection of registers and memory.
 8086 ASSEMBLY PROGRAM FOR ADDITION OF TWO 8 BIT
NUMBERS
Data Segment:
data segment • data segment: This section defines the variables.
a db 09h • a db 09h: Declares an 8-bit byte variable a initialized
b db 02h to 09h (hexadecimal).
c dw ? • b db 02h: Declares an 8-bit byte variable b initialized
data ends to 02h.
• c dw ?: Declares a 16-bit word variable c to store the sum.
We use a 16-bit variable to handle potential overflow if the
code segment sum exceeds 255 (FFh).
assume cs:code,ds:data Code Segment:
start: This section contains the program instructions.
mov ax,data • assume cs:code,ds:data: Tells the assembler that
mov ds,ax the cs register points to the code segment and
the ds register points to the data segment.
mov al,a • start: The label marking the program’s entry point.
mov bl,b • mov ax,data: Loads the address of the data segment into
add al,bl the ax register.
mov c,ax • mov ds,ax: Sets the ds register to point to the data
int 3 segment. This is crucial for accessing the variables a and b.
• mov al,a: Loads the value of a (09h) into the al register
code ends
(the lower 8 bits of ax).
end start • mov bl,b: Loads the value of b (02h) into the bl register
(the lower 8 bits of bx).
• add al,bl: Adds the contents of bl to al. The result (0Bh) is
stored in al.
• mov c,ax: Moves the contents of ax (which now contains
the sum in its lower byte, al) into the variable c.
8086 ASSEMBLY PROGRAM TO DIVIDE TWO 16 BIT NUMBERS

data segment
a dw 4444h
b dw 0002h
c dw ?
data ends

code segment
assume ds:data, cs:code
start:
mov ax,data
mov ds,ax
mov ax,a
mov bx,b
div bx
mov c,ax
int 3
code ends
end start
 8086 ASSEMBLY PROGRAM TO MULTIPLY TWO 16 BIT
NUMBERS
data segment
a dw 1234h
b dw 5678h
c dd ?
data ends

code segment
assume ds:data, cs:code
start:
mov ax,data
mov ds,ax
mov ax,a
mov bx,b
mul bx
mov word ptr c,ax
mov word ptr c+2,dx
int 3
code ends
end start
 8086 ASSEMBLY PROGRAM TO SUBTRACT TWO 16 BIT NUMBERS

data segment
a dw 9A88h
b dw 8765h
c dw ?
data ends

code segment
assume cs:code,ds:data
start:
mov ax,data
mov ds,ax
mov ax,a
mov bx,b
sub ax,bx
mov c,ax
int 3
code ends
end start
8086 ASSEMBLY PROGRAM FOR SUBTRACTION OF TWO 32 BIT
NUMBERS

data segment
abc dd 9ABCDEF0h
def dd 12345678h
ghi dw ?
data ends

code segment
assume cs:code, ds:data
start: mov ax,data
mov ds,ax
mov dl,00h
mov ax, word ptr abc
mov bx, word ptr def
sub ax,bx
mov word ptr ghi,ax
mov ax, word ptr abc+2
mov bx, word ptr def+2
sbb ax,bx
mov word ptr ghi+2,ax
jnc move
inc dl
move: mov byte ptr ghi+4,dl
int 3
code ends
end start
 data
8086 segment
ASSEMBLY PROGRAM TO MULTIPLY TWO 32 BIT NUMBERS
abc dd 12345678H move: mov ax,word ptr abc
def dd 12345678H mul word ptr def+2
ghi dq ? add cx, ax
data ends mov word ptr ghi+2, cx
mov cx,dx
code segment
assume cs:code, jnc ma
ds:data add bx, 0001H
start: ma: mov ax, word ptr abc+2
mov ax, data mul word ptr def+2
mov ds, ax add cx, ax
mov ax, word ptr abc
mul word ptr def jnc mb
mov word ptr ghi, ax add dx, 0001H
mov cx, dx mb: add cx, bx
mov ax, word ptr mov word ptr ghi+4, cx
abc+2
mul word ptr def jnc mc
add cx, ax add dx, 0001H
mov bx, dx mc: mov word ptr ghi+6, dx
jnc move int 3
add bx,0001H code ends
end start
Data Segment
8086 Assembly Program to Add Two 16-bit Numbers with Carry

data segment
a dw 0FFFFh ; Example value that will cause a carry
b dw 0001h ; Example value
c dw ? ; To store result
carry_flag db 0 ; To store carry (0 or 1)
data ends
; Code Segment

code segment
assume cs:code, ds:data
start:
mov ax, data
mov ds, ax ; Initialize data segment

mov ax, a ; Load first number

mov bx, b ; Load second number
add ax, bx ; Perform addition

mov c, ax ; Store result in 'c'

jc carry_occurred ; Jump if carry flag is set

mov carry_flag, 0 ; No carry, store 0
jmp end_program

carry_occurred:
mov carry_flag, 1 ; Store carry flag as 1

end_program:
int 3 ; Halt program

code ends
end start
Assembly program sorts an array of numbers in ascending order using the bubble sort
algorithm:
DATA SEGMENT
STRING1 DB 99H,12H,56H,45H,36H
DATA ENDS

CODE SEGMENT
ASSUME CS:CODE,DS:DATA
START: MOV AX,DATA
MOV DS,AX

MOV CH,04H

UP2: MOV CL,04H

LEA SI,STRING1

UP1: MOV AL,[SI]

MOV BL,[SI+1]
CMP AL,BL
JC DOWN
MOV DL,[SI+1]
XCHG [SI],DL
MOV [SI+1],DL

DOWN: INC SI
DEC CL
JNZ UP1
DEC CH
JNZ UP2

INT 3
CODE ENDS
 Assembly program sorts an array of numbers in descending order using the bubble sort algorithm:

DATA SEGMENT
STRING1 DB 99H,12H,56H,45H,36H
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE,DS:DATA
START: MOV AX,DATA
MOV DS,AX
MOV CH,04H
UP2: MOV CL,04H
LEA SI,STRING1

UP1:MOV AL,[SI]
MOV BL,[SI+1]
CMP AL,BL
JNC DOWN
MOV DL,[SI+1]
XCHG [SI],DL
MOV [SI+1],DL

DOWN: INC SI
DEC CL
JNZ UP1
DEC CH
JNZ UP2
INT 3
CODE ENDS
END START
Procedures and Macros:
When we need to use a group of instructions several times throughout a program there
are two ways we can avoid having to write the group of instructions each time we
want to use them.
1.One way is to write the group of instructions as a separate procedure.
2.Another way we can use macros.
Procedures:
The procedure is a group of instructions stored as a separate program in the memory
and it is called from the main program whenever required using CALL instruction.
For calling the procedure we have to store the return address (next instruction
address followed by CALL) onto the stack.
At the end of the procedure RET instruction used to return the execution to the next
instruction in the main program by retrieving the address from the top of the stack.
Machine codes for the procedure instructions put only once in memory.
The procedure can be defined anywhere in the program using assembly directives
PROC and ENDP.
The four major ways of passing parameters to and from a procedure are:
1.In registers
2.In dedicated memory location accessed by name
3.With pointers passed in registers
4. With the stack
The type of procedure depends on where the procedure is stored in the memory.
If it is in the same code segment where the main program is stored the it is called near procedure otherwise it
is referred to as far procedure.
For near procedure CALL instruction pushes only the IP register contents on the stack, since CS register
contents remains unchanged for main program.
But for Far procedure CALL instruction pushes both IP and CS on the stack.
Syntax:
Procedure name PROC near instruction 1
instruction 2 RET
Procedure name ENDP Example:

near procedure: far procedure:

ADD2 PROC near
Procedures segment
ADD AX,BX Assume CS : Procedures
RET
ADD2 PROC far
ADD2 ENDP
ADD AX,BX
RET ADD2 ENDP
Procedures ends
  Depending on the characteristics the procedures are two types
1.Re-entrant Procedures
2.Recursive Procedures
Reentrant Procedures
 The procedure which can be interrupted, used and “reentered” without losing or writing over anything.

Recursive Procedure
A recursive procedure is procedure
which calls itself.
Macros:
 A macro is a group of repetitive instructions in a program which are codified only once and can be used as many
times as necessary.
 A macro can be defined anywhere in program using the directives MACRO and ENDM
 Each time we call the macro in a program, the assembler will insert the defined group of instructions in place of the
call.
 The assembler generates machine codes for the group of instructions each time the macro is called.
 Using a macro avoids the overhead time involved in calling and returning from a procedure.
Syntax of macro:
macroname MACRO
instruction1 instruction2
.. ENDM
 Example:
ALP for Finding Factorial of number using procedures
CODE SEGMENT
ASSUME CS:CODE
FACT MACRO
MOV BX,AX
DEC BX
Read Display MACRO
BACK: MUL BX
MACRO mov dl,al
DEC BX Mov ah,02h
mov ah,01h
JNZ BACK int 21h
int 21h
ENDM ENDM ENDM
START: MOV AX,7 FACT
MOV AH,4CH
INT 21H
CODE ENDS
END START
Advantage of Procedure and Macros:
Procedures: Advantages
⚫ The machine codes for the group of instructions in the procedure Page 83
Disadvantages
⚫Need for stack
⚫Overhead time required to call the procedure and return to the calling
program. Macros: Advantages
⚫Macro avoids overhead time involving in calling and returning from a procedure.
Disadvantages
⚫Generating in line code each time a macro is called is that this will make the program take up more
memory than using a procedure.
Differences between Procedures and Macros:
PROCEDURES MACROS
Accessed by CALL and RET mechanism during Accessed by name given to macro when defined
program execution during assembly
Machine code for instructions only put in memory Machine code generated for instructions each
once time called
Parameters are passed in registers, memory Parameters passed as part of statement which
locations or stack calls macro
Procedures uses stack Macro does not utilize stack
A procedure can be defined anywhere in program A macro can be defined anywhere in program
using the directives PROC and ENDP using the directives MACRO and ENDM
Procedures takes huge memory for CALL (3 bytes Length of code is very huge if macro’s are called for
each time CALL is used) instruction more number of times
Page 84
 UNIT -3

Interfacing to Microprocessor
Overview of I/O Data Transfer
In microprocessor-based systems, communication between the microprocessor and
external devices (such as keyboards, displays, sensors, etc.) is essential. This data
exchange is known as Input/Output (I/O) data transfer and is facilitated using I/O
ports.
Input Operation: Data transfer from an external device (e.g., keyboard) to the
microprocessor.
Output Operation: Data transfer from the microprocessor to an external device (e.g.,
display).
Input port:

It is used to read data from the input device such as keyboard. The simplest form of
input port is a buffer. The input device is connected to the microprocessor through buffer,
as shown in the fig.1. This buffer is a tri-state buffer and its output is available only when
enable signal is active. When microprocessor wants to read data from the input device
(keyboard), the control signals from the microprocessor activates the buffer by asserting
enable input of the buffer. Once the buffer is enabled, data from the input device is
available on the data bus. Microprocessor reads this data by initiating read command.
 It is used to send data to the output device such as display from the microprocessor. The
simplest form of output port is a latch. The output device is connected to the microprocessor through
latch, as shown in the fig.2. When microprocessor wants to send data to the output device is puts the
data on the data bus and activates the clock signal of the latch, latching the data from the data bus at
the output of latch. It is then available at the output of latch for the output device.
Serial and Parallel Transmission:

In telecommunications, serial transmission is the sequential transmission of signal elements of a

group representing a character or other entity of data. Digital serial transmissions are bits sent over a
single wire, frequency or optical path sequentially. Because it requires less signal processing and less
chance for error than parallel transmission, the transfer rate of each individual path may be faster. This
can be used over longer distances as a check digit or parity bit can be sent along it easily.
In telecommunications, parallel transmission is the simultaneous transmission of the signal elements of
a character or other entity of data. In digital communications, parallel transmission is the simultaneous
transmission of related signal elements over two or more separate paths. Multiple electrical wires are
used which can transmit multiple bits simultaneously, which allows for higher data transfer rates than
can be achieved with serial transmission. This method is used internally within the computer, for example
the internal buses, and sometimes externally for such things as printers, The major issue with this is
"skewing" because the wires in parallel data transmission have slightly different properties (not
intentionally) so some bits may arrive before others, which may corrupt the message. A parity bit can help
to reduce this. However, electrical wire parallel data transmission is therefore less reliable for long
Interrupt driven I/O:
In this technique, a CPU automatically executes one of a collection of special routines whenever
certain condition exists within a program or a processor system. Example CPU gives response to devices
such as keyboard, sensor and other components when they request for service. When the CPU is asked to
communicate with devices, it services the devices. Example each time you type a character on a keyboard,
a keyboard service routine is called. It transfers the character you typed from the keyboard I/O port into the
processor and then to a data buffer in memory.
The interrupt driven I/O technique allows the CPU to execute its main program and only stop to service
I/O device when it is told to do so by the I/O system as shown in fig.3. This method provides an external
asynchronous input that would inform the processor that it should complete whatever instruction that is
currently being executed and fetch a new routine that will service the requesting device. Once this
servicing is completed, the processor would resume exactly where it left off.

An analogy to the interrupt concept is in the classroom, where the professor serves as CPU and the
students as I/O ports. The classroom scenario for this interrupt analogy will be such that the professor is
busy in writing on the blackboard and delivering his lecture.
The student raises his finger when he wants to ask a question (student requesting for service). The
professor then completes his sentence and acknowledges student‟s request by saying “YES”
(professor acknowledges the interrupt request). After acknowledgement from the professor, student
asks the question and professor gives answer to the question (professor services the interrupt). After that
professor continues its remaining lecture form where it was left.
PPI- 8255:
PIO 8255:
The parallel input-output port chip 8255 is also called as
programmableperipheral input-output port. The Intel‟s 8255 are
designed for use with Intel‟s 8-bit, 16-bit and higher capability
microprocessors. It has 24 input/output lineswhich may be individually
programmed in two groups of twelve lines each, orthree groups of eight
lines.

The two groups of I/O pins are named as Group A and Group B. Each of
thesetwo groups contains a subgroup of eight I/O lines called as 8-bit port
and anothersubgroup of four lines or a 4-bit port. Thus Group A contains an
8-bit port Aalong with a 4-bit port C upper.
The 8-bit data bus buffer is controlled by the read/write control logic. The
read/write control logic manages all of the internal and external transfer of
both data and control words. RD, WR, A1, A0 and RESET are the inputs,
provided by the microprocessor to READ/WRITE control logic of 8255. The
8-bit, 3-state bidirectional buffer is used to interface the 8255 internal
data bus with the external system data bus. This buffer receives or
transmits data upon the execution of input or output instructions by the
microprocessor. The control words or status information is also transferred
through the buffer.
Pin Diagram of 8255A
 The pin diagram of 8255 is shown in fig.
The port A lines are identified by symbols PA0-PA7 while the port C lines are
Identified as PC4-PC7. Similarly, Group B contains an 8-bit port B, containing
lines PB0-PB7 and a 4-bit port C with lower bits PC0- PC3. The port C upper
and port C lower can be used in combination as an 8-bit port C. Both the port
C is assigned the same address. Thus one may have either three 8-bit I/O
ports or two 8-bit and two 4-bit ports from 8255. All of these ports can
function independently either as input or as output ports. This can be
achieved by programming the bits of an internal register of 8255 called as
control word register (CWR).

The signal description of 8255 is briefly presented as follows:

PA7-PA0: These are eight port A lines that acts as either latched output or
buffered input lines depending upon the control word loaded into the control
word register.
PC7-PC4: Upper nibble of port C lines. They may act as either output latches
or input buffers lines.
This port also can be used for generation of handshake lines in mode1 or
mode2.
PC3-PC0: These are the lower port C lines; other details are the same as
PC7-PC4 lines.
PB0-PB7: These are the eight port B lines which are used as latched output
lines or buffered input lines in the same way as port A.
RD: This is the input line driven by the microprocessor and should be low
to indicate read operation to 8255.
WR: This is an input line driven by the microprocessor. A low on this line
indicates write operation.
CS: This is a chip select line. If this line goes low, it enables the 8255 to
respond to RD and WR signals, otherwise RD and WR signal are neglected.
D0-D7: These are the data bus lines those carry data or control word
to/from the microprocessor.
RESET:Logic high on this line clears the control word register of 8255. All
ports are set as input ports by default after reset.
A1-A0: These are the address input lines and are driven by the
microprocessor.
These lines A1-A0 with RD, WR and CS from the following operations for
8255. These address lines are used for addressing any one of the four
registers, i.e. three ports and a control word register as given in table
below.
In case of 8086 systems, if the 8255 is to be interfaced with lower order
data bus, the A0 and A1 pins of 8255 are connected with A1 and A2
respectively.
Control word
register
Modes of Operation of 8255
These are two basic modes of operation of 8255. I/O mode and Bit Set-Reset mode (BSR).
In I/O mode, the 8255 ports work as programmable I/O ports, while in BSR mode only port C
(PC0-PC7) can be used to set or reset its individual port bits.
Under the I/O mode of operation, further there are three modes of operation of 8255, so as to
support different types of applications, mode 0, mode 1 and mode 2.
BSR Mode: In this mode any of the 8-bits of port C can be set or reset depending on D0 of the
control word. The bit to be set or reset is selected by bit select flags D3, D2 and D1 of the CWR
as given in table.
I/O Modes:
a) Mode 0 (Basic I/O mode): This mode is also called as basic input/output Mode. This mode
provides simple input and output capabilities using each of the three ports. Data can be simply
read from and written to the input and output ports respectively, after appropriate
initialization.
The salient features of this mode are as listed below:

1.Two 8-bit ports (port A and port B) and two 4-bit ports (port C upper and lower) are
available. The two 4-bit ports can be combined used as a third 8-bit port.
2.Any port can be used as an input or output port.
3.Output ports are latched. Input ports are not latched.
4.A maximum of four ports are available so that overall 16 I/O configurations
arepossible.

All these modes can be selected by programming a register internal to 8255known as

CWR.
The controlThese
wordformats arehas
register shown
twoinformats.
followingThe
fig. first format is valid for I/O modesof
operation, i.e. modes 0, mode 1 and mode 2 while the second format is valid for bit
set/reset (BSR) mode of operation.
b) Mode 1: ( Strobed input/output mode ) In this mode the
handshaking control the input and output action of the specified port. Port
C lines PC0-PC2, provide strobe or handshake lines for port B. This group
which includes port B and PC0-PC2 is called asgroup B for Strobed data
input/output. Port C lines PC3-PC5 provides strobe lines for portA.This group
including port A and PC3-PC5 from group A. Thus port C is utilized for
generating handshake signals.
The salient features of mode 1 are listed as follows:

1.Two groups – group A and group B are available for strobed data transfer.
2.Each group contains one 8-bit data I/O port and one 4-bit control/data
port.
3.The 8-bit data port can be either used as input and output port. The
inputs and outputs both are latched.
4.Out of 8-bit port C, PC0-PC2 are used to generate control signals for
port B andPC3-PC5 are used to generate control signals for port A. the
lines PC6, PC7 may be used as independent data lines.
The control signals for both the groups in input and output modes
are explained as follows: Input control signal definitions (mode 1):

• STB (Strobe input) – If this lines falls to logic low level, the data available
at 8- bit input port is loaded into input latches.
• IBF (Input buffer full) – If this signal rises to logic 1, it indicates that
data has been loaded into latches, i.e. it works as an acknowledgement.
IBF is set by a low on STB and is reset by the rising edge of RD input.
• INTR (Interrupt request) – This active high output signal can be
used to
interrupt the CPU whenever an input device requests the service. INTR is
set by a
high STB pin and a high at IBF pin. INTE is an internal flag that can be
controlledby the bit set/reset mode of either PC4 (INTEA) or PC2 (INTEB) as
shown in fig.
• INTR is reset by a falling edge of RD input. Thus an external input
device can be request the service of the processor by putting the data on
the bus and sending the strobe signal.
Output control signal definitions (mode 1):

• OBF (Output buffer full) – This status signal, whenever falls to low,
indicatesthat CPU has written data to the specified output port. The OBF flip- flop will
beset by a rising edge of WR signal and reset by a low going edge at the ACKinput.
• ACK (Acknowledgeinput) – ACK signal acts as an acknowledgement to begiven by
an output device. ACK signal, whenever low, informs the CPU that thedata transferred
by the CPU to the output device through the port is received bythe output device.
• INTR (Interruptrequest) – Thus an output signal that can be used to
interruptthe CPU when an output device acknowledges the data received from the
CPU.INTR is set when ACK, OBF and INTE are 1. It is reset by a falling edge on WR
input. The INTEA and INTEB flags are controlled by the bit set-reset mode ofPC6 and
PC2 respectively.
 c)Mode 2 (Strobed bidirectional I/O): This mode of operation of 8255 is also called
as strobed bidirectional I/O. This mode of operation provides 8255 with additional features
for communicating with a peripheral device on an 8-bit databus. Handshaking signals
are provided to maintain proper data flow andsynchronization between the data
transmitter and receiver. The interruptgeneration and other functions are similar to mode
1.
In this mode, 8255 is a bidirectional 8-bit port with handshake signals. The RD and WR
signals decide whether the 8255 is going to operate as an input port or output port.
The Salient features of Mode 2 of 8255 are listed as follows:

1.The single 8-bit port in group A is available.

2.The 8-bit port is bidirectional and additionally a 5-bit control port is available.
3.Three I/O lines are available at port C.( PC2 – PC0 )
4.Inputs and outputs are both latched.
5.The 5-bitcontrol portC(PC3-PC7)is usedfor generating/accepting handshake signals for the 8-bit data
transfer on port A.
Control signal definitions in mode 2:
INTR – (Interrupt request) As in mode 1, this control signal is active high and is used to
interrupt the microprocessor to ask for transfer of the next data byte to/from it. This
signal is used for input (read) as well as output (write) operations.
Control Signals for Output operations:
OBF (Output buffer full) – This signal, when falls to low level, indicates that the CPU has
written data to port A
ACK (Acknowledge) This control input, when falls to logic low level,
Acknowledges that the previous data byte is received by the destination and next byte
may be sent by the processor. This signal enables the internal tristate buffers to send the
next data byte on port A.
Control signals for input operations:

STB (Strobe input)a low on this line is used to strobe in the data into the input Latches
of 8255.
IBF (Input buffer full) when the data is loaded into input buffer, this signal risesto logic
„1‟. This can be used as an acknowledge that the data has been receivedby the receiver.
The waveforms in fig show the operation in Mode 2 for output as well as input port.
Note: WR must occur before ACK and STB must be activated before RD.
The following fig shows a schematic diagram containing an 8-bit bidirectionalport, 5-bit control port
and the relation of INTR with the control pins. Port B caneither be set to Mode 0 or 1 with port A( Group A ) is
in Mode 2.
Mode 2 is not available for port B. The following fig shows the control word. The INTR goes high only if IBF,
INTE2, STB and RD go high or OBF,
INTE1, ACK and WR go high. The port C can be read to know the status of theperipheral device, in terms
of the control signals, using the normal I/Oinstructions.
Interfacing Analog to Digital Data Converters:
In most of the cases, the PIO 8255 is used for interfacing the analog to
digital converters with microprocessor.
 The ADC is treated as an input device by the microprocessor that sends an
initializing signal to the ADC to start the analogy to digital data
conversation process. The start of conversation signal is a pulse of a specific
duration.
The process of analog to digital conversion is a slow Process and the
microprocessor have to wait for the digital data till the conversion is over.
After the conversion is over, the ADC sends end of conversion EOC signal to
inform the microprocessor that the conversion is over and the result is ready
at the output buffer of the ADC. These tasks of issuing an SOC pulse to ADC,
reading EOC signal from the ADC and reading the digital output of the
ADCare carried out by the CPU using 8255 I/O ports.
The time taken by the ADC from the active edge of SOCpulse till the active
edge of EOC signal is called as the conversion delay of the ADC.
It may range anywhere from a few microseconds in caseof fast ADC to even
a few hundred milliseconds in case ofslow ADCs.
Approximation techniques and dual slope integration techniques are the
most popular techniques used in the integrated ADC chip.
General algorithm for ADC interfacing contains thefollowing steps:
Ensure the stability of analog input, applied to the ADC.
Issue start of conversion pulse to ADC
Read end of conversion signal to mark the end ofconversion processes.
Read digital data output of the ADC as equivalent digital output.
Analog input voltage must be constant at the input of the ADC right from the start of
conversion till the end of the conversion to get correct results. This may be ensured by a
sample and hold circuit which samples the analog signal and holds it constant for
specific time duration. The microprocessor may issue a hold signal to the sample and
hold circuit.
If the applied input changes before the complete conversion process is over, the digital
equivalent of the analog input calculated by the ADC may not be correct.
ADC 0808/0809:
 The analog to digital converter chips 0808 and 0809 are 8-bit CMOS, successive
approximation converters. This technique is one of the fast techniques for analog to
digital conversion. The conversion delay is 100µs at a clock frequency of 640 KHz,
which is quite low as compared to other converters. These converters do not need
any external zero or full scale adjustments as they are already taken care of by
internal circuits.
 These converters internally have a 3:8 analog multiplexer so that at a time eight
different analog conversion by using address lines - A, B, and C, as shown. Using
these address inputs, multichannel data acquisition system can be designed using a
single ADC. The CPU may drive these lines using output port lines in case of
multichannel applications. In case of single input applications, these may be
hardwired to select the proper input.
 There are unipolar analog to digital converters, i.e. they are able to convert only
positive analog input voltage to their digital equivalent. These chips do not
contain any internal sample and hold circuit.
If one needs a sample and hold circuit for the conversion of fast signal into
equivalent digital quantities, it has to be externally connected at each of the
analog inputs.
Fig (1) and Fig (2) show the block diagrams and pin diagrams for ADC 0808/0809.

Table.1
Address lines

Analog I/P
selected C B A

I/P 0 0 0 0
I/P 1 0 0 1
I/P 2 0 1 0
I/P 3 0 1 1
I/P 4 1 0 0
I/P 5 1 0 1
I/P 6 1 1 0
I/P 7 1 1 1
Block Diagram of ADC 0808/0809
 Pin Diagram

0- I/P7
I/P
: Analog inputs
ADD A, B, C : Address lines for selecting analog inputs
O7-O0 : Digital 8-bit output with O7 MSB and O0
SOC LSB
EOC : Start conversion signal pin
OE : End of conversion signal pin
: Output latch enable pin, if high enable output
CLK
: Clock input for ADC
VCC,
: Supply pins +5V and GND
GND
Vref+ and
: Reference voltage positive (+5 V maximum)
Vref-
and reference voltage negative (0V minimum)
Some Electrical Specifications Of The ADC 0808/0809 Are Given In Table.2.
Table.2

Fig.3 Timing Diagram Of ADC 0808.

Interfacing ADC0808 with 8086

Figure 3.23. Interfacing Diagram

Control word
1 0 0 1 1 0 0 0 =98h
 The analog I/P I/P2 is used and therefore the address pins A, B, C
should be
0,1,0 respectively to select I/P 2. The OE and ALE pins are at +5V to select
the ADC and enable the outputs
 PCU acts as the input port to receive the EOC signal and PCL acts as the
output port to send SOC to ADC
 PA acts as a 8-bit input data port to receive the digital data output from
 ALP is shown
below : initialize 8255 as
MOV AL, 98H : discussed above
OUT CWR, AL : Select I/P2 as analog
MOV AL, 02H : Input
OUT PORT B, : Give start of conversion
AL MOV : Pulse to the ADC
AL,00H OUT :
PORT C, AL :
WAIT: MOV AL, 01 H :
OUT
IN AL,PORT C,
PORTC : Check for EOC by
AL MOV AL,
RCL : reading port C upper and
00H WAIT
JNC : rotating through carry
IN AL, PORTA : If EOC. Read digital equivalent
HLT in AL
: Stop
Interfacing Digital To Analog Converters:
The digital to analog converters convert binary numbers into their analog equivalent
voltages. The DAC find applications in areas like digitally controlled gains, motor speed
controls, programmable gain amplifiers, etc.
DAC0800 8-bit Digital to Analog Converter
The DAC0800 is a monolithic 8-bitDAC manufactured by National Semiconductor.
It has settling time around 100ms and can operate on a range of power supply voltages i.e. from
4.5V to +18V. Usually the supply V+ is 5V or +12V. The V-pin can be kept at a minimum of -12V.

Pin Diagram of DAC 0800

Interfacing DAC0800 with 8086
Ad 7523 8-Bit Multiplying DAC:
Intersil‘s AD 7523 is a 16 pin DIP, multiplying digital to analog converter, containing R-
2R ladder(R=10KΩ) for digital to analog conversion along with single pole double
through NMOS switches to connect the digital inputs to the ladder.
Pin Diagram of AD7523
The supply range extends from +5V to +15V , while Vref may be anywhere between -10V to
+10V. The maximum analog output voltage will be +10V, when all the digital inputs are at logic
high state. Usually a Zener is connected between OUT1 and OUT2 to save the DAC from negative
transients.
An operational amplifier is used as a current to voltage converter at the output of AD 7523 to
convert the current output of AD7523 to a proportional output voltage.

It also offers additional drive capability to the DAC output. An external

feedback resistor acts to control the gain. One may not connect any external
feedback resistor, if no gain control is required.
Interfacing AD7523 with 8086
 Keyboard Interfacing
In most keyboards, the key switches are connected in a matrix of Rows and Columns.
Getting meaningful data from a keyboard requires three major tasks:
1.D e t e c t a k e y p r e s s
2.D e b o u n c e t h e k e y p r e s s .
3.Encode the keypress (produce a standard code for the pressed key).

Logic „0‟ is read by the microprocessor when the key is pressed.

Key Debounce:

Whenever a mechanical push-bottom is pressed or released once,the mechanical

components of the key do not change the positionsmoothly; rather it generates a transient
response. These may be interpreted as the multiple pressures and responded accordingly.
The rows of the matrix are connected to four output Port lines, &columns
are connected to four input Port lines.
When no keys are pressed, the column lines are held high by the pull-up
resistors connected to +5v.
Pressing a key connects a row & a column.
To detect if any key is pressed is to output 0‟s to all rows & then check
columns
to see it a pressed key has connected a low (zero) to a column.
Once the columns are found to be all high, the program enters another
loop, which waits until a low appears on one of the columns i.e indicating a
key press. A simple 20/10 msec delay is executed to debounce task.
After the debounce time, another check is made to see if the key is still
pressed. If the columns are now all high, then no key is pressed & the initial
detection was caused by a noise pulse.
To avoid this problem, two schemes are suggested:
1.Use of Bistablemultivibrator at the output of the key to debounce it.
2.The microprocessor has to wait for the transient period (at least for 10
ms), so that the transient response settles down and reaches a steady
state.

If any of the columns are low now, then the assumption is made that it
was a valid key press.
 Interfacing 4x4 keyboard
The final task is to determine the row & column of the pressed key
&convert this information to Hex-code for the pressed key.
The 4-bit code from I/P port & the 4-bit code from O/P port (row &column)
are converted to Hex-code.
Display Interface
Interfacing multiplexed 7-segment display
8253 PROGRAMMABLE INTERVAL TIMER
8253 Programmable Interval Timer – In the process control system or
automation industry, a number of operations are generally performed
sequentially. Between two operations, a fixed time delay is specified. In a
microprocessor-based system, time delay can be generated using software.
Sequences of operations are also performed based on software. Therefore,
time delay, sequence and counting can be done under the control of a
microprocessor. These most common problems can be solved using the 8253
in any microcomputer system.
The 8253 Programmable Interval Timer/counter specifically designed for
use in real-time application for timing and counting function such as binary
The counter/timer can also use for non-delay in nature such as
counting,
Programmable Rate Generator, Event Counter, Binary Rate Multiplier, Real
Time Clock, Digital One-Shot, and Complex Motor Controller. The 8253
operates in the frequency range of dc to 2.6 MHz while the 8253 use NMOS
technology. The 8253 is compatible to
the 8085 microprocessors. Generally, 8253 Programmable Interval Timer
can be operating in the following modes.
 Mode 0 Interrupt on terminal count
 Mode 1 Programmable one-shot
 Mode 2 Rate generator
 Mode 3 Square-wave generator
 Mode 4 Software triggered mode
 Mode 5 Hardware triggered mode
 The pin diagram, block diagram of 8253, interfacing with 8085
microprocessor and operation of each mode have been explained in this
section.

3.14.1. Pin Diagram of 8253

The 8253 timer is a 24-pin IC and operates at +5 V dc. It consists of three

independent programmable 16-bit counters: Counter 0, Counter 1, and
Counter 2. Each counter operates as a 16-bit down counter and each counter
consists of clock input, gate input and output as depicted in Fig. 8.75. The
schematic block diagram is given in Fig. 8.75. The gate input is used to
enable the counting process. Therefore, the starting of counting may be
controlled by external input pulse in gate terminal. After gate triggered, the
counter starts count down. When the counter has completed counting, output
signal would be available at the out terminal.
Schematic block diagram of intel 8253 timer/counter
 Pin diagram of 8253
The programmer can program 8253 using software in any one of the six
operating modes: Mode 0, Mode 1, Mode 2, Mode 3, Mode 4, and Mode 5.
The pin diagram of 8253 Programmable Interval Timer is shown in Fig.
8.76 and Fig. 8.77. The functional descriptions of pins are as follows:
 . Pin diagram of 8253
R̅ D̅ (Read) When this pin is low, the CPU is inputting data in the counter.
W̅ R̅ (Write) When this is low, the CPU is outputting data in the form of
mode information or loading of counters.
A0, A1 These pins are normally connected to the address bus. The function of
these
pins is used to select one of the three counters to be operated and to
address the control word registers for mode selection as given below:
 8253 control word register selection
A1 A0 Selection of counters and control word
register
0 0 Counter 0

0 1 Counter 1

1 0 Counter 2

1 1 Control Word Register

C̅ S̅ Chip select A ‘low’ on C̅ S̅ input enables the 8253. No reading or

writing operation will be performed until the device is selected. The C̅ S̅
input signal is not used to control the actual operation of the counters.
Data Bus Buffer The 3-state, bi-directional, 8-bit buffers exist in 8253.
These
buffers are used to interface the 8253 to the systems data bus D0-D7 lines.

Data can be transmitted or received by the buffer upon execution of input

and output CPU instructions. The data bus buffer has three basic functions,
namely, programming the Modes of the 8253, loading the count registers
and reading the count values.
D0-D7 Bi-directional Data Bus There are eight data lines through which the
 Read/Write Logic The read/write Logic accepts inputs from the system bus
and in turn Gate generates control signals for operation of 8253. This is
enabled by C̅ S̅ . Therefore, no operation can take place to change the
function unless the device has been selected by the system logic. Table 8.15
shows the various functions of 8253 Programmable Interval Timer based on
the status of pins associated with read/write logic.
Functions of 8253
̅𝐶𝑆̅̅ ̅ ̅𝑅𝐷
̅̅ ̅ ̅𝑊̅̅ 𝑅
̅ ̅ A1 A0 Function
0 1 0 0 0 Load counter 0
0 1 0 0 1 Load counter 1
0 1 0 1 0 Load counter 2
0 1 0 1 1 Write mode word
0 0 1 0 0 Read counter 0
0 0 1 0 1 Read counter 1
0 0 1 1 0 Read counter 2
0 0 1 1 1 No operation 3-state
1 × × × × Disable 3 state
0 1 1 × × No operation 3-state